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[Qemu-commits] [qemu/qemu] 452e3d: target-tricore: Add missing ULL suffi

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 452e3d: target-tricore: Add missing ULL suffix on 64 bit c...
Date: Tue, 27 Jan 2015 05:00:08 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 452e3d49d871f311f7b884dc69160c3e0973b050
      
https://github.com/qemu/qemu/commit/452e3d49d871f311f7b884dc69160c3e0973b050
  Author: Peter Maydell <address@hidden>
  Date:   2015-01-26 (Mon, 26 Jan 2015)

  Changed paths:
    M target-tricore/op_helper.c

  Log Message:
  -----------
  target-tricore: Add missing ULL suffix on 64 bit constant

Add a missing ULL suffix to a 64 bit constant: this suppresses a
compiler warning from mingw32 gcc.

Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 5f30046f156c181fb4088da2f4b8ea25a7d07c7a
      
https://github.com/qemu/qemu/commit/5f30046f156c181fb4088da2f4b8ea25a7d07c7a
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-26 (Mon, 26 Jan 2015)

  Changed paths:
    M target-tricore/cpu.c
    M target-tricore/op_helper.c
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Several translator and cpu model fixes

Fix tc1796 cpu model using wrong ISA version.
Fix cond_add sometimes writing back wrong result.
Fix RCR_SEL and RCR_SELN using wrong registers for result and cond.

Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 811ea608e9721dc4f6933da440f235e7d3a39c0f
      
https://github.com/qemu/qemu/commit/811ea608e9721dc4f6933da440f235e7d3a39c0f
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-26 (Mon, 26 Jan 2015)

  Changed paths:
    M target-tricore/op_helper.c

  Log Message:
  -----------
  target-tricore: calculate av bits before saturation

64 bit mac instructions calculated the av bits after the saturation, which
resulted in a wrong PSW. This moves the av bit calculation before the
saturation.

Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 40a1f64b468ee247fca3b237f0b89f066e59626c
      
https://github.com/qemu/qemu/commit/40a1f64b468ee247fca3b237f0b89f066e59626c
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-26 (Mon, 26 Jan 2015)

  Changed paths:
    M target-tricore/cpu.h
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Fix bugs found by coverity

This fixes one bug and one false positive found by coverity. The bug is,
that gen_mtcr was missing a mask to check the flag, which resulted in dead code.

The false positive is a intentional missing break for a jump and link address
insn followed by a jump and link insn. This adds a fall through comment to avoid
the false positive in the future.

Reported-by: Markus Armbruster <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 85d604af5f96c32734af9974ec6ddb625b6716a2
      
https://github.com/qemu/qemu/commit/85d604af5f96c32734af9974ec6ddb625b6716a2
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-26 (Mon, 26 Jan 2015)

  Changed paths:
    M target-tricore/op_helper.c

  Log Message:
  -----------
  target-tricore: split up suov32 into suov32_pos and suov32_neg

suov checks unsigned for an overflow and an underflow, after some arithmetic
operations and saturates the result to either max_uint32 or 0. So far we
handled this by expanding to the next bigger data type and compare whether
the result is > max_uint32 or < 0.

However this approach can fail for an 32 bit multiplication, if both operands of
the multiplication are 0x80000000. This sets the sign bit of the 64 bit integer
and would result in a false saturation to 0.

Since unsigned operations, e.g add, sub, mul always result in either a positive
or negative overflow, we split the functions for suov32 up into two functions
(suov32_pos, suov32_neg) for each case.

Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: f1cc6eafdd08817a234e0e1a9c8f03177a31faf1
      
https://github.com/qemu/qemu/commit/f1cc6eafdd08817a234e0e1a9c8f03177a31faf1
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-27 (Tue, 27 Jan 2015)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RR1 opcode format, that have 0x93 as 
first opcode

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 12f323e66e2d850b0e27300d609deae6e7290457
      
https://github.com/qemu/qemu/commit/12f323e66e2d850b0e27300d609deae6e7290457
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-27 (Tue, 27 Jan 2015)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RR2 opcode format

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 8fb9d0eb68376363553d81525cc526842543e2dc
      
https://github.com/qemu/qemu/commit/8fb9d0eb68376363553d81525cc526842543e2dc
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-27 (Tue, 27 Jan 2015)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RRPW opcode format

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 0953225588ee30de2e92485331ad1bb3d7c7d089
      
https://github.com/qemu/qemu/commit/0953225588ee30de2e92485331ad1bb3d7c7d089
  Author: Bastian Koppelmann <address@hidden>
  Date:   2015-01-27 (Tue, 27 Jan 2015)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RRR opcode format

Add microcode generator function gen_cond_sub.

Add helper functions:
    * ixmax/ixmin: search for the max/min value and its related index in a
             vector of 16-bit values.
    * pack: dack two data registers into an IEEE-754 single precision floating
      point format number.
    * dvadj: divide-adjust the result after dvstep instructions.
    * dvstep: divide a reg by a divisor, producing 8-bits of quotient at a time.

OPCM_32_RRR_FLOAT -> OPCM_32_RRR_DIVIDE

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 7baef630732a50fcbb7ca5b1e9cc0ecf4f2998c9
      
https://github.com/qemu/qemu/commit/7baef630732a50fcbb7ca5b1e9cc0ecf4f2998c9
  Author: Peter Maydell <address@hidden>
  Date:   2015-01-27 (Tue, 27 Jan 2015)

  Changed paths:
    M target-tricore/cpu.c
    M target-tricore/cpu.h
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150127' 
into staging

tricore bugfixes and RR1, RR2, RRPW and RRR insn

# gpg: Signature made Tue 27 Jan 2015 12:02:06 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"

* remotes/bkoppelmann/tags/pull-tricore-20150127:
  target-tricore: Add instructions of RRR opcode format
  target-tricore: Add instructions of RRPW opcode format
  target-tricore: Add instructions of RR2 opcode format
  target-tricore: Add instructions of RR1 opcode format, that have 0x93 as 
first opcode
  target-tricore: split up suov32 into suov32_pos and suov32_neg
  target-tricore: Fix bugs found by coverity
  target-tricore: calculate av bits before saturation
  target-tricore: Several translator and cpu model fixes
  target-tricore: Add missing ULL suffix on 64 bit constant

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1ac0206b2ae1...7baef630732a
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