[Qemu-commits] [qemu/qemu] 781b71: target-tricore: fix offset masking in BOL format

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 781b717c5049f42d45d31fd47617f3129c07541c
      
https://github.com/qemu/qemu/commit/781b717c5049f42d45d31fd47617f3129c07541c
  Author: Alex Zuepke <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: fix offset masking in BOL format

Signed-off-by: Alex Zuepke <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: af715d980271a1c8ea9596bf9147b5421a49e01a
      
https://github.com/qemu/qemu/commit/af715d980271a1c8ea9596bf9147b5421a49e01a
  Author: Alex Zuepke <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: typo in BOL format

Signed-off-by: Alex Zuepke <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 4b5b44357651b7563790e246be64bc55f4d90d47
      
https://github.com/qemu/qemu/commit/4b5b44357651b7563790e246be64bc55f4d90d47
  Author: Alex Zuepke <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: add missing 64-bit MOV in RLC format

Signed-off-by: Alex Zuepke <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 45820fccaf731a2fec5d0cb5416f944104e89373
      
https://github.com/qemu/qemu/commit/45820fccaf731a2fec5d0cb5416f944104e89373
  Author: Alex Zuepke <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: pretty-print register dump and show more status registers

Now using psw_read() to retrieve the status bits correctly.

Signed-off-by: Alex Zuepke <address@hidden>
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: 7f13420ec000ad7644b65ea1a32b5674ad0cd204
      
https://github.com/qemu/qemu/commit/7f13420ec000ad7644b65ea1a32b5674ad0cd204
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Fix mask handling JNZ.T being 7 bit long

The mask is actually 7 bit long, instead of 6, so the expression checking
for JNZ.T is always false. Let's make the mask 1 bit wider.

Signed-off-by: Bastian Koppelmann <address@hidden>


  Commit: e4e39176305adff59b05a02a072ae1369d0a2274
      
https://github.com/qemu/qemu/commit/e4e39176305adff59b05a02a072ae1369d0a2274
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/op_helper.c

  Log Message:
  -----------
  target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32

Those makros are exclusively used for 32 bit arithmetics and won't work for
16 bit with two halfwords. So lets get rid of the len parameter and make them
always use 32 bit. Now no token pasting is needed anymore and they can be
regular functions.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: d5de7839d78b08c7bd14b03dac0413699b90da67
      
https://github.com/qemu/qemu/commit/d5de7839d78b08c7bd14b03dac0413699b90da67
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RR opcode format, that have 0xb as the 
first opcode

Add instructions of RR opcode format, that have 0xb as the first opcode.
Add helper functions, for hword and byte arithmetics:
    * add_h_ssov/suov: Add two halfword and saturate on overflow.
    * sub_h_ssov/suov: Sub two halfword and saturate on overflow.
    * absdif_h_ssov: Compute absolute difference for halfwords and saturate on 
overflow.
    * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on 
overflow.
    * abs_b/h: Compute absolute value for four/two bytes/halfwords
    * absdif_b/h: Compute absolute difference for four/two bytes/halfwords
    * add_b/h: Add four/two bytes/halfwords.
    * sub_b/h: Sub four/two bytes/halfwords.
    * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on
        equality and set all bits of to either one ore zero.
    * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords 
on equality.
    * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two 
bytes/halfwords
              on less than signed and unsigned.
    * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and 
unsigned.
    * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and 
unsigned.
Add helper function abs_ssov, that computes the absolute value for a 32 bit 
integer and saturates on overflow.
Add microcode generator functions:
    * gen_sub_CC: Caluclates sub and sets the carry bit.
    * gen_subc_CC: Caluclates sub and carry and sets the carry bit
    * gen_abs: Compute absolute value for a 32 bit integer.
    * gen_cond_w: Compares two 32 bit values on cond and sets result either 
zero or all bits one.

OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 0b79a78169d813d11ad32f103e7a2c64c32bd705
      
https://github.com/qemu/qemu/commit/0b79a78169d813d11ad32f103e7a2c64c32bd705
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RR opcode format, that have 0xf as the 
first opcode

Add instructions of RR opcode format, that have 0xf as the first opcode.
Add helper functions:
    * clo/z/s: Counts leading ones/zeros/signs.
    * clo/z/s_h: Count leading ones/zeros/signs in two haflwords.
    * sh/_h: Shifts one/two word/hwords.
    * sha/_h: Shifts one/two word/hwords arithmeticly.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: f2f1585f60df656dc1755727cc66a0c3c8dd627d
      
https://github.com/qemu/qemu/commit/f2f1585f60df656dc1755727cc66a0c3c8dd627d
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RR opcode format, that have 0x1 as the 
first opcode

Add instructions of RR opcode format, that have 0x1 as the first opcode.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e2bed107c6d1dbde564029ac2bca450cdb3f596e
      
https://github.com/qemu/qemu/commit/e2bed107c6d1dbde564029ac2bca450cdb3f596e
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RR opcode format, that have 0x4b as the 
first opcode

Add instructions of RR opcode format, that have 0x4b as the first opcode.
Add helper functions:
    * parity: Calculates the parity bits for every byte of a 32 int.
    * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two 
bitwise.
    * unpack: unpack a IEEE 754 single precision floating point number as 
exponent and mantissa.
    * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
                 where the quotient result is guaranteed to fit into 8 bit.
    * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
                 where the quotient result is guaranteed to fit into 16 bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: b5fd8fa34594da327e2965a8c3b5dddf21f862ff
      
https://github.com/qemu/qemu/commit/b5fd8fa34594da327e2965a8c3b5dddf21f862ff
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add missing 1.6 insn of BOL opcode format

Some of the 1.6 ISA instructions were still missing. So let's add them.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 436d63ff3e3f87cda3e8df35827a40093cc17430
      
https://github.com/qemu/qemu/commit/436d63ff3e3f87cda3e8df35827a40093cc17430
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Fix MFCR/MTCR insn and B format offset.

Fix gen_mtcr using wrong register.
Fix gen_mtcr/mfcr using sign extended offsets.
Fix B format insn using not sign extendend offsets.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 9655b9328a566116c198c52792775a0641d56915
      
https://github.com/qemu/qemu/commit/9655b9328a566116c198c52792775a0641d56915
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-21 (Sun, 21 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as 
first opcode

Add instructions of RR1 opcode format, that have 0xb3 as first opcode.
Add helper functions mulh, mulmh and mulrh, that compute multiplication,
with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either 
low or high parts
of two 32 bit regs.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 7db96d6cf877d4bb8132462ec7dd19055ff968eb
      
https://github.com/qemu/qemu/commit/7db96d6cf877d4bb8132462ec7dd19055ff968eb
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-22 (Mon, 22 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20141221' 
into staging

TriCore RR, RR1 insn added and several bug fixes

# gpg: Signature made Sun 21 Dec 2014 18:39:11 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"

* remotes/bkoppelmann/tags/pull-tricore-20141221:
  target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as 
first opcode
  target-tricore: Fix MFCR/MTCR insn and B format offset.
  target-tricore: Add missing 1.6 insn of BOL opcode format
  target-tricore: Add instructions of RR opcode format, that have 0x4b as the 
first opcode
  target-tricore: Add instructions of RR opcode format, that have 0x1 as the 
first opcode
  target-tricore: Add instructions of RR opcode format, that have 0xf as the 
first opcode
  target-tricore: Add instructions of RR opcode format, that have 0xb as the 
first opcode
  target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32
  target-tricore: Fix mask handling JNZ.T being 7 bit long
  target-tricore: pretty-print register dump and show more status registers
  target-tricore: add missing 64-bit MOV in RLC format
  target-tricore: typo in BOL format
  target-tricore: fix offset masking in BOL format

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c95f3901b4ea...7db96d6cf877