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[Qemu-commits] [qemu/qemu] 3fb763: target-tricore: Add instructions of B

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 3fb763: target-tricore: Add instructions of BOL opcode for...
Date: Thu, 11 Dec 2014 04:30:06 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 3fb763cb55c282a686e22b7639ff6615d527bb10
      
https://github.com/qemu/qemu/commit/3fb763cb55c282a686e22b7639ff6615d527bb10
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of BOL opcode format

Add instructions of BOL opcode format.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: fc2ef4a391c39688d35c7f78cec6a20d552e5a3b
      
https://github.com/qemu/qemu/commit/fc2ef4a391c39688d35c7f78cec6a20d552e5a3b
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of BRC opcode format

Add instructions of BRC opcode format.
Fixed OP2_BRC_JGE -> OP2_32_BRC_JGE

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 83c1bb1868848912f3d5516880e937cb247dfcd1
      
https://github.com/qemu/qemu/commit/83c1bb1868848912f3d5516880e937cb247dfcd1
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of BRN opcode format

Add instructions of BRN opcode format.
Add MASK_OP_BRN_DISP15_SEXT.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: a68e0d547f042f1d75f4d56ca5b6c4cc719d7077
      
https://github.com/qemu/qemu/commit/a68e0d547f042f1d75f4d56ca5b6c4cc719d7077
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of BRR opcode format

Add instructions of BRR opcode format.
Add MASK_OP_BRR_DISP15_SEXT.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 0974257ed58ff3e9512d74ffa5b4039bbec49b2d
      
https://github.com/qemu/qemu/commit/0974257ed58ff3e9512d74ffa5b4039bbec49b2d
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RC opcode format

Add instructions of RC opcode format.
Add helper for mul, sha, absdif with signed saturation on overflow.
Add helper for add, sub, mul with unsigned saturation on overflow.
Add microcode generator functions:
    * gen_add_CC, which calculates the carry bit.
    * gen_addc_CC, which adds the carry bit to the add and calculates the carry 
bit.
    * gen_absdif, which calculates the absolute difference.
    * gen_mul_i64s/u, which mul two 32 bits val into one 64bit reg.
    * gen_sh_hi, which shifts two 16bit words in one reg.
    * gen_sha_hi, which does a arithmetic shift on two 16bit words.
    * gen_sh_cond, which shifts left a reg by one and writes the result of cond 
into the lsb.
    * gen_accumulating_cond, which ands/ors/xors the result of cond of the lsbs
      with the lsb of the result.
    * gen_eqany_bi/hi, which checks ever byte/hword on equality.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 47e04430ed3e6ab835f023a5c84381ca2ce9f4d8
      
https://github.com/qemu/qemu/commit/47e04430ed3e6ab835f023a5c84381ca2ce9f4d8
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/cpu.c
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Make TRICORE_FEATURES implying others.

Since all the TriCore instructionsets are subsets of each other (1.3 C 1.3.1 C 
1.6),
make the features implying each other, e.g 1.6 also has 1.3.1 and 1.3. This way
we only need to check our features for the instructionset, where a instruction 
was first introduced.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: ed51626066ea40092335f653780b6d1ca22c574a
      
https://github.com/qemu/qemu/commit/ed51626066ea40092335f653780b6d1ca22c574a
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/translate.c

  Log Message:
  -----------
  target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format

Add instructions of RCPW, RCRR and RCRW opcode format.
Add microcode generator function gen_insert.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 2b2f7d97d856a4e7020d881ec1e6e60be64d0ab6
      
https://github.com/qemu/qemu/commit/2b2f7d97d856a4e7020d881ec1e6e60be64d0ab6
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    A target-tricore/csfr.def
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RLC opcode format

Add instructions of RLC opcode format.
Add helper psw_write/read.
Add microcode generator gen_mtcr/mfcr, which loads/stores a value to a core 
special function register, which are defined in csfr.def

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 328f1f0f08f1aa303eef7493bd7c3d97a8d9636a
      
https://github.com/qemu/qemu/commit/328f1f0f08f1aa303eef7493bd7c3d97a8d9636a
  Author: Bastian Koppelmann <address@hidden>
  Date:   2014-12-10 (Wed, 10 Dec 2014)

  Changed paths:
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  target-tricore: Add instructions of RCR opcode format

Add instructions of RCR opcode format.
Add helper for madd32/64_ssov and madd32/64_suov.
Add helper for msub32/64_ssov and msub32/64_suov.
Add microcode generator function madd/msub for 32bit and 64bit, which calculate 
a mul and a add/sub.
OPC2_32_RCR_MSUB_U_32 -> OPC2_32_RCR_MSUB_U_32.

Signed-off-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: a09f2d16f6b9f5bcdedb4d116bb54da86e9a3f6e
      
https://github.com/qemu/qemu/commit/a09f2d16f6b9f5bcdedb4d116bb54da86e9a3f6e
  Author: Peter Maydell <address@hidden>
  Date:   2014-12-11 (Thu, 11 Dec 2014)

  Changed paths:
    M target-tricore/cpu.c
    A target-tricore/csfr.def
    M target-tricore/helper.h
    M target-tricore/op_helper.c
    M target-tricore/translate.c
    M target-tricore/tricore-opcodes.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20141210' 
into staging

TriCore BOL, BRC, BRN, BRR, RC, RCPW, RCRR, RCR, RLC and RCR insn added

# gpg: Signature made Wed 10 Dec 2014 11:21:58 GMT using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <address@hidden>"

* remotes/bkoppelmann/tags/pull-tricore-20141210:
  target-tricore: Add instructions of RCR opcode format
  target-tricore: Add instructions of RLC opcode format
  target-tricore: Add instructions of RCPW, RCRR and RCRW opcode format
  target-tricore: Make TRICORE_FEATURES implying others.
  target-tricore: Add instructions of RC opcode format
  target-tricore: Add instructions of BRR opcode format
  target-tricore: Add instructions of BRN opcode format
  target-tricore: Add instructions of BRC opcode format
  target-tricore: Add instructions of BOL opcode format

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/67a5eebca1ac...a09f2d16f6b9
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