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[Qemu-commits] [qemu/qemu] e98c0d: target-mips: add KScratch registers

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] e98c0d: target-mips: add KScratch registers
Date: Tue, 04 Nov 2014 05:00:10 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e98c0d179fe43adb99a39b7bf7c74820adc3c0ca
      
https://github.com/qemu/qemu/commit/e98c0d179fe43adb99a39b7bf7c74820adc3c0ca
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add KScratch registers

KScratch<n> Registers (CP0 Register 31, Selects 2 to 7)

The KScratch registers are read/write registers available for scratch pad
storage by kernel mode software. They are 32-bits in width for 32-bit
processors and 64-bits for 64-bit processors.

CP0Config4.KScrExist[2:7] bits indicate presence of CP0_KScratch1-6 registers.
For Release 6, all KScratch registers are required.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 55e9409366c5b7954a5dfb3efec9b191c238dd12
      
https://github.com/qemu/qemu/commit/55e9409366c5b7954a5dfb3efec9b191c238dd12
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M include/exec/cpu-common.h
    M softmmu_template.h

  Log Message:
  -----------
  softmmu: provide softmmu access type enum

New MIPS features depend on the access type and enum is more convenient than
using the numbers directly.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>


  Commit: 9f6bcedba61927438000fb94b0706c22dfb87eaa
      
https://github.com/qemu/qemu/commit/9f6bcedba61927438000fb94b0706c22dfb87eaa
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.c

  Log Message:
  -----------
  target-mips: distinguish between data load and instruction fetch

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 2fb58b73746e2f99ac85e82160277b18b18279be
      
https://github.com/qemu/qemu/commit/2fb58b73746e2f99ac85e82160277b18b18279be
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: add RI and XI fields to TLB entry

In Revision 3 of the architecture, the RI and XI bits were added to the TLB
to enable more secure access of memory pages. These bits (along with the Dirty
bit) allow the implementation of read-only, write-only, no-execute access
policies for mapped pages.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 7207c7f9d74816c32783a394d8072d1f978157ac
      
https://github.com/qemu/qemu/commit/7207c7f9d74816c32783a394d8072d1f978157ac
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}

PageGrain needs rw bitmask which differs between MIPS architectures.
In pre-R6 if RIXI is supported, PageGrain.XIE and PageGrain.RIE are writeable,
whereas in R6 they are read-only 1.

On MIPS64 mtc0 instruction left shifts bits 31:30 for MIPS32 backward
compatiblity, therefore there are separate mtc0 and dmtc0 helpers.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 92ceb440d47b9ef3ba860cdc75a7e31563a7dc0c
      
https://github.com/qemu/qemu/commit/92ceb440d47b9ef3ba860cdc75a7e31563a7dc0c
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c

  Log Message:
  -----------
  target-mips: add new Read-Inhibit and Execute-Inhibit exceptions

An Execute-Inhibit exception occurs when the virtual address of an instruction
fetch matches a TLB entry whose XI bit is set. This exception type can only
occur if the XI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain XIE bit.

An Read-Inhibit exception occurs when the virtual address of a memory load
reference matches a TLB entry whose RI bit is set. This exception type can
only occur if the RI bit is implemented within the TLB and is enabled, this is
denoted by the PageGrain RIE bit.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 9456c2fbcd82dd82328ac6e7602a815582b1043e
      
https://github.com/qemu/qemu/commit/9456c2fbcd82dd82328ac6e7602a815582b1043e
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M disas/mips.c
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add TLBINV support

For Standard TLB configuration (Config.MT=1):

TLBINV invalidates a set of TLB entries based on ASID. The virtual address is
ignored in the entry match. TLB entries which have their G bit set to 1 are not
modified.

TLBINVF causes all entries to be invalidated.

Single TLB entry can be marked as invalid on TLB entry write by having
EntryHi.EHINV set to 1.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: aea14095ea91f792ee43ee52fe6032cd8cdd7190
      
https://github.com/qemu/qemu/commit/aea14095ea91f792ee43ee52fe6032cd8cdd7190
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add BadInstr and BadInstrP support

BadInstr Register (CP0 Register 8, Select 1)
The BadInstr register is a read-only register that capture the most recent
instruction which caused an exception.

BadInstrP Register (CP0 Register 8, Select 2)
The BadInstrP register contains the prior branch instruction, when the
faulting instruction is in a branch delay slot.

Using error_code to indicate whether AdEL or TLBL was triggered during
instruction fetch, in this case BadInstr is not updated as valid instruction
word is not available.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 460c81f14a74f671d14bad3a3fb4502292d7a355
      
https://github.com/qemu/qemu/commit/460c81f14a74f671d14bad3a3fb4502292d7a355
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/machine.c

  Log Message:
  -----------
  target-mips: update cpu_save/cpu_load to support new registers

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: faf1f68ba11c919191dd7a5f32cfd0b6401c4827
      
https://github.com/qemu/qemu/commit/faf1f68ba11c919191dd7a5f32cfd0b6401c4827
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add Config5.SBRI

SDBBP instruction Reserved Instruction control. The purpose of this field is
to restrict availability of SDBBP to kernel mode operation.

If the bit is set then SDBBP instruction can only be executed in kernel mode.
User execution of SDBBP will cause a Reserved Instruction exception.

Additionally add missing Config4 and Config5 cases for dm{f,t}c0.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 339cd2a82aca031370cd71b1118a5565dc2af0a9
      
https://github.com/qemu/qemu/commit/339cd2a82aca031370cd71b1118a5565dc2af0a9
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: implement forbidden slot

When conditional compact branch is encountered decode one more instruction in
current translation block - that will be forbidden slot. Instruction in
forbidden slot will be executed only if conditional compact branch is not taken.

Any control transfer instruction (CTI) which are branches, jumps, ERET,
DERET, WAIT and PAUSE will generate RI exception if executed in forbidden or
delay slot.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: a63eb0ce0f5c43cf022022c5f4860aaf4f292a06
      
https://github.com/qemu/qemu/commit/a63eb0ce0f5c43cf022022c5f4860aaf4f292a06
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h

  Log Message:
  -----------
  target-mips: CP0_Status.CU0 no longer allows the user to access CP0

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: ba801af429aaa68f6cc03842c8b6be81a6ede65a
      
https://github.com/qemu/qemu/commit/ba801af429aaa68f6cc03842c8b6be81a6ede65a
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: add restrictions for possible values in registers

In Release 6 not all the values are allowed to be written to a register.
If the value is not valid or unsupported then it should stay unchanged.

For pre-R6 the existing behaviour has been changed only for CP0_Index register
as the current implementation does not seem to be correct - it looks like it
tries to limit the input value but the limit is higher than the actual
number of tlb entries.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: f31b035a9f10dc9b57f01c426110af845d453ce2
      
https://github.com/qemu/qemu/commit/f31b035a9f10dc9b57f01c426110af845d453ce2
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: correctly handle access to unimplemented CP0 register

Release 6 limits the number of cases where software can cause UNDEFINED or
UNPREDICTABLE behaviour. In this case, when accessing reserved / unimplemented
CP0 register, writes are ignored and reads return 0.

In pre-R6 the behaviour is not specified, but generating RI exception is not
what the real HW does.

Additionally, remove CP0 Random register as it became reserved in Release 6.

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: 2d9e48bc041d9281f305ee82ae97776eb5ef0aab
      
https://github.com/qemu/qemu/commit/2d9e48bc041d9281f305ee82ae97776eb5ef0aab
  Author: Leon Alrae <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: enable features in MIPS64R6-generic CPU

Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>


  Commit: e97a391d201c0a7ae4dfd3bb90890191f0e24780
      
https://github.com/qemu/qemu/commit/e97a391d201c0a7ae4dfd3bb90890191f0e24780
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/mips-defs.h
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: add MSA defines and data structure

add defines and data structure for MIPS SIMD Architecture

Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b10ac20446019c7df77e51a30ed902b87fad8ec3
      
https://github.com/qemu/qemu/commit/b10ac20446019c7df77e51a30ed902b87fad8ec3
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.c

  Log Message:
  -----------
  target-mips: add MSA exceptions

add MSA exceptions

Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: b7651e95218d92f84b9602940c6412911372cd3b
      
https://github.com/qemu/qemu/commit/b7651e95218d92f84b9602940c6412911372cd3b
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/gdbstub.c
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: remove duplicated mips/ieee mapping function

Remove the duplicated ieee_rm in gdbstub.c.
Make the other ieee_rm and ieee_ex_to_mips available to other files.

Reviewed-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 4cf8a45f56b71d474c33c5d8c2f9e39c4476a3d3
      
https://github.com/qemu/qemu/commit/4cf8a45f56b71d474c33c5d8c2f9e39c4476a3d3
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: stop translation after ctc1

stop translation as ctc1 instruction can change hflags

Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 239dfebe124f160ae4c3e4d6aa54dc13cc1f2c08
      
https://github.com/qemu/qemu/commit/239dfebe124f160ae4c3e4d6aa54dc13cc1f2c08
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA opcode enum

add MSA opcode enum

Reviewed-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 863f264d10f917a8c3b2f8f6c3f78d0189fa48e7
      
https://github.com/qemu/qemu/commit/863f264d10f917a8c3b2f8f6c3f78d0189fa48e7
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add msa_reset(), global msa register

add msa_reset() and global msa register (d type only)

Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 42daa9bed40baaec86329e72768f310b8ca9b601
      
https://github.com/qemu/qemu/commit/42daa9bed40baaec86329e72768f310b8ca9b601
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/Makefile.objs
    A target-mips/msa_helper.c

  Log Message:
  -----------
  target-mips: add msa_helper.c

add msa_helper.c

Reviewed-by: James Hogan <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 5692c6e1f8ac1ed883076dec7dd14065b8df27dd
      
https://github.com/qemu/qemu/commit/5692c6e1f8ac1ed883076dec7dd14065b8df27dd
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA branch instructions

add MSA branch instructions

Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 4c7895465e069b204e8eb4731ac7f37cd3b1a4eb
      
https://github.com/qemu/qemu/commit/4c7895465e069b204e8eb4731ac7f37cd3b1a4eb
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA I8 format instructions

add MSA I8 format instructions

Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 80e7159184fadfc2dee3b6cc92013d4c4c58348a
      
https://github.com/qemu/qemu/commit/80e7159184fadfc2dee3b6cc92013d4c4c58348a
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA I5 format instruction

add MSA I5 format instructions

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d4cf28dec265f2f8a25ddbe818b1da62e174bcfa
      
https://github.com/qemu/qemu/commit/d4cf28dec265f2f8a25ddbe818b1da62e174bcfa
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA BIT format instructions

add MSA BIT format instructions

Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 28f99f08cf9a5ceb01704d84834dfac0f5635866
      
https://github.com/qemu/qemu/commit/28f99f08cf9a5ceb01704d84834dfac0f5635866
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA 3R format instructions

add MSA 3R format instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 1e608ec14e0a0e9b57a889365fc8739043a46527
      
https://github.com/qemu/qemu/commit/1e608ec14e0a0e9b57a889365fc8739043a46527
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA ELM format instructions

add MSA ELM format instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 7d05b9c86fa1b5620296eceed8c347815da8d688
      
https://github.com/qemu/qemu/commit/7d05b9c86fa1b5620296eceed8c347815da8d688
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA 3RF format instructions

add MSA 3RF format instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: cbe50b9a8e70eff6fead3f4bfc7a76e3db70c56c
      
https://github.com/qemu/qemu/commit/cbe50b9a8e70eff6fead3f4bfc7a76e3db70c56c
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA VEC/2R format instructions

add MSA VEC/2R format instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 3bdeb68866ef2eb212b660381e080f412cc7c817
      
https://github.com/qemu/qemu/commit/3bdeb68866ef2eb212b660381e080f412cc7c817
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/msa_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA 2RF format instructions

add MSA 2RF format instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: f7685877f596cfe7e873be5479f975ae985edba9
      
https://github.com/qemu/qemu/commit/f7685877f596cfe7e873be5479f975ae985edba9
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: add MSA MI10 format instructions

add MSA MI10 format instructions
update LSA and DLSA for MSA

add 16, 64 bit load and store

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: ed8a933f977e39fc696d92f0b9f93100319a8668
      
https://github.com/qemu/qemu/commit/ed8a933f977e39fc696d92f0b9f93100319a8668
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M disas/mips.c

  Log Message:
  -----------
  disas/mips.c: disassemble MSA instructions

disassemble MIPS SIMD Architecture instructions

Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: 55a2201e79d063766509ed2f2f2e8837b9e1facf
      
https://github.com/qemu/qemu/commit/55a2201e79d063766509ed2f2f2e8837b9e1facf
  Author: Yongbok Kim <address@hidden>
  Date:   2014-11-03 (Mon, 03 Nov 2014)

  Changed paths:
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add MSA support to mips32r5-generic

add MSA support to mips32r5-generic core definition

Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>


  Commit: d780615520c9c26871df9d4df72bed73ed6215fc
      
https://github.com/qemu/qemu/commit/d780615520c9c26871df9d4df72bed73ed6215fc
  Author: Peter Maydell <address@hidden>
  Date:   2014-11-04 (Tue, 04 Nov 2014)

  Changed paths:
    M disas/mips.c
    M include/exec/cpu-common.h
    M softmmu_template.h
    M target-mips/Makefile.objs
    M target-mips/cpu.h
    M target-mips/gdbstub.c
    M target-mips/helper.c
    M target-mips/helper.h
    M target-mips/machine.c
    M target-mips/mips-defs.h
    A target-mips/msa_helper.c
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141103' into staging

* remotes/lalrae/tags/mips-20141103: (34 commits)
  target-mips: add MSA support to mips32r5-generic
  disas/mips.c: disassemble MSA instructions
  target-mips: add MSA MI10 format instructions
  target-mips: add MSA 2RF format instructions
  target-mips: add MSA VEC/2R format instructions
  target-mips: add MSA 3RF format instructions
  target-mips: add MSA ELM format instructions
  target-mips: add MSA 3R format instructions
  target-mips: add MSA BIT format instructions
  target-mips: add MSA I5 format instruction
  target-mips: add MSA I8 format instructions
  target-mips: add MSA branch instructions
  target-mips: add msa_helper.c
  target-mips: add msa_reset(), global msa register
  target-mips: add MSA opcode enum
  target-mips: stop translation after ctc1
  target-mips: remove duplicated mips/ieee mapping function
  target-mips: add MSA exceptions
  target-mips: add MSA defines and data structure
  target-mips: enable features in MIPS64R6-generic CPU
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/949ca9e479c3...d780615520c9
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