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[Qemu-commits] [qemu/qemu] dec71d: target-xtensa: add definition for XTH
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[Qemu-commits] [qemu/qemu] dec71d: target-xtensa: add definition for XTHAL_INTTYPE_PR... |
Date: |
Mon, 03 Nov 2014 11:00:09 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: dec71d2d63b766136d5b6ded616dcc3fae18e97d
https://github.com/qemu/qemu/commit/dec71d2d63b766136d5b6ded616dcc3fae18e97d
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M target-xtensa/cpu.h
M target-xtensa/overlay_tool.h
Log Message:
-----------
target-xtensa: add definition for XTHAL_INTTYPE_PROFILING
There's new interrupt type in the recent Xtensa releases that may appear
in configuration overlay. Add definition so that new cores that use it
could be automatically imported.
Signed-off-by: Max Filippov <address@hidden>
Commit: 20303e42d4726018ee64798b4d3051cbe6eea9f8
https://github.com/qemu/qemu/commit/20303e42d4726018ee64798b4d3051cbe6eea9f8
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M tests/tcg/xtensa/Makefile
R tests/tcg/xtensa/linker.ld
A tests/tcg/xtensa/linker.ld.S
Log Message:
-----------
target-xtensa: tests: pre-process tests linker script
Xtensa cores have configurable interrupt vectors and endiannes. This
information is needed to link executable images correctly for a specific
core configuration. Instead of hard-coding dc232 defaults pull endianness,
number of high-priority interrupts and location of vectors from the core
configuration and pass it through the C preprocessor.
While at it clean up tabs and align the initial stack on 16 bytes.
Signed-off-by: Max Filippov <address@hidden>
Commit: c9e9521fcb840b14ec0ae9117b224ff8a71418da
https://github.com/qemu/qemu/commit/c9e9521fcb840b14ec0ae9117b224ff8a71418da
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M hw/xtensa/pic_cpu.c
Log Message:
-----------
target-xtensa: avoid duplicate timer interrupt delivery
Timer interrupt should be raised at the same cycle when CCOUNT equals
CCOMPARE. As cycles are counted in batches, timer interrupt is sent
every time CCOMPARE lies in the interval [old CCOUNT, new CCOUNT]. This
is wrong, because when new CCOUNT equals CCOMPARE interrupt is sent
twice, once for the upper interval boundary and once for the lower. Fix
that by excluding lower interval boundary from the condition.
This doesn't have user-visible effect, because CCOMPARE reload always
causes CCOUNT increment followed by current timer interrupt reset.
Signed-off-by: Max Filippov <address@hidden>
Commit: 25bda50a0c7241dcb247483af2b7f961632020cc
https://github.com/qemu/qemu/commit/25bda50a0c7241dcb247483af2b7f961632020cc
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M hw/arm/boot.c
M hw/core/loader.c
M hw/m68k/an5206.c
M hw/m68k/dummy_m68k.c
M hw/m68k/mcf5208.c
M hw/microblaze/boot.c
M hw/openrisc/openrisc_sim.c
M hw/ppc/e500.c
M hw/ppc/ppc440_bamboo.c
M hw/xtensa/xtfpga.c
M include/hw/loader.h
Log Message:
-----------
hw/core/loader: implement address translation in uimage loader
Such address translation is needed when load address recorded in uImage
is a virtual address. When the actual load address is requested, return
untranslated address: user that needs the translated address can always
apply translation function to it and those that need it untranslated
don't need to do the inverse translation.
Add translation function pointer and its parameter to uimage_load
prototype. Update all existing users.
No user-visible functional changes.
Cc: address@hidden
Signed-off-by: Max Filippov <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Commit: 6d2e4530532ca1dbb5e68bdcca12e10931bc6503
https://github.com/qemu/qemu/commit/6d2e4530532ca1dbb5e68bdcca12e10931bc6503
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M hw/xtensa/xtfpga.c
Log Message:
-----------
hw/xtensa/xtfpga: treat uImage load address as virtual
U-boot for xtensa always treats uImage load address as virtual address.
This is important when booting uImage on xtensa core with MMUv2, because
MMUv2 has fixed non-identity virtual-to-physical mapping after reset.
Always do virtual-to-physical translation of uImage load address and
load uImage at the translated address. This fixes booting uImage kernels
on dc232b and other MMUv2 cores.
Cc: address@hidden
Reported-by: Waldemar Brodkorb <address@hidden>
Signed-off-by: Max Filippov <address@hidden>
Commit: 9bea2e91a6dec2156416aed7a2d3ef93c3bdb922
https://github.com/qemu/qemu/commit/9bea2e91a6dec2156416aed7a2d3ef93c3bdb922
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
A target-xtensa/import_core.sh
Log Message:
-----------
target-xtensa: add core importing script
This script copies configuration and gdb information from the xtensa
configuration overlay archive and registers new xtensa core.
Signed-off-by: Max Filippov <address@hidden>
Commit: ab5824134fa92c3f7de4e307a8c7273c4729f328
https://github.com/qemu/qemu/commit/ab5824134fa92c3f7de4e307a8c7273c4729f328
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M target-xtensa/overlay_tool.h
Log Message:
-----------
target-xtensa: fix build for cores w/o windowed registers
Cores without windowed registers don't have window overflow/underflow
vectors. Move these vectors to a separate group defined conditionally.
Signed-off-by: Max Filippov <address@hidden>
Commit: 437a8c11c06f53ed3bcdcc3e5abc5d20b2d439bd
https://github.com/qemu/qemu/commit/437a8c11c06f53ed3bcdcc3e5abc5d20b2d439bd
Author: Max Filippov <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: update xtensa boards
- fix file names that were changed by the commit
b707ab7 hw/xtensa: remove extraneous xtensa_ prefix from file names
- mark OpenCores 10/100 Mbit MAC model as maintained.
Signed-off-by: Max Filippov <address@hidden>
Commit: eb5f222b5c125de1b47970c6096a3107ffe1d69b
https://github.com/qemu/qemu/commit/eb5f222b5c125de1b47970c6096a3107ffe1d69b
Author: Peter Maydell <address@hidden>
Date: 2014-11-03 (Mon, 03 Nov 2014)
Changed paths:
M MAINTAINERS
M hw/arm/boot.c
M hw/core/loader.c
M hw/m68k/an5206.c
M hw/m68k/dummy_m68k.c
M hw/m68k/mcf5208.c
M hw/microblaze/boot.c
M hw/openrisc/openrisc_sim.c
M hw/ppc/e500.c
M hw/ppc/ppc440_bamboo.c
M hw/xtensa/pic_cpu.c
M hw/xtensa/xtfpga.c
M include/hw/loader.h
M target-xtensa/cpu.h
A target-xtensa/import_core.sh
M target-xtensa/overlay_tool.h
M tests/tcg/xtensa/Makefile
R tests/tcg/xtensa/linker.ld
A tests/tcg/xtensa/linker.ld.S
Log Message:
-----------
Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into
staging
Xtensa fixes and improvements 2014-11-03:
- build fixes for cores w/o windowed registers and with profiling
interrupts;
- fix uImage load address for MMUv2 cores;
- add script for automatic core import from xtensa configuration overlay.
# gpg: Signature made Sun 02 Nov 2014 22:04:44 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <address@hidden>"
# gpg: aka "Max Filippov <address@hidden>"
* remotes/xtensa/tags/20141103-xtensa:
MAINTAINERS: update xtensa boards
target-xtensa: fix build for cores w/o windowed registers
target-xtensa: add core importing script
hw/xtensa/xtfpga: treat uImage load address as virtual
hw/core/loader: implement address translation in uimage loader
target-xtensa: avoid duplicate timer interrupt delivery
target-xtensa: tests: pre-process tests linker script
target-xtensa: add definition for XTHAL_INTTYPE_PROFILING
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/7135781f65f1...eb5f222b5c12
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