[Qemu-commits] [qemu/qemu] 7797a7: hmp: Remove "info pcmcia"

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 7797a73947d5c0e63dd5552b348cf66c384b4555
      
https://github.com/qemu/qemu/commit/7797a73947d5c0e63dd5552b348cf66c384b4555
  Author: Markus Armbruster <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M hmp-commands.hx
    M hw/ide/microdrive.c
    M hw/pcmcia/pxa2xx.c
    M include/hw/pcmcia.h
    M monitor.c
    M vl.c

  Log Message:
  -----------
  hmp: Remove "info pcmcia"

This command lists PCMCIA sockets and cards.  Only a few ARM boards
have sockets (akita, borzoi, connex, mainstone, spitz, terrier, tosa,
verdex, z2), the only card is the DSCM-1xxxx Hitachi Microdrive (qdev
"microdrive"), and it is only inserted during machine init, if ever.
So this command doesn't really tell anybody anything new so far.

Moreover, pcmcia_socket_unregister() has a use-after-free bug, flagged
by Coverity.  Has never been used, because there has never been code
to eject a PCMCIA card.

Not worth fixing & converting to QMP.  Remove it.

Signed-off-by: Markus Armbruster <address@hidden>
Acked-by: Luiz Capitulino <address@hidden>
Acked-by: Andreas Färber <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b32a950910bc03f2c012794b3215fc2de8f90de3
      
https://github.com/qemu/qemu/commit/b32a950910bc03f2c012794b3215fc2de8f90de3
  Author: Claudio Fontana <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: mark timer in fdt as v8-compatible

check if the first cpu is an armv8 cpu, and if so, put
arm,armv8-timer in the compatible string list.

Note that due to this check, this patch moves the creation
of the timer fdt node to after the cpu creation loop.

Signed-off-by: Claudio Fontana <address@hidden>
Message-id: address@hidden
[PMM: updated to list arm,armv8-timer first]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c6faa758e30c3563f22ffbee11bf206a3ee952c8
      
https://github.com/qemu/qemu/commit/c6faa758e30c3563f22ffbee11bf206a3ee952c8
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: register cpu reset handlers if using -bios

Move the registering of CPU reset handlers to before the point where
we leave the function in the -bios (not -kernel) case, so CPU reset
works correctly with -bios as well.

Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6aea44fc2b842e14de18006ed7609f4a90cd3bf4
      
https://github.com/qemu/qemu/commit/6aea44fc2b842e14de18006ed7609f4a90cd3bf4
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M disas/arm-a64.cc
    M disas/libvixl/README
    M disas/libvixl/a64/assembler-a64.h
    M disas/libvixl/a64/decoder-a64.cc
    M disas/libvixl/a64/decoder-a64.h
    M disas/libvixl/a64/disasm-a64.cc
    M disas/libvixl/a64/disasm-a64.h
    M disas/libvixl/a64/instructions-a64.cc
    M disas/libvixl/a64/instructions-a64.h
    A disas/libvixl/code-buffer.h
    M disas/libvixl/utils.cc
    M disas/libvixl/utils.h

  Log Message:
  -----------
  disas/libvixl: Update to libvixl 1.6

Update our copy of libvixl to upstream 1.6. There are no
changes of any particular interest to QEMU, so this is simply
keeping up with current upstream.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 7b95a50858502485b0e159a1adabfa9912214147
      
https://github.com/qemu/qemu/commit/7b95a50858502485b0e159a1adabfa9912214147
  Author: KONRAD Frederic <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M hw/intc/arm_gic.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  arm_gic: remove unused parameter.

This removes num_irq parameter from gic_init_irqs_and_distributor as it is not
used.

Signed-off-by: KONRAD Frederic <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 94cc44a9e51eabd67282b1691f882c31436df2c4
      
https://github.com/qemu/qemu/commit/94cc44a9e51eabd67282b1691f882c31436df2c4
  Author: Chen Gang <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M disas/libvixl/a64/instructions-a64.h

  Log Message:
  -----------
  disas/libvixl/a64/instructions-a64.h: Remove unused constants

The instructions-a64.h header defines a number of floating point
constants whose initializers are function calls. gcc 5 will warn
if these constants are not used by the C or C++ file which includes
the header, because they imply a runtime cost. Since for the files
QEMU uses from libvixl we don't use these constants at all, just
remove them.

Upstream intend to fix these by shifting to an 'extern const' in
the header plus definition in a suitable source file, so we can
drop this patch when we sync with the upcoming libvixl 1.7.

The related compiling error:

    CXX   disas/arm-a64.o
  In file included from /upstream/qemu/disas/libvixl/a64/disasm-a64.h:32:0,
             from disas/arm-a64.cc:20:
  disas/libvixl/a64/instructions-a64.h:98:13: error: 
'vixl::kFP32PositiveInfinity' defined but not used [-Werror=unused-variable]
   const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000);
         ^
  disas/libvixl/a64/instructions-a64.h:99:13: error: 
'vixl::kFP32NegativeInfinity' defined but not used [-Werror=unused-variable]
   const float kFP32NegativeInfinity = rawbits_to_float(0xff800000);
         ^
  disas/libvixl/a64/instructions-a64.h:100:14: error: 
'vixl::kFP64PositiveInfinity' defined but not used [-Werror=unused-variable]
   const double kFP64PositiveInfinity =
          ^
  disas/libvixl/a64/instructions-a64.h:102:14: error: 
'vixl::kFP64NegativeInfinity' defined but not used [-Werror=unused-variable]
   const double kFP64NegativeInfinity =
          ^
  disas/libvixl/a64/instructions-a64.h:107:21: error: 
'vixl::kFP64SignallingNaN' defined but not used [-Werror=unused-variable]
   static const double kFP64SignallingNaN =
                 ^
  disas/libvixl/a64/instructions-a64.h:109:20: error: 
'vixl::kFP32SignallingNaN' defined but not used [-Werror=unused-variable]
   static const float kFP32SignallingNaN = rawbits_to_float(0x7f800001);
                ^
  disas/libvixl/a64/instructions-a64.h:112:21: error: 'vixl::kFP64QuietNaN' 
defined but not used [-Werror=unused-variable]
   static const double kFP64QuietNaN =
                 ^
  disas/libvixl/a64/instructions-a64.h:114:20: error: 'vixl::kFP32QuietNaN' 
defined but not used [-Werror=unused-variable]
   static const float kFP32QuietNaN = rawbits_to_float(0x7fc00001);
                ^
  disas/libvixl/a64/instructions-a64.h:117:21: error: 'vixl::kFP64DefaultNaN' 
defined but not used [-Werror=unused-variable]
   static const double kFP64DefaultNaN =
                 ^
  disas/libvixl/a64/instructions-a64.h:119:20: error: 'vixl::kFP32DefaultNaN' 
defined but not used [-Werror=unused-variable]
   static const float kFP32DefaultNaN = rawbits_to_float(0x7fc00000);
                ^
  cc1plus: all warnings being treated as errors
  make: *** [disas/arm-a64.o] Error 1

Signed-off-by: Chen Gang <address@hidden>
[PMM: Rewrote the commit message a little]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 635117e71fc697824e82cc694ba4e44dda7a9216
      
https://github.com/qemu/qemu/commit/635117e71fc697824e82cc694ba4e44dda7a9216
  Author: Dr. David Alan Gilbert <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M hw/misc/omap_gpmc.c

  Log Message:
  -----------
  omap_gpmc.c: Remove duplicate assignment

This looks like an old merge error and should have no effect.
(Build tested only)

Found by Coccinelle using Julia Lawall's script:
https://lkml.org/lkml/2014/8/23/128

Signed-off-by: Dr. David Alan Gilbert <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 543486db353b53f3601d0b5abf652ab330261107
      
https://github.com/qemu/qemu/commit/543486db353b53f3601d0b5abf652ab330261107
  Author: Rob Herring <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: add powered off cpu state

Add tracking of cpu power state in order to support powering off of
cores in system emuluation. The initial state is determined by the
start-powered-off QOM property.

Signed-off-by: Rob Herring <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 0adf7d3cc3f724e1e9ce5aaa008bd9daeb490f19
      
https://github.com/qemu/qemu/commit/0adf7d3cc3f724e1e9ce5aaa008bd9daeb490f19
  Author: Rob Herring <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu64.c
    M target-arm/helper-a64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes

User mode emulation should never get interrupts and thus should not
use the system emulation exception handler function. Remove the reference,
and '#ifndef USER_MODE_ONLY' the function itself as well, so that we can add
system mode only functionality to it.

Signed-off-by: Rob Herring <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 3df53cdf5616c1a1760d1e9166446140aa4b82e6
      
https://github.com/qemu/qemu/commit/3df53cdf5616c1a1760d1e9166446140aa4b82e6
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/kvm-consts.h

  Log Message:
  -----------
  target-arm: add missing PSCI constants needed for PSCI emulation

This adds some PSCI function IDs and symbolic return codes that are needed
to implement PSCI emulation in TCG mode.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 394043384337d3e84fe92ecc83bd90b0dcd661d5
      
https://github.com/qemu/qemu/commit/394043384337d3e84fe92ecc83bd90b0dcd661d5
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/op_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers

SMC must UNDEF if EL3 is not implemented; similarly HVC UNDEFs
if EL2 is not implemented. Move the handling of this from
translate-a64.c into the pre_smc and pre_hvc helper functions.
This is necessary because use of these instructions for PSCI
takes precedence over this UNDEF case, and we can't tell if
this is a PSCI call until runtime.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 37e6456ef539b2c4d1b9438f3df90eb032a9618f
      
https://github.com/qemu/qemu/commit/37e6456ef539b2c4d1b9438f3df90eb032a9618f
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/internals.h
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Add support for A32 and T32 HVC and SMC insns

Add support for HVC and SMC instructions to the A32 and
T32 decoder. Using these for real exceptions to EL2 or EL3
is currently not supported (the do_interrupt routine does
not handle them) but we require the instruction support to
implement PSCI.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 98128601ac8ff23df8a4c48acff00f9614613463
      
https://github.com/qemu/qemu/commit/98128601ac8ff23df8a4c48acff00f9614613463
  Author: Rob Herring <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/Makefile.objs
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c
    A target-arm/psci.c

  Log Message:
  -----------
  target-arm: add emulation of PSCI calls for system emulation

Add support for handling PSCI calls in system emulation. Both version
0.1 and 0.2 of the PSCI spec are supported. Platforms can enable support
by setting the "psci-conduit" QOM property on the cpus to SMC or HVC
emulation and having a PSCI binding in their dtb.

Signed-off-by: Rob Herring <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: made system reset/off PSCI functions power down the CPU so
 we obey the PSCI API requirement never to return from them;
 rearranged how the code is plumbed into the exception system,
 so that we split "is this a valid call?" from "do the call"]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 211b016915210e2b860d495f2573cfe85ec2a5d1
      
https://github.com/qemu/qemu/commit/211b016915210e2b860d495f2573cfe85ec2a5d1
  Author: Rob Herring <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  arm/virt: enable PSCI emulation support for system emulation

Now that we have PSCI emulation, enable it for the virt platform.
This simplifies the virt machine a bit now that PSCI no longer
needs to be a KVM only feature.

Signed-off-by: Rob Herring <address@hidden>
Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 14e5f106073d67e5a00a8f29a017550b0436bde8
      
https://github.com/qemu/qemu/commit/14e5f106073d67e5a00a8f29a017550b0436bde8
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correct sense of the DCZID DZP bit

The DZP bit in the DCZID system register should be set if
the control bits which prohibit use of the DC ZVA instruction
have been set (it stands for Data Zero Prohibited). However
we had the sense of the test inverted; fix this so that the
bit reads correctly.

To avoid this regressing the behaviour of the user-mode
emulator, we must set the DZE bit in the SCTLR for that
config so that userspace continues to see DZP as zero (it
was getting the correct result by accident previously).

Reported-by: Christopher Covington <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Message-id: address@hidden


  Commit: 0e7b176ae01d5a664d4cbf619a7315819494e6cb
      
https://github.com/qemu/qemu/commit/0e7b176ae01d5a664d4cbf619a7315819494e6cb
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"

For the CPU type "any" (only used with linux-user) we were reporting
the L1Ip field as 0b00, which is reserved. Change this field to 0b10
instead, indicating a VIPT icache as the comment describes.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: 23adb8618caf24ab7cbb41fb2f27bad1c429cbda
      
https://github.com/qemu/qemu/commit/23adb8618caf24ab7cbb41fb2f27bad1c429cbda
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0

The ARM ARM requires that the FPINST and FPINST2 VFP control
registers are not accessible to code at EL0. We were already
correctly implementing this for reads of these registers; add
the missing check for the write code path.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: 0b7d409d428dcd606128c71d589f3a8469c9944f
      
https://github.com/qemu/qemu/commit/0b7d409d428dcd606128c71d589f3a8469c9944f
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: increase arrays of registers R13 & R14

Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 19e0fefa6f66adb5bd7d072a6b83dbb95f92db2d
      
https://github.com/qemu/qemu/commit/19e0fefa6f66adb5bd7d072a6b83dbb95f92db2d
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: add arm_is_secure() function

arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 027fc52704b815bd67a92399d255f066308ca70c
      
https://github.com/qemu/qemu/commit/027fc52704b815bd67a92399d255f066308ca70c
  Author: Sergey Fedorov <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: reject switching to monitor mode

Reject switching to monitor mode from non-secure state.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dcbff19bd07c198f4f9bdbf2db740a8e282dd5f6
      
https://github.com/qemu/qemu/commit/dcbff19bd07c198f4f9bdbf2db740a8e282dd5f6
  Author: Greg Bellows <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: rename arm_current_pl to arm_current_el

Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.

Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: fixed a minor merge resolution error in a couple of hunks]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 592125f83a8034deaa26f840cde5909f26429c4a
      
https://github.com/qemu/qemu/commit/592125f83a8034deaa26f840cde5909f26429c4a
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: make arm_current_el() return EL3

Make arm_current_el() return EL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly inferred from arm_
current_el(). Change assertion in arm_el_is_aa64() to allow EL3.

Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dbe9d1636787dd226d3f9a61c07fbc27e0db5bbf
      
https://github.com/qemu/qemu/commit/dbe9d1636787dd226d3f9a61c07fbc27e0db5bbf
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: A32: Emulate the SMC instruction

Implements SMC instruction in AArch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.

Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 71b7f54fdfa6a9bd56546b5c3996311b7b836636
      
https://github.com/qemu/qemu/commit/71b7f54fdfa6a9bd56546b5c3996311b7b836636
  Author: Peter Maydell <address@hidden>
  Date:   2014-10-24 (Fri, 24 Oct 2014)

  Changed paths:
    M disas/arm-a64.cc
    M disas/libvixl/README
    M disas/libvixl/a64/assembler-a64.h
    M disas/libvixl/a64/decoder-a64.cc
    M disas/libvixl/a64/decoder-a64.h
    M disas/libvixl/a64/disasm-a64.cc
    M disas/libvixl/a64/disasm-a64.h
    M disas/libvixl/a64/instructions-a64.cc
    M disas/libvixl/a64/instructions-a64.h
    A disas/libvixl/code-buffer.h
    M disas/libvixl/utils.cc
    M disas/libvixl/utils.h
    M hmp-commands.hx
    M hw/arm/boot.c
    M hw/arm/virt.c
    M hw/ide/microdrive.c
    M hw/intc/arm_gic.c
    M hw/intc/armv7m_nvic.c
    M hw/intc/gic_internal.h
    M hw/misc/omap_gpmc.c
    M hw/pcmcia/pxa2xx.c
    M include/hw/pcmcia.h
    M monitor.c
    M target-arm/Makefile.objs
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/kvm-consts.h
    M target-arm/machine.c
    M target-arm/op_helper.c
    A target-arm/psci.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20141024' 
into staging

target-arm queue:
 * remove pointless 'info pcmcia' and a lot of now-dead code
 * register ARM cpu reset handlers even if not using -kernel
 * update to libvixl 1.6
 * various minor code cleanups
 * support PSCI under TCG ('virt' machine can now be shut down,
   SMP configurations work)
 * correct the sense of the AArch64 DCZID DZP bit
 * report a valid L1Ip field in CTR_EL0 for CPU type "any"
 * correctly UNDEF writes to FPINST/FPINST2 from EL0
 * more preparatory code refactoring for EL2/EL3 support

# gpg: Signature made Fri 24 Oct 2014 12:35:52 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20141024: (23 commits)
  target-arm: A32: Emulate the SMC instruction
  target-arm: make arm_current_el() return EL3
  target-arm: rename arm_current_pl to arm_current_el
  target-arm: reject switching to monitor mode
  target-arm: add arm_is_secure() function
  target-arm: increase arrays of registers R13 & R14
  target-arm: correctly UNDEF writes to FPINST/FPINST2 from EL0
  target-arm: Report a valid L1Ip field in CTR_EL0 for CPU type "any"
  target-arm: Correct sense of the DCZID DZP bit
  arm/virt: enable PSCI emulation support for system emulation
  target-arm: add emulation of PSCI calls for system emulation
  target-arm: Add support for A32 and T32 HVC and SMC insns
  target-arm: Handle SMC/HVC undef-if-no-ELx in pre_* helpers
  target-arm: add missing PSCI constants needed for PSCI emulation
  target-arm: do not set do_interrupt handlers for ARM and AArch64 user modes
  target-arm: add powered off cpu state
  omap_gpmc.c: Remove duplicate assignment
  disas/libvixl/a64/instructions-a64.h: Remove unused constants
  arm_gic: remove unused parameter.
  disas/libvixl: Update to libvixl 1.6
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/8b135a288ae8...71b7f54fdfa6