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[Qemu-commits] [qemu/qemu] 46747d: target-arm: Implement setting guest b
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[Qemu-commits] [qemu/qemu] 46747d: target-arm: Implement setting guest breakpoints |
Date: |
Tue, 30 Sep 2014 04:00:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 46747d15080a93cc82cac563c1b7b8ffef164bb5
https://github.com/qemu/qemu/commit/46747d15080a93cc82cac563c1b7b8ffef164bb5
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/internals.h
M target-arm/machine.c
Log Message:
-----------
target-arm: Implement setting guest breakpoints
This patch adds support for setting guest breakpoints
based on values the guest writes to the DBGBVR and DBGBCR
registers. (It doesn't include the code to handle when
these breakpoints fire, so has no guest-visible effect.)
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 0eacea706060f9c53998896696b5f94cf49b8f03
https://github.com/qemu/qemu/commit/0eacea706060f9c53998896696b5f94cf49b8f03
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/internals.h
M target-arm/op_helper.c
Log Message:
-----------
target-arm: Implement handling of breakpoint firing
Implement handling of breakpoint event firing to correctly
inject the debug exception into the guest.
Since the breakpoint and watchpoint control register format is
very similar we adjust wp_matches() to also handle breakpoints
as well rather than using a separate function.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 8f95ce2e4ceecc861dc20038871c6c0df7d40842
https://github.com/qemu/qemu/commit/8f95ce2e4ceecc861dc20038871c6c0df7d40842
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M configure
Log Message:
-----------
configure: Build GDB XML for 32 bit ARM CPUs into qemu aarch64 binaries
The qemu-aarch64 and qemu-system-aarch64 binaries include support
for all the 32 bit ARM CPUs as well as the 64 bit ones. This means
we need to build in the GDB XML files for the 32 bit CPUs too.
Otherwise gdb will complain:
warning: while parsing target description (at line 1): Could not load XML
document "arm-core.xml"
when you try to connect to our gdbserver to debug a 32 bit CPU
running in a qemu-aarch64 or qemu-system-aarch64 binary.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 65731d1c3ee1f9ffc811aa290fd520cdb50ff11f
https://github.com/qemu/qemu/commit/65731d1c3ee1f9ffc811aa290fd520cdb50ff11f
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M hw/display/blizzard.c
Log Message:
-----------
hw/display/blizzard.c: Delete unused function blizzard_rgb2yuv
The function blizzard_rgb2yuv() is unused; delete it.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 93c9aea9b42bedb65a03dbb3c6ff7dbfc43ef9a7
https://github.com/qemu/qemu/commit/93c9aea9b42bedb65a03dbb3c6ff7dbfc43ef9a7
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M hw/intc/imx_avic.c
Log Message:
-----------
hw/intc/imx_avic.c: Remove unused function imx_avic_set_prio()
The function imx_avic_set_prio() is unused; delete it.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 6ac285b824270821ac36eaaa2d92dc25ba2a5669
https://github.com/qemu/qemu/commit/6ac285b824270821ac36eaaa2d92dc25ba2a5669
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M hw/display/pxa2xx_lcd.c
Log Message:
-----------
hw/display/pxa2xx_lcd.c: Remove unused function pxa2xx_dma_rdst_set
The function pxa2xx_dma_rdst_set() is unused; delete it.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: f59492b984934170f624487ffdec983a0102ba96
https://github.com/qemu/qemu/commit/f59492b984934170f624487ffdec983a0102ba96
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M hw/input/tsc210x.c
Log Message:
-----------
hw/input/tsc210x.c: Delete unused array tsc2101_rates
The array tsc2101_rates[] is unused (and we don't implement
the TSC2101 anyway, only the 2102); delete it.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: c0f4af171999eda4e49de5169906ce98246457f0
https://github.com/qemu/qemu/commit/c0f4af171999eda4e49de5169906ce98246457f0
Author: Peter Maydell <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/op_helper.c
M target-arm/translate.c
M target-arm/translate.h
Log Message:
-----------
target-arm: Don't handle c15_cpar changes via tb_flush()
At the moment we try to handle c15_cpar with the strategy of:
* emit generated code which makes assumptions about its value
* when the register value changes call tb_flush() to throw
away the now-invalid generated code
This works because XScale CPUs are always uniprocessor, but
it's confusing because it suggests that the same approach can
be taken for other registers. It also means we do a tb_flush()
on CPU reset, which makes multithreaded linux-user binaries
even more likely to fail than would otherwise be the case.
Replace it with a combination of TB flags for the access
checks done on cp0/cp1 for the XScale and iwMMXt instructions,
plus a runtime check for cp2..cp13 coprocessor accesses.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: f149e3e8479c3ac231bd58ba4955b02b67950547
https://github.com/qemu/qemu/commit/f149e3e8479c3ac231bd58ba4955b02b67950547
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
Log Message:
-----------
target-arm: Add HCR_EL2
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 64e0e2de0c6735202acd575dbf32b310ec8ebad5
https://github.com/qemu/qemu/commit/64e0e2de0c6735202acd575dbf32b310ec8ebad5
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
Log Message:
-----------
target-arm: Add SCR_EL3
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: apply offsetoflow32() to correct regdef]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9e729b57ac2a3adebee2746a2106a70eb8230a72
https://github.com/qemu/qemu/commit/9e729b57ac2a3adebee2746a2106a70eb8230a72
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
Log Message:
-----------
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Introduce new_el and new_mode in preparation for future patches
that add support for taking exceptions to and from EL2 and 3.
No functional change.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 043b7f8d12dc922172cf7d570dc2854dbf81dcb3
https://github.com/qemu/qemu/commit/043b7f8d12dc922172cf7d570dc2854dbf81dcb3
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.c
M target-arm/cpu.h
Log Message:
-----------
target-arm: Break out exception masking to a separate func
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: updated to account for recent cpu-exec refactoring]
Signed-off-by: Peter Maydell <address@hidden>
Commit: dfafd0908820acf68f7c69ab3e0ebe855278d0bb
https://github.com/qemu/qemu/commit/dfafd0908820acf68f7c69ab3e0ebe855278d0bb
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
Log Message:
-----------
target-arm: Don't take interrupts targeting lower ELs
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2dd081ae7642d54470225ea8c3f5cd4ef62fc732
https://github.com/qemu/qemu/commit/2dd081ae7642d54470225ea8c3f5cd4ef62fc732
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/helper-a64.c
Log Message:
-----------
target-arm: A64: Correct updates to FAR and ESR on exceptions
Not all exception types update both FAR and ESR.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 35979d71c40180a33242bf396a16b302f025fb82
https://github.com/qemu/qemu/commit/35979d71c40180a33242bf396a16b302f025fb82
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/helper.h
M target-arm/internals.h
M target-arm/op_helper.c
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Emulate the HVC insn
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 607d98b81e68a5fe23e553a0b75c0c38346a6d5f
https://github.com/qemu/qemu/commit/607d98b81e68a5fe23e553a0b75c0c38346a6d5f
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/internals.h
Log Message:
-----------
target-arm: Add a Hypervisor Trap exception type
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e0d6e6a5e799c91b74e157ca2cb7f4d2dbc0d56b
https://github.com/qemu/qemu/commit/e0d6e6a5e799c91b74e157ca2cb7f4d2dbc0d56b
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/helper.h
M target-arm/internals.h
M target-arm/op_helper.c
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Emulate the SMC insn
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 041c96666d0480380e50fe66fc66cc35bddcf741
https://github.com/qemu/qemu/commit/041c96666d0480380e50fe66fc66cc35bddcf741
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
Log Message:
-----------
target-arm: Add IRQ and FIQ routing to EL2 and 3
Reviewed-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 136e67e9b50b61fb03fedcea5c4fbe74cf44fdcc
https://github.com/qemu/qemu/commit/136e67e9b50b61fb03fedcea5c4fbe74cf44fdcc
Author: Edgar E. Iglesias <address@hidden>
Date: 2014-09-29 (Mon, 29 Sep 2014)
Changed paths:
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/internals.h
Log Message:
-----------
target-arm: Add support for VIRQ and VFIQ
This only implements the external delivery method via the GIC.
Acked-by: Greg Bellows <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: adjusted following cpu-exec refactoring]
Signed-off-by: Peter Maydell <address@hidden>
Commit: 29429c7244c73eefada3d0ec6dd30c5698782d08
https://github.com/qemu/qemu/commit/29429c7244c73eefada3d0ec6dd30c5698782d08
Author: Peter Maydell <address@hidden>
Date: 2014-09-30 (Tue, 30 Sep 2014)
Changed paths:
M configure
M hw/display/blizzard.c
M hw/display/pxa2xx_lcd.c
M hw/input/tsc210x.c
M hw/intc/imx_avic.c
M target-arm/cpu.c
M target-arm/cpu.h
M target-arm/helper-a64.c
M target-arm/helper.c
M target-arm/helper.h
M target-arm/internals.h
M target-arm/machine.c
M target-arm/op_helper.c
M target-arm/translate-a64.c
M target-arm/translate.c
M target-arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140929'
into staging
target-arm:
* more EL2/EL3 preparation work
* don't handle c15_cpar changes via tb_flush()
* fix some unused function warnings in ARM devices
* build the GDB XML for 32 bit CPUs into qemu-*-aarch64
* implement guest breakpoint support
# gpg: Signature made Mon 29 Sep 2014 19:25:37 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
* remotes/pmaydell/tags/pull-target-arm-20140929:
target-arm: Add support for VIRQ and VFIQ
target-arm: Add IRQ and FIQ routing to EL2 and 3
target-arm: A64: Emulate the SMC insn
target-arm: Add a Hypervisor Trap exception type
target-arm: A64: Emulate the HVC insn
target-arm: A64: Correct updates to FAR and ESR on exceptions
target-arm: Don't take interrupts targeting lower ELs
target-arm: Break out exception masking to a separate func
target-arm: A64: Refactor aarch64_cpu_do_interrupt
target-arm: Add SCR_EL3
target-arm: Add HCR_EL2
target-arm: Don't handle c15_cpar changes via tb_flush()
hw/input/tsc210x.c: Delete unused array tsc2101_rates
hw/display/pxa2xx_lcd.c: Remove unused function pxa2xx_dma_rdst_set
hw/intc/imx_avic.c: Remove unused function imx_avic_set_prio()
hw/display/blizzard.c: Delete unused function blizzard_rgb2yuv
configure: Build GDB XML for 32 bit ARM CPUs into qemu aarch64 binaries
target-arm: Implement handling of breakpoint firing
target-arm: Implement setting guest breakpoints
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/70d3a7a7b834...29429c7244c7
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