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[Qemu-commits] [qemu/qemu] 508280: disas/libvixl: Update to upstream VIX

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 508280: disas/libvixl: Update to upstream VIXL 1.5
Date: Fri, 29 Aug 2014 09:00:05 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 508280f5666a706a3681462b2a1d7de8107fd6fb
      
https://github.com/qemu/qemu/commit/508280f5666a706a3681462b2a1d7de8107fd6fb
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M disas/libvixl/README
    M disas/libvixl/a64/assembler-a64.h
    M disas/libvixl/a64/constants-a64.h
    M disas/libvixl/a64/cpu-a64.h
    M disas/libvixl/a64/decoder-a64.cc
    M disas/libvixl/a64/decoder-a64.h
    M disas/libvixl/a64/disasm-a64.cc
    M disas/libvixl/a64/disasm-a64.h
    M disas/libvixl/a64/instructions-a64.cc
    M disas/libvixl/a64/instructions-a64.h
    M disas/libvixl/platform.h
    M disas/libvixl/utils.cc
    M disas/libvixl/utils.h

  Log Message:
  -----------
  disas/libvixl: Update to upstream VIXL 1.5

Update our copy of libvixl to upstream's 1.5 release.
This includes the upstream versions of the fixes we
were carrying locally (commit ffebe899).

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: ed1f13d607e2c64c66bea49d6f4edaf278d3d246
      
https://github.com/qemu/qemu/commit/ed1f13d607e2c64c66bea49d6f4edaf278d3d246
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Fix regression that disabled VFP for ARMv5 CPUs

Commit 2c7ffc414 added support for honouring the CPACR coprocessor
access control register bits which may disable access to VFP
and Neon instructions. However it failed to account for the
fact that the CPACR is only present starting from the ARMv6
architecture version, so it accidentally disabled VFP completely
for ARMv5 CPUs like the ARM926. Linux would detect this as
"no VFP present" and probably fall back to its own emulation,
but other guest OSes might crash or misbehave.

This fixes bug LP:1359930.

Reported-by: Jakub Jermar <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c379621451e64cad166a60f42e1d67f0438b8d1b
      
https://github.com/qemu/qemu/commit/c379621451e64cad166a60f42e1d67f0438b8d1b
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values

We implement the crypto extensions but were incorrectly reporting
ID register values for the Cortex-A57 which did not advertise
crypto. Use the correct values as described in the TRM.
With this fix Linux correctly detects presence of the crypto
features and advertises them in /proc/cpuinfo.

Reported-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 71a62046ae7accb4fdd4b2413a77342fc5e0c554
      
https://github.com/qemu/qemu/commit/71a62046ae7accb4fdd4b2413a77342fc5e0c554
  Author: Adam Lackorzynski <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  arm_gic: Fix read of GICD_ICFGR

The GICD_ICFGR register covers 4 interrupts per byte.

Acked-by: Christoffer Dall <address@hidden>
Signed-off-by: Adam Lackorzynski <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 24b790df4388009c25cee311a4eff792c89cada1
      
https://github.com/qemu/qemu/commit/24b790df4388009c25cee311a4eff792c89cada1
  Author: Adam Lackorzynski <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  arm_gic: GICD_ICFGR: Write model only for pre v1 GICs

Setting the model is only available in pre-v1 GIC models.

Acked-by: Christoffer Dall <address@hidden>
Signed-off-by: Adam Lackorzynski <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: de7a900f0cdeeb5ebcb9d4a56cba2f0da7477001
      
https://github.com/qemu/qemu/commit/de7a900f0cdeeb5ebcb9d4a56cba2f0da7477001
  Author: Adam Lackorzynski <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  arm_gic: Do not force PPIs to edge-triggered mode

Only SGIs must be WI, done by forcing them to their default
(edge-triggered).

Acked-by: Christoffer Dall <address@hidden>
Signed-off-by: Adam Lackorzynski <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 93b5f6f1a630f8db141d7ce9030d4fc2e3fa5b14
      
https://github.com/qemu/qemu/commit/93b5f6f1a630f8db141d7ce9030d4fc2e3fa5b14
  Author: Adam Lackorzynski <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M hw/intc/arm_gic_common.c

  Log Message:
  -----------
  arm_gic: Use GIC_NR_SGIS constant

Use constant rather than a plain number.

Acked-by: Christoffer Dall <address@hidden>
Signed-off-by: Adam Lackorzynski <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d3579f362f61addb6b8b9c683f398d29af47eb23
      
https://github.com/qemu/qemu/commit/d3579f362f61addb6b8b9c683f398d29af47eb23
  Author: Joel Schopp <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  aarch64: raise max_cpus to 8

I'm running on a system with 8 cpus and it would be nice to have qemu
support all of them.  The attached patch does that and has been tested.

That said, I'm not sure if 8 is enough or if we want to bump this even higher
now before systems with many more cpus come along. 255 anyone?

Cc: Peter Maydell <address@hidden>
Signed-off-by: Joel Schopp <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b52b81e44f7d087a7b06217eb83cd79f8bf2fb05
      
https://github.com/qemu/qemu/commit/b52b81e44f7d087a7b06217eb83cd79f8bf2fb05
  Author: Sergey Fedorov <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: honor target mask in gic_update()

Take IRQ target mask into account when determining the highest priority
pending interrupt.

Signed-off-by: Sergey Fedorov <address@hidden>
Acked-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c92c06872a092eaba64ea7e56ceff762be48b093
      
https://github.com/qemu/qemu/commit/c92c06872a092eaba64ea7e56ceff762be48b093
  Author: Alistair Francis <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make the ARM PMCCNTR register 64-bit

This makes the PMCCNTR register 64-bit to allow for the
64-bit ARMv8 version.

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 421c7ebd93d33a3276b78985b9e25cfea35692f0
      
https://github.com/qemu/qemu/commit/421c7ebd93d33a3276b78985b9e25cfea35692f0
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  arm: Implement PMCCNTR 32b read-modify-write

The register is now 64bit, however a 32 bit write to the register
should leave the higher bits unchanged. The open coded write handler
does not implement this, so we need to read-modify-write accordingly.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8521466b391f92681d64eabfeeca17de9b03585d
      
https://github.com/qemu/qemu/commit/8521466b391f92681d64eabfeeca17de9b03585d
  Author: Alistair Francis <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement PMCCNTR_EL0 and related registers

This patch adds support for the ARMv8 version of the PMCCNTR and
related registers. It also starts to implement the PMCCFILTR_EL0
register.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 87124fdea443322924be00eb79430a6243cf0747
      
https://github.com/qemu/qemu/commit/87124fdea443322924be00eb79430a6243cf0747
  Author: Alistair Francis <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add arm_ccnt_enabled function

Include a helper function to determine if the CCNT counter
is enabled.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[ PC changes
  * Remove EL based checks
]
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ec7b4ce4c7864337a336721721d48456b4b5b51d
      
https://github.com/qemu/qemu/commit/ec7b4ce4c7864337a336721721d48456b4b5b51d
  Author: Alistair Francis <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement pmccntr_sync function

This is used to synchronise the PMCCNTR counter and swap its
state between enabled and disabled if required. It must always
be called twice, both before and after any logic that could
change the state of the PMCCNTR counter.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[PMM: fixed minor typos in pmccntr_sync doc comment]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 942a155b2098d7cd9b6f93e251cd06fe11d96bcf
      
https://github.com/qemu/qemu/commit/942a155b2098d7cd9b6f93e251cd06fe11d96bcf
  Author: Alistair Francis <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Remove old code and replace with new functions

Remove the old PMCCNTR code and replace it with calls to the new
pmccntr_sync() and arm_ccnt_enabled() functions.

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0614601cecc8e5d9c6c5fa606b39fe388a18583a
      
https://github.com/qemu/qemu/commit/0614601cecc8e5d9c6c5fa606b39fe388a18583a
  Author: Alistair Francis <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement pmccfiltr_write function

This is the function that is called when writing to the
PMCCFILTR_EL0 register

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8b3030114a449e66c68450acaac4b66f26d91416
      
https://github.com/qemu/qemu/commit/8b3030114a449e66c68450acaac4b66f26d91416
  Author: Peter Maydell <address@hidden>
  Date:   2014-08-29 (Fri, 29 Aug 2014)

  Changed paths:
    M disas/libvixl/README
    M disas/libvixl/a64/assembler-a64.h
    M disas/libvixl/a64/constants-a64.h
    M disas/libvixl/a64/cpu-a64.h
    M disas/libvixl/a64/decoder-a64.cc
    M disas/libvixl/a64/decoder-a64.h
    M disas/libvixl/a64/disasm-a64.cc
    M disas/libvixl/a64/disasm-a64.h
    M disas/libvixl/a64/instructions-a64.cc
    M disas/libvixl/a64/instructions-a64.h
    M disas/libvixl/platform.h
    M disas/libvixl/utils.cc
    M disas/libvixl/utils.h
    M hw/arm/virt.c
    M hw/intc/arm_gic.c
    M hw/intc/arm_gic_common.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140829' 
into staging

target-arm queue:
 * support PMCCNTR in ARMv8
 * various GIC fixes and cleanups
 * Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
 * Fix regression that disabled VFP for ARMv5 CPUs
 * Update to upstream VIXL 1.5

# gpg: Signature made Fri 29 Aug 2014 15:34:47 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140829:
  target-arm: Implement pmccfiltr_write function
  target-arm: Remove old code and replace with new functions
  target-arm: Implement pmccntr_sync function
  target-arm: Add arm_ccnt_enabled function
  target-arm: Implement PMCCNTR_EL0 and related registers
  arm: Implement PMCCNTR 32b read-modify-write
  target-arm: Make the ARM PMCCNTR register 64-bit
  hw/intc/arm_gic: honor target mask in gic_update()
  aarch64: raise max_cpus to 8
  arm_gic: Use GIC_NR_SGIS constant
  arm_gic: Do not force PPIs to edge-triggered mode
  arm_gic: GICD_ICFGR: Write model only for pre v1 GICs
  arm_gic: Fix read of GICD_ICFGR
  target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
  target-arm: Fix regression that disabled VFP for ARMv5 CPUs
  disas/libvixl: Update to upstream VIXL 1.5

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/d9aa68855724...8b3030114a44
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