[Qemu-commits] [qemu/qemu] 623e25: linux-user: Correct AUXV Cache Line Sizes for Powe...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 623e250abdca2c29830793e3ac81a9e405f33216
      
https://github.com/qemu/qemu/commit/623e250abdca2c29830793e3ac81a9e405f33216
  Author: Tom Musta <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Correct AUXV Cache Line Sizes for PowerPC

Set the AT_ICACHEBSIZE and AT_DCACHEBSIZE entries of the AUXV to match the
CPU model's cache line sizes.  This fixes memory clobbering problems on more
recent Book 3s implementations; memset(p, 0, N) will use the dcbz instruction
when N is sufficiently large and many of the newer server CPUs have cache lines
sizes of 128 bytes.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b2f1355020b1b48c479426b50f37baccb3b1fe84
      
https://github.com/qemu/qemu/commit/b2f1355020b1b48c479426b50f37baccb3b1fe84
  Author: Tom Musta <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  target-ppc: Add DFP to Emulated Instructions Flag

Decimal Floating Point is emulated, so add it the mask.  This will
fix the erroneous message:

  Warning: Disabling some instructions which are not emulated by TCG (0x0, 0x4)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0e019746d7c27899c832562a72d736667d7ce1b7
      
https://github.com/qemu/qemu/commit/0e019746d7c27899c832562a72d736667d7ce1b7
  Author: Tom Musta <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Identify Addition Hardware Capabilities for PowerPC

Add VSX, DFP and ISA 2.06 to the bits identified in the AT_HWCAP
entry of the AUXV.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a60438ddd68d45bc378b324fe7ecc61452d4f131
      
https://github.com/qemu/qemu/commit/a60438ddd68d45bc378b324fe7ecc61452d4f131
  Author: Tom Musta <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  linux-user: Support HWCAP2 in PowerPC

Set bits in the AT_HWCAP2 entry of the AUXV.  Specifically, detect and set bits
for bctar, ISEL and ISA 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: cc84c0f3571c75ced90a9ba9dcbb208464a1d997
      
https://github.com/qemu/qemu/commit/cc84c0f3571c75ced90a9ba9dcbb208464a1d997
  Author: Avik Sil <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Add "qemu, boot-menu" property to /chosen

This is required to enable boot menu display during booting

Signed-off-by: Avik Sil <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 294d1292893867894992e810a01cfcfa451f1885
      
https://github.com/qemu/qemu/commit/294d1292893867894992e810a01cfcfa451f1885
  Author: Sorav Bansal <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: fixed translation of mcrxr instruction

Fixed bug in gen_mcrxr() in target-ppc/translate.c:
The XER[SO], XER[OV], and XER[CA] flags are stored in the least
significant bit (bit 0) of their respective registers. They need
to be shifted left (by their respective offsets) to generate the final
XER value. The old translation code for the 'mcrxr' instruction
was assuming that  the flags are stored in bit 2, and was shifting them
right (incorrectly)

Signed-off-by: Sorav Bansal <address@hidden>
Reviewed-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b3cad3abf6df07db165091343b912c2a5de63c26
      
https://github.com/qemu/qemu/commit/b3cad3abf6df07db165091343b912c2a5de63c26
  Author: Alexander Graf <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M target-ppc/cpu-qom.h
    M target-ppc/gdbstub.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  PPC: Add support for Apple gdb in gdbstub

The Apple gdbstub protocol is different from the normal gdbstub protocol
used on PowerPC. Add support for the different variant, so that we can use
Apple's gdb to debug guest code.

Keep in mind that the switch is a compile time option. We can't detect
during runtime whether a gdb connecting to us is an upstream gdb or an
Apple gdb.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3a3b8502e6f0c8d30865c5f36d2c3ae4114000b5
      
https://github.com/qemu/qemu/commit/3a3b8502e6f0c8d30865c5f36d2c3ae4114000b5
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/nvram/spapr_nvram.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: Fix RTAS token numbers

At the moment spapr_rtas_register() allocates a new token number for every
new RTAS callback so numbers are not fixed and depend on the number of
supported RTAS handlers and the exact order of spapr_rtas_register() calls.
These tokens are copied into the device tree and remain the same during
the guest lifetime.

When we start another guest to receive a migration, it calls
spapr_rtas_register() as well. If the number of RTAS handlers or their
order is different in QEMU on source and destination sides, the "/rtas"
node in the device tree will differ. Since migration overwrites the device
tree (as it overwrites the entire RAM), the actual RTAS config on
the destination side gets broken.

This defines global contant values for every RTAS token which QEMU
is using today.

This changes spapr_rtas_register() to accept a token number instead of
allocating one. This changes all users of spapr_rtas_register().

This changes XICS-KVM not to cache tokens registered with KVM as they
constant now.

This makes TOKEN_BASE global as RTAS_XXX use TOKEN_BASE as
a base. TOKEN_MAX is moved and renamed too and its value is changed
to the last token + 1. Boundary checks for token values are adjusted.

This reserves token numbers for "os-term" handlers and PCI hotplug
which we are working on.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9bb62a0702dec4e103a3bb820b2a642e75995a56
      
https://github.com/qemu/qemu/commit/9bb62a0702dec4e103a3bb820b2a642e75995a56
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h

  Log Message:
  -----------
  spapr_iommu: Make in-kernel TCE table optional

POWER KVM supports an KVM_CAP_SPAPR_TCE capability which allows allocating
TCE tables in the host kernel memory and handle H_PUT_TCE requests
targeted to specific LIOBN (logical bus number) right in the host without
switching to QEMU. At the moment this is used for emulated devices only
and the handler only puts TCE to the table. If the in-kernel H_PUT_TCE
handler finds a LIOBN and corresponding table, it will put a TCE to
the table and complete hypercall execution. The user space will not be
notified.

Upcoming VFIO support is going to use the same sPAPRTCETable device class
so KVM_CAP_SPAPR_TCE is going to be used as well. That means that TCE
tables for VFIO are going to be allocated in the host as well.
However VFIO operates with real IOMMU tables and simple copying of
a TCE to the real hardware TCE table will not work as guest physical
to host physical address translation is requited.

So until the host kernel gets VFIO support for H_PUT_TCE, we better not
to register VFIO's TCE in the host.

This adds a place holder for KVM_CAP_SPAPR_TCE_VFIO capability. It is not
in upstream yet and being discussed so now it is always false which means
that in-kernel VFIO acceleration is not supported.

This adds a bool @vfio_accel flag to the sPAPRTCETable device telling
that sPAPRTCETable should not try allocating TCE table in the host kernel
for VFIO. The flag is false now as at the moment there is no VFIO.

This adds an vfio_accel parameter to spapr_tce_new_table(), the semantic
is the same. Since there is only emulated PCI and VIO now, the flag is set
to false. Upcoming VFIO support will set it to true.

This is a preparation patch so no change in behaviour is expected

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6d8be4c3434783a59ae29f7ea6a792b56c812349
      
https://github.com/qemu/qemu/commit/6d8be4c3434783a59ae29f7ea6a792b56c812349
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/misc/vfio.c
    A include/hw/misc/vfio.h

  Log Message:
  -----------
  vfio: Add vfio_container_ioctl()

While most operations with VFIO IOMMU driver are generic and used inside
vfio.c, there are still some operations which only specific VFIO IOMMU
drivers implement. The first example of it will be reading a DMA window
start from the host.

This adds a helper which passes an ioctl request to the container's fd.

The helper will check if @req is known. For this, stub is added. This return
-1 on any requests for now.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Acked-by: Alex Williamson <address@hidden>
Acked-by: Alex Williamson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9fc34ada7e80a7c561f64eb124b2b814a8feca68
      
https://github.com/qemu/qemu/commit/9fc34ada7e80a7c561f64eb124b2b814a8feca68
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/Makefile.objs
    A hw/ppc/spapr_pci_vfio.c
    M include/hw/pci-host/spapr.h

  Log Message:
  -----------
  spapr_pci_vfio: Add spapr-pci-vfio-host-bridge to support vfio

The patch adds a spapr-pci-vfio-host-bridge device type
which is a PCI Host Bridge with VFIO support. The new device
inherits from the spapr-pci-host-bridge device and adds an "iommu"
property which is an IOMMU id. This ID represents a minimal entity
for which IOMMU isolation can be guaranteed. In SPAPR architecture IOMMU
group is called a Partitionable Endpoint (PE).

Current implementation supports one IOMMU id per QEMU VFIO PHB. Since
SPAPR allows multiple PHB for no extra cost, this does not seem to
be a problem. This limitation may change in the future though.

Example of use:
Configure and Add 3 functions of a multifunctional device to QEMU:
(the NEC PCI USB card is used as an example here):
-device spapr-pci-vfio-host-bridge,id=USB,iommu=4,index=7 \
-device vfio-pci,host=4:0:1.0,addr=1.0,bus=USB,multifunction=true
-device vfio-pci,host=4:0:1.1,addr=1.1,bus=USB
-device vfio-pci,host=4:0:1.2,addr=1.2,bus=USB

where:
* index=7 is a QEMU PHB index (used as source for MMIO/MSI/IO windows
offset);
* iommu=4 is an IOMMU id which can be found in sysfs:
address@hidden ~]$ cd /sys/bus/pci/devices/0004:00:00.0/
address@hidden 0004:00:00.0]$ ls -l iommu_group
lrwxrwxrwx 1 root root 0 Jun  5 12:49 iommu_group -> 
../../../kernel/iommu_groups/4

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 591812634c84471fc68feb259ebebb82d0d5513a
      
https://github.com/qemu/qemu/commit/591812634c84471fc68feb259ebebb82d0d5513a
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/misc/vfio.c

  Log Message:
  -----------
  vfio: Enable for SPAPR

This turns the sPAPR support on and enables VFIO container use
in the kernel.

This extends vfio_connect_container to support VFIO_SPAPR_TCE_IOMMU type
in the host kernel.

This registers a memory listener which sPAPR IOMMU will notify when
executing H_PUT_TCE/etc DMA calls. The listener then will notify the host
kernel about DMA map/unmap operation via VFIO_IOMMU_MAP_DMA/
VFIO_IOMMU_UNMAP_DMA ioctls.

This executes VFIO_IOMMU_ENABLE ioctl to make sure that the IOMMU is free
of mappings and can be exclusively given to the user. At the moment SPAPR
is the only platform requiring this call to be implemented.

Note that the host kernel function implementing VFIO_IOMMU_DISABLE
is called automatically when container's fd is closed so there is
no need to call it explicitly from QEMU. We may need to call
VFIO_IOMMU_DISABLE explicitly in the future for some sort of dynamic
reconfiguration (PCI hotplug or dynamic IOMMU group management).

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Acked-by: Alex Williamson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b247812e4afda505a5ab48dd9ad05bd51bb55bee
      
https://github.com/qemu/qemu/commit/b247812e4afda505a5ab48dd9ad05bd51bb55bee
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Remove unused IMM and d extract helpers

Remove the definition of the IMM and d extract helpers; these seem to have
been added as part of the initial PPC support in 2003 but never actually
used.

Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c99b6f879a9b29b89a9c88237119d3801b086051
      
https://github.com/qemu/qemu/commit/c99b6f879a9b29b89a9c88237119d3801b086051
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Remove unused gen_qemu_ld8s()

The gen_qemu_ld8s() function is unused; remove it.

Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a0bb2a5fa095c88819eb6d8e08b1630c8d23c261
      
https://github.com/qemu/qemu/commit/a0bb2a5fa095c88819eb6d8e08b1630c8d23c261
  Author: BALATON Zoltan <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/mac_newworld.c

  Log Message:
  -----------
  mac99: Add motherboard devices before PCI cards

Change the order of creating devices for New World Mac emulation so
that devices on the motherboard are added first and PCI cards (VGA and
NIC) come later. As a side effect, this also causes OpenBIOS to map
the motherboard devices into the MMIO space to the same addresses as
on real hardware and allow clients that hardcode these addresses (e.g.
MorphOS) to find and use them until OpenBIOS is tought to map devices
to specific addresses. (On real hardware the graphics and network
cards are really on separate buses but we don't model that yet.) This
brings the memory map closer to what is found on PowerMac3,1.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1be88255a71f92f79e027b12609ca36999a21d7c
      
https://github.com/qemu/qemu/commit/1be88255a71f92f79e027b12609ca36999a21d7c
  Author: BALATON Zoltan <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  uninorth: Fix PCI hole size

Fix PCI hole size to match that what is found on real hardware.
(OpenBIOS already uses the correct length.)

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f6c3ebcc3b117311389bac58cffc4ad7c3016e1c
      
https://github.com/qemu/qemu/commit/f6c3ebcc3b117311389bac58cffc4ad7c3016e1c
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add support for POWER8 pvr 0x4D0000

At the moment QEMU knows about one version of POWER8 CPU with
PVR 0x4B.0000. This CPU class is defined as "POWER8". The linux
kernel names it as "POWER8E" which is different from the name QEMU uses.

Now we get another version of POWER8 which is architecturally equivalent
to POWER8E but has different PVR 0x4D.0000 so QEMU fails to find
a PPC CPU class on these machines. The linux kernel names these CPUs as
"POWER8".

This renames the existing "POWER8" to "POWER8E" to be more precise and
stay in sync with the linux kernel.

This adds a new "POWER8" family which calls POWER8E class init function
and defines own PVR mask (used to match a CPU class) and desc (used to
create dynamic version-less CPU class).

This does not change CPU class fw_name attribute as the host POWER8
firmware keeps using "PowerPC,POWER8" on both POWER8 and POWER8E.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6ca1502e3694cdb79f7143f700e3dc60a5d73539
      
https://github.com/qemu/qemu/commit/6ca1502e3694cdb79f7143f700e3dc60a5d73539
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Fix code design style (s/SPAPRMachine/sPAPRMachineState)

Every single sPAPR QOM object has small first "s".
Most (not all yet) QOM objects have "State" suffix.

This replaces SPAPRMachine with sPAPRMachineState to conform with QEMU
code style and removes redundant empty line.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6026db4501f773caaa2895cde7f93022960c7169
      
https://github.com/qemu/qemu/commit/6026db4501f773caaa2895cde7f93022960c7169
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Define a 2.1 pseries machine

This adds a v2.1 machine to support backward compatibility
for newer macines in the case if they ever be implemented.

This adds a "pseries-2.1" machine as a child of the "pseries"
machine and only changes visible machine name.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ce3fa1eca2c60673fede2222defb4bd13a3b5b1e
      
https://github.com/qemu/qemu/commit/ce3fa1eca2c60673fede2222defb4bd13a3b5b1e
  Author: Sam bobroff <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: Add rtas_st_buffer utility function

Add a function to write lengh + data into a buffer as required for the
emulation of the RTAS ibm,get-system-parameter call.

If the destination is smaller than the source, the write is truncated
and success is returned. This matches the behaviour of pHyp.

This will be used in following patches.

Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3052d9519000739ec25224ed1ca7498b7ff66d77
      
https://github.com/qemu/qemu/commit/3052d9519000739ec25224ed1ca7498b7ff66d77
  Author: Sam bobroff <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: Fix RTAS sysparm DIAGNOSTICS_RUN_MODE

This allows the ibm,get-system-parameter RTAS call to succeed for the
DIAGNOSTICS_RUN_MODE system parameter.

The problem can be seen with "ppc64_cpu --run-mode" from the
powerpc-utils package which fails before this patch with "Machine does
not support diagnostic run mode".

This is corrected by using the rtas_st_buffer() function to write to
the buffer.

The RTAS constants are also moved out into a header file, some new
constants added and the surrounding code slightly simplified.

Signed-off-by: Sam Bobroff <address@hidden>
[agraf: remove some commentary]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b907d7b0fdc8b2bbb93a37ac4b5c68a44f22e8ac
      
https://github.com/qemu/qemu/commit/b907d7b0fdc8b2bbb93a37ac4b5c68a44f22e8ac
  Author: Sam bobroff <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: Add RTAS sysparm UUID

Add support for the UUID parameter to the emulated RTAS call
ibm,get-system-parameter.

Return the guest's UUID as the value for the RTAS UUID system
parameter, or null (a zero length result) if it is not set.

Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3b50d8974b979bbaa091978e70d83de939593d1f
      
https://github.com/qemu/qemu/commit/3b50d8974b979bbaa091978e70d83de939593d1f
  Author: Sam bobroff <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr: Add RTAS sysparm SPLPAR Characteristics

Add support for the SPLPAR Characteristics parameter to the emulated
RTAS call ibm,get-system-parameter.

The support provides just enough information to allow "cat
/proc/powerpc/lparcfg" to succeed without generating a kernel error
message.

Without this patch the above command will produce the following kernel
message: arch/powerpc/platforms/pseries/lparcfg.c \
parse_system_parameter_string Error calling get-system-parameter \
(0xfffffffd)

Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4af88944d013330910826af10aaa2ef9a2919fde
      
https://github.com/qemu/qemu/commit/4af88944d013330910826af10aaa2ef9a2919fde
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M include/hw/ppc/xics.h

  Log Message:
  -----------
  xics: Add flags for interrupts

The existing interrupt allocation scheme in SPAPR assumes that
interrupts are allocated at the start time, continously and the config
will not change. However, there are cases when this is not going to work
such as:

1. migration - we will have to have an ability to choose interrupt
numbers for devices in the command line and this will create gaps in
interrupt space.

2. PCI hotplug - interrupts from unplugged device need to be returned
back to interrupt pool, otherwise we will quickly run out of interrupts.

This replaces a separate lslsi[] array with a byte in the ICSIRQState
struct and defines "LSI" and "MSI" flags. Neither of these flags set
signals that the descriptor is not allocated and not in use.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 641c349352cd3846ad164357d5a831e748d13536
      
https://github.com/qemu/qemu/commit/641c349352cd3846ad164357d5a831e748d13536
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/intc/xics.c

  Log Message:
  -----------
  xics: Add xics_find_source()

PAPR allows having multiple interrupt sources such as PHB.

This adds a source lookup function and makes use of it.

Since at the moment QEMU only supports a single source,
no change in behaviour is expected.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a7e519a8cf12c9f08a28339743b648dde38cd9d3
      
https://github.com/qemu/qemu/commit/a7e519a8cf12c9f08a28339743b648dde38cd9d3
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c

  Log Message:
  -----------
  xics: Disable flags reset on xics reset

Since islsi[] array has been merged into the ICSState struct,
we must not reset flags as they tell if the interrupt is in use.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bee763dbfb8cfceea112131970da07f215f293a6
      
https://github.com/qemu/qemu/commit/bee763dbfb8cfceea112131970da07f215f293a6
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/intc/xics.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h
    M include/hw/ppc/xics.h
    M trace-events

  Log Message:
  -----------
  spapr: Move interrupt allocator to xics

The current allocator returns IRQ numbers from a pool and does not
support IRQs reuse in any form as it did not keep track of what it
previously returned, it only keeps the last returned IRQ. Some use
cases such as PCI hot(un)plug may require IRQ release and reallocation.

This moves an allocator from SPAPR to XICS.

This switches IRQ users to use new API.

This uses LSI/MSI flags to know if interrupt is allocated.

The interrupt release function will be posted as a separate patch.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ba0e5bf8de38a33ea2e09b40e0493d30b62fcbf0
      
https://github.com/qemu/qemu/commit/ba0e5bf8de38a33ea2e09b40e0493d30b62fcbf0
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Remove @next_irq

This removes @next_irq from sPAPREnvironment which was used in old
IRQ allocator as XICS is now responsible for IRQs and keeps track of
allocated IRQs.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 51bba713fe1120ba7b0542216278f10e48349589
      
https://github.com/qemu/qemu/commit/51bba713fe1120ba7b0542216278f10e48349589
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/intc/xics.c
    M include/hw/ppc/xics.h
    M trace-events

  Log Message:
  -----------
  xics: Implement xics_ics_free()

This implements interrupt release function so IRQs can be returned back
to the pool for reuse in cases such as PCI hot plug.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f32935ea2284fe833fdf4a0d6b2fe423fc08a1b2
      
https://github.com/qemu/qemu/commit/f32935ea2284fe833fdf4a0d6b2fe423fc08a1b2
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M include/migration/vmstate.h
    M vmstate.c

  Log Message:
  -----------
  vmstate: Add preallocation for migrating arrays (VMS_ALLOC flag)

There are few helpers already to support array migration. However they all
require the destination side to preallocate arrays before migration which
is not always possible due to unknown array size as it might be some
sort of dynamic state. One of the examples is an array of MSIX-enabled
devices in SPAPR PHB - this array may vary from 0 to 65536 entries and
its size depends on guest's ability to enable MSIX or do PCI hotplug.

This adds new VMSTATE_VARRAY_STRUCT_ALLOC macro which is pretty similar to
VMSTATE_STRUCT_VARRAY_POINTER_INT32 but it can alloc memory for migratign
array on the destination side.

This defines VMS_ALLOC flag for a field.

This changes vmstate_base_addr() to do the allocation when receiving
migration.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Juan Quintela <address@hidden>
[agraf: drop g_malloc_n usage]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9a321e92343891e30f6fe8bfaad40454ae358bfb
      
https://github.com/qemu/qemu/commit/9a321e92343891e30f6fe8bfaad40454ae358bfb
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/spapr_pci.c
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M trace-events

  Log Message:
  -----------
  spapr_pci: Use XICS interrupt allocator and do not cache interrupts in PHB

Currently SPAPR PHB keeps track of all allocated MSI (here and below
MSI stands for both MSI and MSIX) interrupt because
XICS used to be unable to reuse interrupts. This is a problem for
dynamic MSI reconfiguration which happens when guest reloads a driver
or performs PCI hotplug. Another problem is that the existing
implementation can enable MSI on 32 devices maximum
(SPAPR_MSIX_MAX_DEVS=32) and there is no good reason for that.

This makes use of new XICS ability to reuse interrupts.

This reorganizes MSI information storage in sPAPRPHBState. Instead of
static array of 32 descriptors (one per a PCI function), this patch adds
a GHashTable when @config_addr is a key and (first_irq, num) pair is
a value. GHashTable can dynamically grow and shrink so the initial limit
of 32 devices is gone.

This changes migration stream as @msi_table was a static array while new
@msi_devs is a dynamic hash table. This adds temporary array which is
used for migration, it is populated in "spapr_pci"::pre_save() callback
and expanded into the hash table in post_load() callback. Since
the destination side does not know the number of MSI-enabled devices
in advance and cannot pre-allocate the temporary array to receive
migration state, this makes use of new VMSTATE_STRUCT_VARRAY_ALLOC macro
which allocates the array automatically.

This resets the MSI configuration space when interrupts are released by
the ibm,change-msi RTAS call.

This fixed traces to be more informative.

This changes vmstate_spapr_pci_msi name from "...lsi" to "...msi" which
was incorrect by accident. As the internal representation changed,
thus bumps migration version number.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: drop g_malloc_n usage]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 79c0ff2cae1f24cb7e041ac2dbdcc329d2a86ba2
      
https://github.com/qemu/qemu/commit/79c0ff2cae1f24cb7e041ac2dbdcc329d2a86ba2
  Author: Alexander Graf <address@hidden>
  Date:   2014-06-27 (Fri, 27 Jun 2014)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  PPC: e500: Only create dt entries for existing serial ports

When the user specifies -nodefaults he can tell us that he doesn't want any
serial ports spawned by default. While we do honor that wish, we still create
device tree entries for those non-existent devices.

Make device tree generation depend on whether the device is actually available.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2d80e0ab4b4326e340df7e0bcc687b2bc63c68d8
      
https://github.com/qemu/qemu/commit/2d80e0ab4b4326e340df7e0bcc687b2bc63c68d8
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-29 (Sun, 29 Jun 2014)

  Changed paths:
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/misc/vfio.c
    M hw/nvram/spapr_nvram.c
    M hw/pci-host/uninorth.c
    M hw/ppc/Makefile.objs
    M hw/ppc/e500.c
    M hw/ppc/mac_newworld.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    A hw/ppc/spapr_pci_vfio.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    A include/hw/misc/vfio.h
    M include/hw/pci-host/spapr.h
    M include/hw/ppc/spapr.h
    M include/hw/ppc/xics.h
    M include/migration/vmstate.h
    M linux-user/elfload.c
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu-qom.h
    M target-ppc/cpu.h
    M target-ppc/gdbstub.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/translate.c
    M target-ppc/translate_init.c
    M trace-events
    M vmstate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' 
into staging

Patch queue for ppc - 2014-06-27

Changes include:

  - instruction emulation fixes
  - linux-user fixes
  - mac99: layout fixes
  - pseries: Initial VFIO support
  - pseries: support for UUID
  - pseries: support for -boot m

# gpg: Signature made Fri 27 Jun 2014 12:51:01 BST using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found

* remotes/agraf/tags/signed-ppc-for-upstream: (32 commits)
  PPC: e500: Only create dt entries for existing serial ports
  spapr_pci: Use XICS interrupt allocator and do not cache interrupts in PHB
  vmstate: Add preallocation for migrating arrays (VMS_ALLOC flag)
  xics: Implement xics_ics_free()
  spapr: Remove @next_irq
  spapr: Move interrupt allocator to xics
  xics: Disable flags reset on xics reset
  xics: Add xics_find_source()
  xics: Add flags for interrupts
  spapr: Add RTAS sysparm SPLPAR Characteristics
  spapr: Add RTAS sysparm UUID
  spapr: Fix RTAS sysparm DIAGNOSTICS_RUN_MODE
  spapr: Add rtas_st_buffer utility function
  spapr: Define a 2.1 pseries machine
  spapr: Fix code design style (s/SPAPRMachine/sPAPRMachineState)
  target-ppc: Add support for POWER8 pvr 0x4D0000
  uninorth: Fix PCI hole size
  mac99: Add motherboard devices before PCI cards
  target-ppc: Remove unused gen_qemu_ld8s()
  target-ppc: Remove unused IMM and d extract helpers
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/de6793e8c2a4...2d80e0ab4b43