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[Qemu-commits] [qemu/qemu] 64641d: vnc: Drop superfluous conditionals ar


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 64641d: vnc: Drop superfluous conditionals around g_free()
Date: Fri, 20 Jun 2014 10:00:06 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 64641d876466333b833e8a188a46e2e06c008bac
      
https://github.com/qemu/qemu/commit/64641d876466333b833e8a188a46e2e06c008bac
  Author: Markus Armbruster <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M ui/vnc-tls.c
    M ui/vnc.c

  Log Message:
  -----------
  vnc: Drop superfluous conditionals around g_free()

Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Gerd Hoffmann <address@hidden>


  Commit: c14e98479bd3cb3667e283e815c238135db2edc1
      
https://github.com/qemu/qemu/commit/c14e98479bd3cb3667e283e815c238135db2edc1
  Author: Markus Armbruster <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M ui/vnc.c

  Log Message:
  -----------
  vnc: Drop superfluous conditionals around g_strdup()

Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Gerd Hoffmann <address@hidden>


  Commit: eb214ff8ef6cceec348f3ad1643b39443fe07910
      
https://github.com/qemu/qemu/commit/eb214ff8ef6cceec348f3ad1643b39443fe07910
  Author: Gerd Hoffmann <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M ui/vnc.c

  Log Message:
  -----------
  vnc: fix screen updates

Bug was added by 38ee14f4f33f8836fc0e209ca59c6ae8c6edf380.
vnc_jobs_join call is missing in one code path.

Reported-by: Anthony PERARD <address@hidden>
Signed-off-by: Gerd Hoffmann <address@hidden>


  Commit: e389be1673052b538534643165111725a79e5afd
      
https://github.com/qemu/qemu/commit/e389be1673052b538534643165111725a79e5afd
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: implement PD0/PD1 bits for TTBCR

Corrected handling of writes to TTBCR for ARMv8 (previously UNK/SBZP
bits are not RES0) and ARMv7 (new bits PD0/PD1 for CPUs with Security
Extensions).

Bits PD0/PD1 are now respected in get_phys_addr_v6/v5() and
get_level1_table_address.

Signed-off-by: Fabian Aggeler <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0062609f70b465a56cf80bc573d0971ef2a0affb
      
https://github.com/qemu/qemu/commit/0062609f70b465a56cf80bc573d0971ef2a0affb
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M hw/arm/spitz.c

  Log Message:
  -----------
  hw/arm/spitz: Avoid clash with Windows header symbol MOD_SHIFT

The Windows headers provided by MinGW define MOD_SHIFT. Avoid
it by using SPITZ_MOD_* for our constants here.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5661ae6be23d8831a19c82f8eafb2aaecdf2da6a
      
https://github.com/qemu/qemu/commit/5661ae6be23d8831a19c82f8eafb2aaecdf2da6a
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add ULL suffix to calculation of page size

The maximum block size for AArch64 address translation is 2GB. This means
that we need a ULL suffix on our shift to avoid shifting into the sign
bit of a signed 32 bit integer.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 220ad4ca846d8e0734dd2d2af38c61a6f5436d66
      
https://github.com/qemu/qemu/commit/220ad4ca846d8e0734dd2d2af38c61a6f5436d66
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()

In disas_simd_3same_int(), none of the instructions permit is_q
to be false with size == 3 (this would be a vector operation with
a one-element vector, and the instruction set encodes those as
scalar operations). Replace the always-true ?: check with an
assert.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 4063452eca8aaa432b5c42b1ccea81be01219b0e
      
https://github.com/qemu/qemu/commit/4063452eca8aaa432b5c42b1ccea81be01219b0e
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()

In handle_simd_shift_fpint_conv(), the combination of is_double == true,
is_scalar == false and is_q == false is an unallocated encoding; the
'both parts false' case of the nested ?: expression for calculating
maxpass is therefore unreachable and can be removed.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 476e75ab9d2cf2ad8ac8dfd9530c9fee148c2c7a
      
https://github.com/qemu/qemu/commit/476e75ab9d2cf2ad8ac8dfd9530c9fee148c2c7a
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M hw/arm/vexpress.c

  Log Message:
  -----------
  hw/arm/vexpress: Forbid specifying flash contents in two ways at once

Detect attempts by the user to specify the contents of the first flash
device via both -bios and -drive if=pflash... simultaneously and
print a helpful error message.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: a0289b8af3b05fe47bee8e434d1c978382a5a8cc
      
https://github.com/qemu/qemu/commit/a0289b8af3b05fe47bee8e434d1c978382a5a8cc
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  hw/block/pflash_cfi01: Report correct size info for parallel configs

If the flash device is configured with a device-width which is
not equal to the bank-width, indicating that it is actually several
narrow flash devices in parallel, the CFI table should report the
number of blocks and the size of a single device, not of the whole
combined setup. This stops Linux from complaining:
"NOR chip too large to fit in mapping. Attempting to cope..."

As usual, we retain the old broken but backwards compatible behaviour
when the device-width is not specified.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 99040447cee777498c1b2125f16402b8af88355c
      
https://github.com/qemu/qemu/commit/99040447cee777498c1b2125f16402b8af88355c
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M kvm-all.c

  Log Message:
  -----------
  kvm: Handle exit reason KVM_EXIT_SYSTEM_EVENT

In-kernel PSCI v0.2 emulation of KVM ARM/ARM64 forwards SYSTEM_OFF
and SYSTEM_RESET function calls to QEMU using KVM_EXIT_SYSTEM_EVENT
exit reason.

This patch updates kvm_cpu_exec() to handle KVM_SYSTEM_EVENT_SHUTDOWN
and KVM_SYSTEM_EVENT_RESET system-level events from QEMU-side.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 228d5e048b68672593d93f1e42d777de80903e3d
      
https://github.com/qemu/qemu/commit/228d5e048b68672593d93f1e42d777de80903e3d
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/kvm.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/kvm_arm.h

  Log Message:
  -----------
  target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64

Introduce a common kvm_arm_vcpu_init() for doing KVM_ARM_VCPU_INIT
ioctl in KVM ARM and KVM ARM64. This also helps us factor-out few
common code lines from kvm_arch_init_vcpu() for KVM ARM/ARM64.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7cd62e53844603357152943f68960c8c5279160c
      
https://github.com/qemu/qemu/commit/7cd62e53844603357152943f68960c8c5279160c
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/kvm32.c
    M target-arm/kvm64.c

  Log Message:
  -----------
  target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible

Latest linux kernel supports in-kernel emulation of PSCI v0.2 but
to enable it we need to select KVM_ARM_VCPU_PSCI_0_2 feature using
KVM_ARM_VCPU_INIT ioctl.

Also, we can use KVM_ARM_VCPU_PSCI_0_2 feature for VCPU only when
linux kernel has KVM_CAP_ARM_PSCI_0_2 capability.

This patch updates kvm_arch_init_vcpu() to enable KVM_ARM_VCPU_PSCI_0_2
feature for VCPU when KVM ARM/ARM64 has KVM_CAP_ARM_PSCI_0_2 capability.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 73542cf6900146f4a203007388e224e5dc25c7da
      
https://github.com/qemu/qemu/commit/73542cf6900146f4a203007388e224e5dc25c7da
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/kvm64.c

  Log Message:
  -----------
  target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64

To implement kvm_arch_reset_vcpu(), we simply re-init the VCPU
using kvm_arm_vcpu_init() so that all registers of VCPU are set
to their reset values by in-kernel KVM code.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dd032e348757bae0451e25a473f34c25f8750c2b
      
https://github.com/qemu/qemu/commit/dd032e348757bae0451e25a473f34c25f8750c2b
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c

  Log Message:
  -----------
  target-arm: Introduce per-CPU field for PSCI version

We require to know the PSCI version available to given CPU at
potentially many places. Currently, we need to know PSCI version
when generating DTB for virt machine.

This patch introduce per-CPU 32bit field representing the PSCI
version available to the CPU. The encoding of this 32bit field
is same as described in PSCI v0.2 spec.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 06955739a283ecaf9e2c7658cd9d471e9967cac4
      
https://github.com/qemu/qemu/commit/06955739a283ecaf9e2c7658cd9d471e9967cac4
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  Use PSCI v0.2 compatible string when KVM or TCG provides it

If we have PSCI v0.2 emulation available for KVM ARM/ARM64 or TCG then
we need to provide PSCI v0.2 compatible string via generated DTB.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Anup Patel <address@hidden>
Reviewed-by: Rob Herring <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b6fb3a89e3cd173153f1edc4edbf970987b4ebdd
      
https://github.com/qemu/qemu/commit/b6fb3a89e3cd173153f1edc4edbf970987b4ebdd
  Author: Oran Avraham <address@hidden>
  Date:   2014-06-19 (Thu, 19 Jun 2014)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m_nvic: fix AIRCR implementation

The returned reset value was wrong (off by one zero nibble), and
qemu didn't log unimplemented writes to the PRIGROUP field.

Signed-off-by: Oran Avraham <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9d3c512021f7363f5877abd975070d08b02ba65c
      
https://github.com/qemu/qemu/commit/9d3c512021f7363f5877abd975070d08b02ba65c
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-20 (Fri, 20 Jun 2014)

  Changed paths:
    M ui/vnc-tls.c
    M ui/vnc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-20140619-1' into 
staging

vnc: cleanups and fixes

# gpg: Signature made Thu 19 Jun 2014 12:02:09 BST using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <address@hidden>"
# gpg:                 aka "Gerd Hoffmann <address@hidden>"
# gpg:                 aka "Gerd Hoffmann (private) <address@hidden>"

* remotes/kraxel/tags/pull-vnc-20140619-1:
  vnc: fix screen updates
  vnc: Drop superfluous conditionals around g_strdup()
  vnc: Drop superfluous conditionals around g_free()

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 53001c148340127c2dca1f90329804cd0ac0e236
      
https://github.com/qemu/qemu/commit/53001c148340127c2dca1f90329804cd0ac0e236
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-20 (Fri, 20 Jun 2014)

  Changed paths:
    M hw/arm/spitz.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/block/pflash_cfi01.c
    M hw/intc/armv7m_nvic.c
    M kvm-all.c
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/kvm.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/kvm_arm.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140619' 
into staging

target-arm:
 * Support PSCI 0.2 when using KVM
 * fix AIRCR reset value for v7M CPUs
 * report correct size information for pflash_cfi01
 * minor coverity fixes
 * avoid warnings on Windows builds due to #define clash
 * implement TTBCR PD0/PD1 bits

# gpg: Signature made Thu 19 Jun 2014 18:35:06 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140619:
  armv7m_nvic: fix AIRCR implementation
  Use PSCI v0.2 compatible string when KVM or TCG provides it
  target-arm: Introduce per-CPU field for PSCI version
  target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64
  target-arm: Enable KVM_ARM_VCPU_PSCI_0_2 feature when possible
  target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64
  kvm: Handle exit reason KVM_EXIT_SYSTEM_EVENT
  hw/block/pflash_cfi01: Report correct size info for parallel configs
  hw/arm/vexpress: Forbid specifying flash contents in two ways at once
  target-arm/translate-a64.c: Fix dead ?: in handle_simd_shift_fpint_conv()
  target-arm/translate-a64.c: Remove dead ?: in disas_simd_3same_int()
  target-arm: Add ULL suffix to calculation of page size
  hw/arm/spitz: Avoid clash with Windows header symbol MOD_SHIFT
  target-arm: implement PD0/PD1 bits for TTBCR

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e8e23b7dcf14...53001c148340

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