[Qemu-commits] [qemu/qemu] 61e992: vexpress: Add support for the -bios f

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[Qemu-commits] [qemu/qemu] 61e992: vexpress: Add support for the -bios f

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 61e992: vexpress: Add support for the -bios flag to provid...
Date:	Mon, 09 Jun 2014 10:00:10 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 61e99241491c2d87af2a9751630e597a54ea7af8
      
https://github.com/qemu/qemu/commit/61e99241491c2d87af2a9751630e597a54ea7af8
  Author: Grant Likely <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M hw/arm/vexpress.c

  Log Message:
  -----------
  vexpress: Add support for the -bios flag to provide firmware

Right now to run firmware inside the QEMU VExpress model requires
padding out the firmware image to the size of the virtual flash and
passing it in via the -pflash argument. If the firmware image is passed
without padding, then QEMU will fail. Also, when passed as a -pflash
argument, QEMU treats the file as persistent storage and will modify the
file.

The -bios flag provides the semantics that we want for providing a
firmware image. This patch maps the contents of the -bios file into the
address space at the boot flash location.

Tested with the vexpress-a15 model and the Tianocore port.

Signed-off-by: Grant Likely <address@hidden>
Tested-by: Roy Franz <address@hidden>
[PMM: folded long line, removed stray \n from error message,
 use correct variable for printing image name, exit(1) rather than 0]
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bf01601764fbef7b54894c9dc1f9c1e727a49294
      
https://github.com/qemu/qemu/commit/bf01601764fbef7b54894c9dc1f9c1e727a49294
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm/cpu64.c: Actually register Cortex-A57 impdef registers

cpu64.c contains a reginfo list for the impdef registers on
the Cortex-A57; however we forgot to actually call define_arm_cp_regs(),
so it was sitting there doing nothing. Remedy this omission.

Message-id: address@hidden
Reviewed-by: Peter Crosthwaite <address@hidden>
Tested-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8d5c773e323b22402abdd0beef4c7d2fc91dd0eb
      
https://github.com/qemu/qemu/commit/8d5c773e323b22402abdd0beef4c7d2fc91dd0eb
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Prepare cpreg writefns/readfns for EL3/SecExt

This patch changes some readfns/writefns to use raw_write
and raw_read functions, which use the fieldoffset specified
in ARMCPRegInfo instead of directly accessing the field.
This will simplify patches for EL3 & Security Extensions.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d615efac7c4dc0984de31791c5c7d6b06408aadb
      
https://github.com/qemu/qemu/commit/d615efac7c4dc0984de31791c5c7d6b06408aadb
  Author: Ian Campbell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables

In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
can just treat this bit as UXN whenever we are in v8 mode.

Also correctly extract the upper attributes from the PTE entry, the v8 version
tried to avoid extracting the CONTIG bit and ended up with the upper bits being
off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
bit.

This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
seen when modprobing modules under Linux.

Signed-off-by: Ian Campbell <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Claudio Fontana <address@hidden>
Cc: Rob Herring <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f1ecb913d81199758383b8cbc15f4eb435b91753
      
https://github.com/qemu/qemu/commit/f1ecb913d81199758383b8cbc15f4eb435b91753
  Author: Ard Biesheuvel <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M linux-user/elfload.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/crypto_helper.c
    M target-arm/helper.h
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: add support for v8 SHA1 and SHA256 instructions

This adds support for the SHA1 and SHA256 instructions that are available
on some v8 implementations of Aarch32.

Signed-off-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM:
 * rebase
 * fix bad indent
 * add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case
 * use g_assert_not_reached()
 * don't re-extract bit 6 for the 2-reg-misc encodings
 * set the ELF HWCAP2 bits for the new features
]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 526d0096e56e82ffa5edb15bd75c5c093e61fa59
      
https://github.com/qemu/qemu/commit/526d0096e56e82ffa5edb15bd75c5c093e61fa59
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Allow 3reg_wide undefreq to encode more bad size options

The current undefreq field in the neon_3reg_wide handling allows us
to encode "UNDEF if size != 0" and "UNDEF if size == 0". This is
no longer sufficient with the advent of 64-bit polynomial VMULL,
which means we want to UNDEF if size == 1. Change the undefreq
encoding to use separate bits for all of "UNDEF if size == 0",
"UNDEF if size == 1" and "UNDEF if size == 2".

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 4e624edaebec9312be7b63096bbe5b2fe76f3613
      
https://github.com/qemu/qemu/commit/4e624edaebec9312be7b63096bbe5b2fe76f3613
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M linux-user/elfload.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: add support for v8 VMULL.P64 instruction

Add support for the VMULL.P64 polynomial 64x64 to 128 bit multiplication
instruction in the A32/T32 instruction sets; this is part of the v8
Crypto Extensions.

To do this we have to move the neon_pmull_64_{lo,hi} helpers from
helper-a64.c into neon_helper.c so they can be used by the AArch32
translator.

Inspired-by: Ard Biesheuvel <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 411bdc7837681f58828ca490647fa1784a6700b9
      
https://github.com/qemu/qemu/commit/411bdc7837681f58828ca490647fa1784a6700b9
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M linux-user/elfload.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Use PMULL feature bit for PMULL

Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for
the A64 PMULL, not the AES feature bit.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 46d9dfdad65fa783691871622271a861466905c4
      
https://github.com/qemu/qemu/commit/46d9dfdad65fa783691871622271a861466905c4
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64

The arm_any_initfn() is used only for the 32-bit linux-user "cpu any",
so it only gets called in builds where TARGET_AARCH64 is not defined.
Remove the unreachable line which sets ARM_FEATURE_AARCH64.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: fb8ad9f2c1a82256b1ac384393a093a61201272f
      
https://github.com/qemu/qemu/commit/fb8ad9f2c1a82256b1ac384393a093a61201272f
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Remove unnecessary setting of feature bits

FEATURE_V8 implies both FEATURE_V7MP and FEATURE_ARM_DIV, so
we don't need to set them explicitly in initfns which set the
V8 feature bit.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 25f748e37a868b322a960c322ca11fb2dc5252b2
      
https://github.com/qemu/qemu/commit/25f748e37a868b322a960c322ca11fb2dc5252b2
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: Clean up handling of ARMv8 optional feature bits

CRC and crypto are both optional v8 extensions, so FEATURE_V8
should not imply them. Instead we should set these bits in the
initfns for the 32-bit and 64-bit "cpu any" and for the Cortex-A57.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: da5141fc45937fa358ca4554a335ae6a4c4453ec
      
https://github.com/qemu/qemu/commit/da5141fc45937fa358ca4554a335ae6a4c4453ec
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: VFPv4 implies half-precision extension

VFPv4 implies the presence of the half-precision floating point
extension (which is optional in VFPv3). Add this implied rule
to arm_cpu_realizefn() and remove some no-longer-needed explicit
setting of the bit in initfns.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 130f2e7dcb4a5f9534fc65200121f06983435a77
      
https://github.com/qemu/qemu/commit/130f2e7dcb4a5f9534fc65200121f06983435a77
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M linux-user/elfload.c
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement CRC instructions

Implement the optional A64 CRC instructions.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: aa633469ed902a6d96b3d4013ec5ce32597f0626
      
https://github.com/qemu/qemu/commit/aa633469ed902a6d96b3d4013ec5ce32597f0626
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: A32/T32: Mask CRC value in calling code, not helper

Bring the 32-bit CRC helper functions into line with the A64 ones,
by masking the high bytes of the value in the calling code rather
than the helper. This is more efficient since we can determine the
mask at translation time.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 5acc765c04300f9ac8b7944008bc3ad54c6b032a
      
https://github.com/qemu/qemu/commit/5acc765c04300f9ac8b7944008bc3ad54c6b032a
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M linux-user/elfload.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement AES instructions

Implement the AES instructions from the optional Crypto Extensions.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: be56f04eeacc22634a3bd709fdbda9873e8f55af
      
https://github.com/qemu/qemu/commit/be56f04eeacc22634a3bd709fdbda9873e8f55af
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement 3-register SHA instructions

Implement the 3-register SHA instruction group from the optional
Crypto Extensions.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: f6fe04d566f1a1e3219b501487cd2d2d00d723a5
      
https://github.com/qemu/qemu/commit/f6fe04d566f1a1e3219b501487cd2d2d00d723a5
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M linux-user/elfload.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement two-register SHA instructions

Implement the two-register SHA instruction group from the optional
Crypto Extensions.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: d3afacc7269fee45d54d1501a46b51f12ea7bb15
      
https://github.com/qemu/qemu/commit/d3afacc7269fee45d54d1501a46b51f12ea7bb15
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix errors in writes to generic timer control registers

The code for handling writes to the generic timer control registers
had several bugs:
 * ISTATUS (bit 2) is read-only but we forced it to zero on any write
 * the check for "was IMASK (bit 1) toggled?" incorrectly used '&' where
   it should be '^'
 * the handling of IMASK was inverted: we should set the IRQ if
   ISTATUS is set and IMASK is clear, not if both are set

The combination of these bugs meant that when running a Linux guest
that uses the generic timers we would fairly quickly end up either
forgetting that the timer output should be asserted, or failing to
set the IRQ when the timer was unmasked. The result is that the guest
never gets any more timer interrupts.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Cc: address@hidden


  Commit: 3b1a41381254f6080b5cfeb149c28a9237d42a0b
      
https://github.com/qemu/qemu/commit/3b1a41381254f6080b5cfeb149c28a9237d42a0b
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/iwmmxt_helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Delete unused iwmmxt_msadb helper

The iwmmxt_msadb helper and its corresponding gen function are unused;
delete them. (This function appears to have never been used right back
to the initial implementation of iwMMXt; it is identical to iwmmxt_madduq,
and is presumably an accidental remnant from the initial development.)

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 7721a3044234c46cd6f5f899e7467dc9351f3c8d
      
https://github.com/qemu/qemu/commit/7721a3044234c46cd6f5f899e7467dc9351f3c8d
  Author: Peter Maydell <address@hidden>
  Date:   2014-06-09 (Mon, 09 Jun 2014)

  Changed paths:
    M hw/arm/vexpress.c
    M linux-user/elfload.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/crypto_helper.c
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/iwmmxt_helper.c
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20140609-1' into staging

----------------------------------------------------------------
target-arm queue:
 * support -bios option in vexpress boards
 * register the Cortex-A57 impdef system registers
 * fix handling of UXN bit in ARMv8 page tables
 * complete support of crypto insns in A32/T32
 * implement CRC and crypto insns in A64
 * fix bugs in generic timer control register

----------------------------------------------------------------

# gpg: Signature made Mon 09 Jun 2014 16:08:26 BST using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140609-1:
  target-arm: Delete unused iwmmxt_msadb helper
  target-arm: Fix errors in writes to generic timer control registers
  target-arm: A64: Implement two-register SHA instructions
  target-arm: A64: Implement 3-register SHA instructions
  target-arm: A64: Implement AES instructions
  target-arm: A32/T32: Mask CRC value in calling code, not helper
  target-arm: A64: Implement CRC instructions
  target-arm: VFPv4 implies half-precision extension
  target-arm: Clean up handling of ARMv8 optional feature bits
  target-arm: Remove unnecessary setting of feature bits
  target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64
  target-arm: A64: Use PMULL feature bit for PMULL
  target-arm: add support for v8 VMULL.P64 instruction
  target-arm: Allow 3reg_wide undefreq to encode more bad size options
  target-arm: add support for v8 SHA1 and SHA256 instructions
  target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
  target-arm: Prepare cpreg writefns/readfns for EL3/SecExt
  target-arm/cpu64.c: Actually register Cortex-A57 impdef registers
  vexpress: Add support for the -bios flag to provide firmware

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/14ac57339288...7721a3044234
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