[Qemu-commits] [qemu/qemu] 9ef137: MAINTAINERS: update Calxeda Highbank

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[Qemu-commits] [qemu/qemu] 9ef137: MAINTAINERS: update Calxeda Highbank

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 9ef137: MAINTAINERS: update Calxeda Highbank maintainer an...
Date:	Wed, 28 May 2014 07:30:06 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9ef137cad67bdfdf6adf80c91eea26209f4115ab
      
https://github.com/qemu/qemu/commit/9ef137cad67bdfdf6adf80c91eea26209f4115ab
  Author: Rob Herring <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: update Calxeda Highbank maintainer and status

Signed-off-by: Rob Herring <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fc37b7a0b0cebe4118d172c4fceb0acc2fa25b4a
      
https://github.com/qemu/qemu/commit/fc37b7a0b0cebe4118d172c4fceb0acc2fa25b4a
  Author: Peter Maydell <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M hw/display/pxa2xx_lcd.c

  Log Message:
  -----------
  hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats

The pxa2xx palette entry "16bpp plus transparency" format is
xxxxxxxTRRRRR000GGGGGG00BBBBB000, and "18bpp plus transparency" is
xxxxxxxTRRRRRR00GGGGGG00BBBBBB00.

Correct errors in the code for reading these and converting
them to the internal format. In particular, the buggy code
was attempting to mask out bit 24 of a uint16_t, which
Coverity spotted as an error.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: f0aff25570003fc618c47dec36852fc7d80436ee
      
https://github.com/qemu/qemu/commit/f0aff25570003fc618c47dec36852fc7d80436ee
  Author: Fabian Aggeler <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: implement CPACR register logic for ARMv7

In ARMv7 the CPACR register allows to control access rights to
coprocessor 0-13 interfaces. Bits corresponding to unimplemented
coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are
UNK/SBZP if VFP is not implemented and RAO/WI in some cases.
Treating TRCDIS as RAZ/WI since we neither implement a trace
macrocell nor a CP14 interface to the trace macrocell registers.

Since CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN
bit in the TB flags, flushing the TLB is not necessary anymore.

Signed-off-by: Fabian Aggeler <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9d4c4e872e7598ecbe25437dc4f663b248b2c8a5
      
https://github.com/qemu/qemu/commit/9d4c4e872e7598ecbe25437dc4f663b248b2c8a5
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Move get_mem_index to translate.h

So that it can be shared with the AArch32 code.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a99caa48d89c2d36362b45d513c4952233acb775
      
https://github.com/qemu/qemu/commit/a99caa48d89c2d36362b45d513c4952233acb775
  Author: Peter Maydell <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm/translate.c: Clean up mmu index handling for ldrt/strt

Clean up the mmu index handling for ldrt/strt insns: instead
of a flag 'user' indicating whether to treat the store as user
mode or not, use 'memidx' to indicate the correct memory index to use.

Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: c1197795436f51652bbb253c9422265676264050
      
https://github.com/qemu/qemu/commit/c1197795436f51652bbb253c9422265676264050
  Author: Peter Maydell <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm/translate.c: Use get_mem_index() for SRS memory accesses

The SRS instruction was using a hardcoded 0 for the memory
accesses. This happens to be OK since the SRS instruction is
UNPREDICTABLE in User and System modes, but is awkward if we
want to rearrange the MMU index uses. Switch to using
get_mem_index() like all the other accesses.

Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 6ce2faf43c7a9853f6575a33f77bcf81c115cb66
      
https://github.com/qemu/qemu/commit/6ce2faf43c7a9853f6575a33f77bcf81c115cb66
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: A32: Use get_mem_index for load/stores

Avoid using IS_USER directly as the MMU-idx to simplify future
changes to the MMU layout.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
[PMM: parts relating to LDRT/STRT moved into earlier patches]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f79fbf39e266e6fef3d796ef3884aefb9506b73c
      
https://github.com/qemu/qemu/commit/f79fbf39e266e6fef3d796ef3884aefb9506b73c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Use a 1:1 mapping between EL and MMU index

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6947f05978806a7066fcaeccd8c187d577677328
      
https://github.com/qemu/qemu/commit/6947f05978806a7066fcaeccd8c187d577677328
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Make elr_el1 an array

No functional change.
Prepares for future additions of the EL2 and 3 versions of this reg.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d81c519c40a24a49c96522a0deb834cdde264d77
      
https://github.com/qemu/qemu/commit/d81c519c40a24a49c96522a0deb834cdde264d77
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make esr_el1 an array

No functional change.
Prepares for future addtion of EL2 and 3 versions of this reg.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 68fdb6c5b0b93d6780255d4f82940d7b342079bd
      
https://github.com/qemu/qemu/commit/68fdb6c5b0b93d6780255d4f82940d7b342079bd
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: c12_vbar -> vbar_el[]

No functional change.
Preparation for adding EL2 and 3 versions of this reg.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 73fb3b764b076132fb269475c128a7e9dcb22ed6
      
https://github.com/qemu/qemu/commit/73fb3b764b076132fb269475c128a7e9dcb22ed6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: A64: Add SP entries for EL2 and 3

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1b1742386c82541d65a5068d9d5da42c3b4f61a5
      
https://github.com/qemu/qemu/commit/1b1742386c82541d65a5068d9d5da42c3b4f61a5
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/machine.c

  Log Message:
  -----------
  target-arm: A64: Add ELR entries for EL2 and 3

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 28c9457df08755ef7d98eb58b17e0e0898553b41
      
https://github.com/qemu/qemu/commit/28c9457df08755ef7d98eb58b17e0e0898553b41
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/machine.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add SPSR entries for EL2/HYP and EL3/MON

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2a923c4dde779fc3e5a55886bfa4085e590cbc96
      
https://github.com/qemu/qemu/commit/2a923c4dde779fc3e5a55886bfa4085e590cbc96
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/internals.h
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: A64: Introduce aarch64_banked_spsr_index()

Add aarch64_banked_spsr_index(), used to map an Exception Level
to an index in the banked_spsr array.

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cca7c2f5236bad765a3c613bdc092060830cbc0e
      
https://github.com/qemu/qemu/commit/cca7c2f5236bad765a3c613bdc092060830cbc0e
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Add a feature flag for EL2

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1fe8141ed4a8b0f2b198da7f4b1046a224ab2eb9
      
https://github.com/qemu/qemu/commit/1fe8141ed4a8b0f2b198da7f4b1046a224ab2eb9
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Add a feature flag for EL3

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3b685ba7bfbecd3e765aff66e67b820653619b7d
      
https://github.com/qemu/qemu/commit/3b685ba7bfbecd3e765aff66e67b820653619b7d
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Register EL2 versions of ELR and SPSR

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 81547d663030cfd3508bc8126d015030ddbe9c96
      
https://github.com/qemu/qemu/commit/81547d663030cfd3508bc8126d015030ddbe9c96
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Register EL3 versions of ELR and SPSR

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7ab6c10d008c79d92b0b62e36fb0edc4066d37d6
      
https://github.com/qemu/qemu/commit/7ab6c10d008c79d92b0b62e36fb0edc4066d37d6
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: A64: Forbid ERET to higher or unimplemented ELs

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 14c521d45eb08b2a829b0fa90c682a7f0664ee85
      
https://github.com/qemu/qemu/commit/14c521d45eb08b2a829b0fa90c682a7f0664ee85
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Trap ERET from EL0 at translation time

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: db6c3cd0e7fc58dacba89bf808e2892cd6a18b28
      
https://github.com/qemu/qemu/commit/db6c3cd0e7fc58dacba89bf808e2892cd6a18b28
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: A64: Generalize ERET to various ELs

Adds support for ERET to and from AArch64 EL2 and 3.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 61d4b215d1a19ff9d4cc508c1520f6a485466982
      
https://github.com/qemu/qemu/commit/61d4b215d1a19ff9d4cc508c1520f6a485466982
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/internals.h

  Log Message:
  -----------
  target-arm: A64: Generalize update_spsel for the various ELs

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 855ea66dd5027a2c665a7056c8ba260a75f59101
      
https://github.com/qemu/qemu/commit/855ea66dd5027a2c665a7056c8ba260a75f59101
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Make vbar_write writeback to any CPREG

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d42e3c26cd21677eacca76386b95093f2f67803f
      
https://github.com/qemu/qemu/commit/d42e3c26cd21677eacca76386b95093f2f67803f
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: A64: Register VBAR_EL2

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1ba125c0ca64b604484ddc104e533546d92088a
      
https://github.com/qemu/qemu/commit/a1ba125c0ca64b604484ddc104e533546d92088a
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-05-27 (Tue, 27 May 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: A64: Register VBAR_EL3

Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 052367ba8573809957f1abd288f79fbbda05a284
      
https://github.com/qemu/qemu/commit/052367ba8573809957f1abd288f79fbbda05a284
  Author: Peter Maydell <address@hidden>
  Date:   2014-05-28 (Wed, 28 May 2014)

  Changed paths:
    M MAINTAINERS
    M hw/display/pxa2xx_lcd.c
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper.c
    M target-arm/internals.h
    M target-arm/kvm64.c
    M target-arm/machine.c
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140527' 
into staging

target-arm:
 * Preliminary restructuring for EL2/EL3 support
 * improve CPACR handling
 * fix pxa2xx_lcd palette formats
 * update highbank/midway maintainer

# gpg: Signature made Tue 27 May 2014 17:26:27 BST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found

* remotes/pmaydell/tags/pull-target-arm-20140527: (26 commits)
  target-arm: A64: Register VBAR_EL3
  target-arm: A64: Register VBAR_EL2
  target-arm: Make vbar_write writeback to any CPREG
  target-arm: A64: Generalize update_spsel for the various ELs
  target-arm: A64: Generalize ERET to various ELs
  target-arm: A64: Trap ERET from EL0 at translation time
  target-arm: A64: Forbid ERET to higher or unimplemented ELs
  target-arm: Register EL3 versions of ELR and SPSR
  target-arm: Register EL2 versions of ELR and SPSR
  target-arm: Add a feature flag for EL3
  target-arm: Add a feature flag for EL2
  target-arm: A64: Introduce aarch64_banked_spsr_index()
  target-arm: Add SPSR entries for EL2/HYP and EL3/MON
  target-arm: A64: Add ELR entries for EL2 and 3
  target-arm: A64: Add SP entries for EL2 and 3
  target-arm: c12_vbar -> vbar_el[]
  target-arm: Make esr_el1 an array
  target-arm: Make elr_el1 an array
  target-arm: Use a 1:1 mapping between EL and MMU index
  target-arm: A32: Use get_mem_index for load/stores
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/adbfc34103f0...052367ba8573
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