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[Qemu-commits] [qemu/qemu] 8e03c1: target-i386: Remove unused data from

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 8e03c1: target-i386: Remove unused data from local array
Date: Thu, 15 May 2014 08:30:07 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 8e03c100a7aeb268a7ebfdd98298591a63df0626
      
https://github.com/qemu/qemu/commit/8e03c100a7aeb268a7ebfdd98298591a63df0626
  Author: Stefan Weil <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/kvm.c

  Log Message:
  -----------
  target-i386: Remove unused data from local array

Signed-off-by: Stefan Weil <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: ada4135f84adcacd9294269e22113460650ae1ab
      
https://github.com/qemu/qemu/commit/ada4135f84adcacd9294269e22113460650ae1ab
  Author: Cornelia Huck <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c
    M target-s390x/kvm.c
    M trace-events

  Log Message:
  -----------
  kvm: make one_reg helpers available for everyone

s390x introduced helper functions for getting/setting one_regs with
commit 860643bc. However, nothing about these is s390-specific.

Alexey Kardashevskiy had already posted a general version, so let's
merge the two patches and massage the code a bit.

CC: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: ee11f7a8227bcd9cb8d8141fa8f6a0352f7c0c68
      
https://github.com/qemu/qemu/commit/ee11f7a8227bcd9cb8d8141fa8f6a0352f7c0c68
  Author: Gonglei <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M hw/i386/kvm/pci-assign.c

  Log Message:
  -----------
  pci-assign: Fix a bug when map MSI-X table memory failed

When mmapping memory for the MSI-X table failsthe dev->msix_table is
not set to NULL and assigned_dev_unregister_msix_mmio() will cause
a segfault when trying to munmap it.

Signed-off-by: Gonglei Arei <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>

Signed-off-by: Gonglei <address@hidden>


  Commit: 639973a4740f38789057744b550df3a175bc49ad
      
https://github.com/qemu/qemu/commit/639973a4740f38789057744b550df3a175bc49ad
  Author: Michael S. Tsirkin <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M hw/i386/kvm/pci-assign.c

  Log Message:
  -----------
  pci-assign: limit # of msix vectors

KVM only supports MSIX table size up to 256 vectors,
but some assigned devices support more vectors,
at the moment attempts to assign them fail with EINVAL.

Tweak the MSIX capability exposed to guest to limit table size
to a supported value.

Signed-off-by: Michael S. Tsirkin <address@hidden>
Tested-by: Gonglei <address@hidden>
Cc: address@hidden
Acked-by: Alex Williamson <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 304520291aac95d6a45a3f369f5275e11ef15b2e
      
https://github.com/qemu/qemu/commit/304520291aac95d6a45a3f369f5275e11ef15b2e
  Author: Kevin O'Connor <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/svm_helper.c

  Log Message:
  -----------
  target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c

The svm_load_seg_cache() function calls cpu_x86_load_seg_cache() which
inspects env->eflags.  So, make sure all changes to eflags are done
prior to loading the segment cache.

Signed-off-by: Kevin O'Connor <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 010e639a8dd3848c7994aae288c218c6ea52a819
      
https://github.com/qemu/qemu/commit/010e639a8dd3848c7994aae288c218c6ea52a819
  Author: Kevin O'Connor <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/smm_helper.c

  Log Message:
  -----------
  target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in 
smm_helper.c

The cpu_x86_load_seg_cache() function inspects cr0 and eflags, so make
sure all changes to eflags and cr0 are done prior to loading the
segment caches.

Signed-off-by: Kevin O'Connor <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: fd460606fd6f356ddcf424558ed67664e8d46eb4
      
https://github.com/qemu/qemu/commit/fd460606fd6f356ddcf424558ed67664e8d46eb4
  Author: Kevin O'Connor <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/seg_helper.c

  Log Message:
  -----------
  target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in 
seg_helper.c

The cpu_x86_load_seg_cache() function inspects eflags, so make sure
all changes to eflags are done prior to loading the segment caches.

Signed-off-by: Kevin O'Connor <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 7848c8d19f8556666df25044bbd5d8b29439c368
      
https://github.com/qemu/qemu/commit/7848c8d19f8556666df25044bbd5d8b29439c368
  Author: Kevin O'Connor <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M bsd-user/main.c
    M linux-user/main.c
    M target-i386/cpu.h
    M target-i386/seg_helper.c
    M target-i386/svm_helper.c

  Log Message:
  -----------
  target-i386: the x86 CPL is stored in CS.selector - auto update hflags 
accordingly.

Instead of manually calling cpu_x86_set_cpl() when the CPL changes,
check for CPL changes on calls to cpu_x86_load_seg_cache(R_CS).  Every
location that called cpu_x86_set_cpl() also called
cpu_x86_load_seg_cache(R_CS), so cpu_x86_set_cpl() is no longer
required.

This fixes the SMM handler code as it was not setting/restoring the
CPL level manually.

Signed-off-by: Kevin O'Connor <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 50a2c6e55fa2ce5a2916a2c206bad2c6b0e06df1
      
https://github.com/qemu/qemu/commit/50a2c6e55fa2ce5a2916a2c206bad2c6b0e06df1
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c
    M target-arm/cpu.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/kvm_arm.h
    M target-i386/cpu.c
    M target-i386/kvm.c
    M target-i386/kvm_i386.h
    M target-ppc/kvm.c
    M target-s390x/cpu.c
    M target-s390x/cpu.h
    M target-s390x/kvm.c

  Log Message:
  -----------
  kvm: reset state from the CPU's reset method

Now that we have a CPU object with a reset method, it is better to
keep the KVM reset close to the CPU reset.  Using qemu_register_reset
as we do now keeps them far apart.

With this patch, PPC no longer calls the kvm_arch_ function, so
it can get removed there.  Other arches call it from their CPU
reset handler, and the function gets an ARMCPU/X86CPU/S390CPU.

Note that ARM- and s390-specific functions are called kvm_arm_*
and kvm_s390_*, while x86-specific functions are called kvm_arch_*.
That follows the convention used by the different architectures.
Changing that is the topic of a separate patch.

Reviewed-by: Gleb Natapov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: e0723c451028102d9165e21424b4833376ce9666
      
https://github.com/qemu/qemu/commit/e0723c451028102d9165e21424b4833376ce9666
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/helper.c
    M target-i386/kvm.c
    M target-i386/kvm_i386.h

  Log Message:
  -----------
  kvm: forward INIT signals coming from the chipset

Reviewed-by: Gleb Natapov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 05e7e819d7d159a75a46354aead95e1199b8f168
      
https://github.com/qemu/qemu/commit/05e7e819d7d159a75a46354aead95e1199b8f168
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/cpu.c
    M target-i386/cpu.h

  Log Message:
  -----------
  target-i386: fix set of registers zeroed on reset

BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
should be (Intel Instruction Set Extensions Programming Reference
319433-015, pages 9-4 and 9-6).  Same for YMM.

XCR0 should be reset to 1.

TSC and TSC_RESET were zeroed already by the memset, remove the explicit
assignments.

Cc: Andreas Faerber <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 43175fa96add507afee6c0a83ec9ffe0ca130fc3
      
https://github.com/qemu/qemu/commit/43175fa96add507afee6c0a83ec9ffe0ca130fc3
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M target-i386/cpu.c
    M target-i386/cpu.h
    M target-i386/helper.c

  Log Message:
  -----------
  target-i386: preserve FPU and MSR state on INIT

Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not
be zeroed on INIT (Table 9-1 in the Intel SDM).  Copy them out of
CPUX86State and back in, instead of special casing env->pat.

The relevant fields are already consecutive except PAT and SMBASE.
However:

- KVM and Hyper-V MSRs should be reset because they include memory
locations written by the hypervisor.  These MSRs are moved together
at the end of the preserved area.

- SVM state can be moved out of the way since it is written by VMRUN.

Cc: Andreas Faerber <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 7b4d915e11ae7afb2d42a8cae90db26bc0c142b8
      
https://github.com/qemu/qemu/commit/7b4d915e11ae7afb2d42a8cae90db26bc0c142b8
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M hw/intc/apic_common.c

  Log Message:
  -----------
  apic: do not accept SIPI on the bootstrap processor

SIPI interrupts are ignored on the bootstrap.  Never accept one.

Cc: Andreas Faerber <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 4a92a558f49cb0693e36bd6d4f9217f298045be2
      
https://github.com/qemu/qemu/commit/4a92a558f49cb0693e36bd6d4f9217f298045be2
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M cpu-exec.c
    M include/exec/cpu-all.h
    M target-i386/cpu.h
    M target-ppc/cpu.h

  Log Message:
  -----------
  cpu: make CPU_INTERRUPT_RESET available on all targets

On the x86, some devices need access to the CPU reset pin (INIT#).
Provide a generic service to do this, using one of the internal
cpu_interrupt targets.  Generalize the PPC-specific code for
CPU_INTERRUPT_RESET to other targets.

Since PPC does not support migration across QEMU versions (its
machine types are not versioned yet), I picked the value that
is used on x86, CPU_INTERRUPT_TGT_INT_1.  Consequently, TGT_INT_2
and TGT_INT_3 are shifted down by one while keeping their value.

Reviewed-by: Anthony Liguori <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: 4700a316df7d2cdcd256dcd64a10cec643f4dfa1
      
https://github.com/qemu/qemu/commit/4700a316df7d2cdcd256dcd64a10cec643f4dfa1
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-05-13 (Tue, 13 May 2014)

  Changed paths:
    M hw/i386/pc.c

  Log Message:
  -----------
  pc: port 92 reset requires a low->high transition

The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.

This bug is masked right now because a full reset will clear the
value of port 92h.  But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.

Reviewed-by: Anthony Liguori <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>


  Commit: ef3cb5ca82c341e575ee5cb9a9dd8edc6aa96b1b
      
https://github.com/qemu/qemu/commit/ef3cb5ca82c341e575ee5cb9a9dd8edc6aa96b1b
  Author: Peter Maydell <address@hidden>
  Date:   2014-05-15 (Thu, 15 May 2014)

  Changed paths:
    M bsd-user/main.c
    M cpu-exec.c
    M hw/i386/kvm/pci-assign.c
    M hw/i386/pc.c
    M hw/intc/apic_common.c
    M include/exec/cpu-all.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M linux-user/main.c
    M target-arm/cpu.c
    M target-arm/kvm32.c
    M target-arm/kvm64.c
    M target-arm/kvm_arm.h
    M target-i386/cpu.c
    M target-i386/cpu.h
    M target-i386/helper.c
    M target-i386/kvm.c
    M target-i386/kvm_i386.h
    M target-i386/seg_helper.c
    M target-i386/smm_helper.c
    M target-i386/svm_helper.c
    M target-ppc/cpu.h
    M target-ppc/kvm.c
    M target-s390x/cpu.c
    M target-s390x/cpu.h
    M target-s390x/kvm.c
    M trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/kvm/uq/master' into staging

* remotes/kvm/uq/master:
  pc: port 92 reset requires a low->high transition
  cpu: make CPU_INTERRUPT_RESET available on all targets
  apic: do not accept SIPI on the bootstrap processor
  target-i386: preserve FPU and MSR state on INIT
  target-i386: fix set of registers zeroed on reset
  kvm: forward INIT signals coming from the chipset
  kvm: reset state from the CPU's reset method
  target-i386: the x86 CPL is stored in CS.selector - auto update hflags 
accordingly.
  target-i386: set eflags prior to calling cpu_x86_load_seg_cache() in 
seg_helper.c
  target-i386: set eflags and cr0 prior to calling cpu_x86_load_seg_cache() in 
smm_helper.c
  target-i386: set eflags prior to calling svm_load_seg_cache() in svm_helper.c
  pci-assign: limit # of msix vectors
  pci-assign: Fix a bug when map MSI-X table memory failed
  kvm: make one_reg helpers available for everyone
  target-i386: Remove unused data from local array

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/06e33c1c3c19...ef3cb5ca82c3
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