[Qemu-commits] [qemu/qemu] 6a450d: PPC: E500: Set PIR default reset value rather than...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6a450df9b8369c0cff7a1d6774d56f0862abd4e3
      
https://github.com/qemu/qemu/commit/6a450df9b8369c0cff7a1d6774d56f0862abd4e3
  Author: Alexander Graf <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M hw/ppc/e500.c

  Log Message:
  -----------
  PPC: E500: Set PIR default reset value rather than SPR value

We now reset SPRs to their reset values on CPU reset. So if we want
to have an SPR persistently changed, we need to change its default
reset value rather than the value itself manually.

Do this for SPR_BOOKE_PIR, fixing e500v2 SMP boot.

Reported-by: Frederic Konrad <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Tested-by: KONRAD Frederic <address@hidden>


  Commit: 3636226ae45a9b04af5202a18f445680c88473e7
      
https://github.com/qemu/qemu/commit/3636226ae45a9b04af5202a18f445680c88473e7
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF

  Log Message:
  -----------
  pseries: Update SLOF firmware image to qemu-slof-20140404

The change log is:
  > Isolate sc 1 detection logic
  > build: auto-detect ppc64 architecture
  > cas: increase hcall buffer size to accomodate 256 cpus
  > usb: change device tree naming
  > usb-core: adjust port numbers in set_address
  > virtio-scsi: correct srplun comment
  > Fix kernel loading
  > Workaround to make grub2 assign server ip from dhcp ack packet only
  > ELF: Enter LE binary in LE mode
  > ELF loading should fail for virt != phys

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a13d44896854329581ba48607d66c6b2aec157f7
      
https://github.com/qemu/qemu/commit/a13d44896854329581ba48607d66c6b2aec157f7
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M fpu/softfloat.c
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: Introduce float32_to_uint64_round_to_zero

This change adds the float32_to_uint64_round_to_zero function to the softfloat
library.  This function fills out the complement of float32 to INT round-to-zero
conversion rountines, where INT is {int32_t, uint32_t, int64_t, uint64_t}.

This contribution can be licensed under either the softfloat-2a or -2b
license.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0453099b7d20c9fc2946ed74f1d965ae4d173d19
      
https://github.com/qemu/qemu/commit/0453099b7d20c9fc2946ed74f1d965ae4d173d19
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Bug: VSX Convert to Integer Should Truncate

The various VSX Convert to Integer instructions should truncate the
floating point number to an integer value, which is equivalent to
a round-to-zero rounding mode.  The existing VSX floating point to
integer conversion helpers are erroneously using the rounding mode set
int the PowerPC Floating Point Status and Control Register (FPSCR).
This change corrects this defect by using the appropriate
float*_to_*_round_to_zero() routines fro the softfloat library.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 80189035de73f30e42a7f933c45cccfc4b0c56e9
      
https://github.com/qemu/qemu/commit/80189035de73f30e42a7f933c45cccfc4b0c56e9
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Define Endian-Correct Accessors for VSR Field Access

This change defines accessors for VSR doubleword and word fields that
are correct from a host Endian perspective.  This allows code to
use the Power ISA indexing numbers in code.

For example, the xscvdpsxws instruction has a target VSR that looks
like this:

  0           32       64                    127
  +-----------+--------+-----------+-----------+
  | undefined | SW     | undefined | undefined |
  +-----------+--------+-----------+-----------+

VSX helper code will use VsrW(1) to access this field.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d359db00e6dfaf12cbdedd30e36f879110d4f9d1
      
https://github.com/qemu/qemu/commit/d359db00e6dfaf12cbdedd30e36f879110d4f9d1
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Correct LE Host Inversion of Lower VSRs

This change properly orders the doublewords of the VSRs 0-31.  Because these
registers are constructed from separate doublewords, they must be inverted
on Little Endian hosts.  The inversion is performed both when the VSR is read
and when it is written.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bcb7652e8dd185f2acc36fd2b9eb7b6dffcc8c47
      
https://github.com/qemu/qemu/commit/bcb7652e8dd185f2acc36fd2b9eb7b6dffcc8c47
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Correct Simple VSR LE Host Inversions

A common pattern in the VSX helper code macros is the use of "x.fld[i]" where
"x" is a VSR and "fld" is an argument to a macro ("f64" or "f32" is passed).
This is not always correct on LE hosts.

This change addresses all instances of this pattern to be "x.fld" where "fld" 
is:

  - "VsrD(0)" for scalar instructions accessing 64-bit numbers
  - "VsrD(i)" for vector instructions accessing 64-bit numbers
  - "VsrW(i)" for vector instructions accessing 32-bit numbers

Note that there are no instances of this pattern where a scalar instruction
accesses a 32-bit number.

Note also that it would be correct to use "VsrD(i)" for scalar instructions 
since
the loop index is only ever "0".  I have choosen to use "VsrD(0)" instead ... it
seems a little clearer.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 50fc89e7b1a2837a2d92025aa2ed161d8439743b
      
https://github.com/qemu/qemu/commit/50fc89e7b1a2837a2d92025aa2ed161d8439743b
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Correct VSX Scalar Compares

This change fixes the VSX scalar compare instructions.  The existing usage of 
"x.f64[0]"
is changed to "x.VsrD(0)".

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6bbad7a91efe49b080391a45bc6305449050465a
      
https://github.com/qemu/qemu/commit/6bbad7a91efe49b080391a45bc6305449050465a
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Correct VSX FP to FP Conversions

This change corrects the VSX double precision to single precision and
single precision to double precisions conversion routines.  The endian
correct accessors are now used.  The auxiliary "j" index is no longer
necessary and is eliminated.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d1dec5ef550802f76ffb8cdec50e6d50467e877e
      
https://github.com/qemu/qemu/commit/d1dec5ef550802f76ffb8cdec50e6d50467e877e
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Correct VSX FP to Integer Conversion

This patch corrects the VSX floating point to integer conversion
instructions by using the endian correct accessors.  The auxiliary
"j" index used by the existing macros is now obsolete and is removed.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6cd7db3d92d44344d75feb432e3ece8587e1afd4
      
https://github.com/qemu/qemu/commit/6cd7db3d92d44344d75feb432e3ece8587e1afd4
  Author: Tom Musta <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Correct VSX Integer to FP Conversion

This patch corrects the VSX integer to floating point conversion instructions
by using the endian correct accessors.  The auxiliary "j" index used by the
existing macros is now obsolete and is removed.  The JOFFSET preprocessor
macro is also obsolete and removed.

Signed-off-by: Tom Musta <address@hidden>
Tested-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e81a982aa5398269a2cc344091ffa4930bdd242f
      
https://github.com/qemu/qemu/commit/e81a982aa5398269a2cc344091ffa4930bdd242f
  Author: Alexander Graf <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M hw/ppc/ppc.c
    M include/hw/ppc/ppc.h
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c

  Log Message:
  -----------
  PPC: Clean up DECR implementation

There are 3 different variants of the decrementor for BookE and BookS.

The BookE variant sets TSR[DIS] to 1 when the DEC value becomes 1 or 0. TSR[DIS]
is then the indicator whether the decrementor interrupt line is asserted or not.

The old BookS variant treats DEC as an edge interrupt that gets triggered when
the DEC value's top bit turns 1 from 0.

The new BookS variant maintains the assertion bit inside DEC itself. Whenever
the DEC value becomes negative (top bit set) the DEC interrupt line is asserted.

So far we implemented mostly the old BookS variant. Let's do them all properly.

This fixes booting pseries ppc64 guest images in TCG mode for me.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 05edc26c61d416831822b3186df099e8e21745b9
      
https://github.com/qemu/qemu/commit/05edc26c61d416831822b3186df099e8e21745b9
  Author: Alexander Graf <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/helper_regs.h

  Log Message:
  -----------
  PPC: Only enter MSR_POW when no interrupts pending

We were entering the power saving state even when interrupts (like an
external interrupt or a decrementer interrupt) were still in flight.

In case we find a pending interrupt, don't enter power saving state.

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Tom Musta <address@hidden>


  Commit: 6a2b3d89fa49ec060db646d196864a8fd15c10cf
      
https://github.com/qemu/qemu/commit/6a2b3d89fa49ec060db646d196864a8fd15c10cf
  Author: Alexander Graf <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M hw/ppc/ppce500_spin.c

  Log Message:
  -----------
  ppce500_spin: Initialize struct properly

The spinning struct is in guest endianness, so we need to initialize
its variables in guest endianness too.

This fixes booting e500 guests with SMP on x86 for me.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 06f6e12491fd767b3b23573c438f925f6092e897
      
https://github.com/qemu/qemu/commit/06f6e12491fd767b3b23573c438f925f6092e897
  Author: Alexander Graf <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  PPC: Add l1 cache sizes for 970 and above systems

Book3s_64 guests expect the L1 cache size in device tree, so let's give
them proper values for all CPU types we support.

This fixes a "not compliant" warning with sles11 guests on -M pseries for me.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9a4fb6aa19d1aa8dfb3abb6210734b1a1df9e322
      
https://github.com/qemu/qemu/commit/9a4fb6aa19d1aa8dfb3abb6210734b1a1df9e322
  Author: Peter Maydell <address@hidden>
  Date:   2014-04-08 (Tue, 08 Apr 2014)

  Changed paths:
    M fpu/softfloat.c
    M hw/ppc/e500.c
    M hw/ppc/ppc.c
    M hw/ppc/ppce500_spin.c
    M include/fpu/softfloat.h
    M include/hw/ppc/ppc.h
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/fpu_helper.c
    M target-ppc/helper_regs.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' 
into staging

Patch queue for ppc - 2014-04-08

This is the final queue for 2.0! It fixes a lot of bugs people have
seen during testing:

  - Fix e500 SMP
  - Fix book3s_64 DEC
  - Fix VSX (new feature in 2.0) for LE hosts
  - Fix PR KVM on top of pHyp (SLOF update)

# gpg: Signature made Tue 08 Apr 2014 10:24:18 BST using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found

* remotes/agraf/tags/signed-ppc-for-upstream:
  PPC: Add l1 cache sizes for 970 and above systems
  ppce500_spin: Initialize struct properly
  PPC: Only enter MSR_POW when no interrupts pending
  PPC: Clean up DECR implementation
  target-ppc: Correct VSX Integer to FP Conversion
  target-ppc: Correct VSX FP to Integer Conversion
  target-ppc: Correct VSX FP to FP Conversions
  target-ppc: Correct VSX Scalar Compares
  target-ppc: Correct Simple VSR LE Host Inversions
  target-ppc: Correct LE Host Inversion of Lower VSRs
  target-ppc: Define Endian-Correct Accessors for VSR Field Access
  target-ppc: Bug: VSX Convert to Integer Should Truncate
  softfloat: Introduce float32_to_uint64_round_to_zero
  pseries: Update SLOF firmware image to qemu-slof-20140404
  PPC: E500: Set PIR default reset value rather than SPR value

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e792933ce1a9...9a4fb6aa19d1