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[Qemu-commits] [qemu/qemu] 7f6613: target-mips: fix MTHC1 and MFHC1 when
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[Qemu-commits] [qemu/qemu] 7f6613: target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 ... |
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Tue, 25 Mar 2014 16:00:06 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 7f6613cedc59fa849105668ae971dc31004bca1c
https://github.com/qemu/qemu/commit/7f6613cedc59fa849105668ae971dc31004bca1c
Author: Petar Jovanovic <address@hidden>
Date: 2014-03-25 (Tue, 25 Mar 2014)
Changed paths:
M target-mips/translate.c
Log Message:
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target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode
Previous implementation presumed that FPU registers are 64-bit and are
working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not
set, it does load/store from the odd numbered register pair.
Patch by Matthew Fortune.
Signed-off-by: Matthew Fortune <address@hidden>
Signed-off-by: Petar Jovanovic <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
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