[Qemu-commits] [qemu/qemu] 9948c3: vexpress: Set reset-cbar property for CPUs

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9948c38bd9aef8fa762a1b62b9fccc35e11a6fd5
      
https://github.com/qemu/qemu/commit/9948c38bd9aef8fa762a1b62b9fccc35e11a6fd5
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M hw/arm/vexpress.c

  Log Message:
  -----------
  vexpress: Set reset-cbar property for CPUs

Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12)
now assume that if the CPU is a Cortex-A9 and the reset value of the
PERIPHBASE/CBAR register is zero then the CPU is a specific buggy
single core A9 SoC, and will not try to start other cores. Since we
now have a CPU property for the reset value of the CBAR, we can
just fix the vexpress board model to correctly set CBAR so SMP
works again. To avoid duplicate boilerplate code in both the A9
and A15 daughterboard init functions, we split out the CPU and
private memory region init to its own function.

Signed-off-by: Peter Maydell <address@hidden>
Reported-by: Rob Herring <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: b5a3ca3e3028ab86131920b45a19d553f278bdb4
      
https://github.com/qemu/qemu/commit/b5a3ca3e3028ab86131920b45a19d553f278bdb4
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M hw/arm/realview.c

  Log Message:
  -----------
  realview-pbx-a9: Set reset-cbar property for CPUs

If the CPU is a Cortex-A9 then we should set its reset-cbar property
so that the guest can read the correct PERIPHBASE/CBAR register value;
newer versions of the Linux kernel (as of commit bc41b8724 in 3.12)
will otherwise assume the CPU is a buggy single core A9 SoC. The
realview-pbx-a9 is the only one of the cluster of boards in realview.c
which works with the Cortex-A9 (ie which gets an a9mpcore_priv device);
make sure it also has reset-cbar set correctly.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 4719ab918a837fb12f34599139f2c7c0137ca703
      
https://github.com/qemu/qemu/commit/4719ab918a837fb12f34599139f2c7c0137ca703
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M hw/arm/exynos4210.c

  Log Message:
  -----------
  exynos4210: Set reset-cbar property of Cortex-A9 CPUs

Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9
CPUs, so that Linux doesn't misrecognize them as a broken
uniprocessor SoC.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: ba7500852d8c3926a732892236765eee1bcaea93
      
https://github.com/qemu/qemu/commit/ba7500852d8c3926a732892236765eee1bcaea93
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  virt: Set reset-cbar on CPUs

Set the reset-cbar property on CPUs used by the virt board,
if they have it. This isn't necessary for correct functioning
under Linux (since the A9 isn't a valid CPU for the virt board),
but it is the correct behaviour.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: d6d60581f3f6778de85ee23427006151b5226667
      
https://github.com/qemu/qemu/commit/d6d60581f3f6778de85ee23427006151b5226667
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Add ARM_CP_IO notation to PMCR reginfo

Now that the PMCR writefn makes timer accesses, its reginfo needs
the ARM_CP_IO flag, so that icount mode works correctly. (Fixes
the bug accidentally introduced in commit 7c2cb42b).

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: a984e42c916ad5afdf3f8660f284857547943aa4
      
https://github.com/qemu/qemu/commit/a984e42c916ad5afdf3f8660f284857547943aa4
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: A64: Implement PMULL instruction

Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.

Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
bit on it, even though we're using more feature bits than a single
"crypto extension present/not present" toggle.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: cf4ab1af296b8ef5d5a1dc65fda804b88ddd0553
      
https://github.com/qemu/qemu/commit/cf4ab1af296b8ef5d5a1dc65fda804b88ddd0553
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Fix bug in add_sub_ext handling of rn

rn == 31 always means SP (not XZR) whether an add_sub_ext
instruction is setting the flags or not; only rd has behaviour
dependent on whether we are setting flags.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 10113b6903c0256c1741918430b0304c5a60b7a8
      
https://github.com/qemu/qemu/commit/10113b6903c0256c1741918430b0304c5a60b7a8
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add last AdvSIMD Integer to FP ops

This adds the remaining [US]CVTF operations to the SIMD
shift-immediate, scalar-shift-immediate, two-reg-misc and
scalar-two-reg-misc groups of opcodes.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: added scalar 2-misc and scalar-shift-imm encodings]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f612537e0706761d5692deaa72516695ef0a2ac8
      
https://github.com/qemu/qemu/commit/f612537e0706761d5692deaa72516695ef0a2ac8
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add FSQRT to C3.6.17 (two misc)

Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: b05c3068577f6caea6f1911b9e03d52dbf84f475
      
https://github.com/qemu/qemu/commit/b05c3068577f6caea6f1911b9e03d52dbf84f475
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add remaining CLS/Z vector ops

Implement the CLS, CLZ operations in the 2-reg-misc category.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: c1b876b2e9a47e3e36be57a4f3d167b19c5f586a
      
https://github.com/qemu/qemu/commit/c1b876b2e9a47e3e36be57a4f3d167b19c5f586a
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Saturating and narrowing shift ops

This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are
saturating and narrowing shift right operations. These are used in
things like libav. Note signed shifts can have an "unsigned" saturating
narrow operation which will floor negative values.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: Added the scalar encodings, style tweaks]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6781fa119f3f403bcab59142faa9581aff974358
      
https://github.com/qemu/qemu/commit/6781fa119f3f403bcab59142faa9581aff974358
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP

Implement the SADDLP, UADDLP, SADALP and UADALP instructions
in the SIMD 2-reg misc category.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 73a81d10fda3cb45e62efd6829f19debb9f54073
      
https://github.com/qemu/qemu/commit/73a81d10fda3cb45e62efd6829f19debb9f54073
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement SHLL, SHLL2

Implement the SHLL and SHLL2 instructions from the 2-reg-misc
category.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 04c7c6c261c3000c851eb177a7d32236828f4be2
      
https://github.com/qemu/qemu/commit/04c7c6c261c3000c851eb177a7d32236828f4be2
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions

Implement the floating-point-to-integer conversion instructions
FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc
categories.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 261a5b4dd1dc6c68b274cc39bb5d4d236b24d4cd
      
https://github.com/qemu/qemu/commit/261a5b4dd1dc6c68b274cc39bb5d4d236b24d4cd
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement FCVTN

Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD
2-reg-misc category.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 931c8cc270793877f8d7bf9934ac9fa3fb7800be
      
https://github.com/qemu/qemu/commit/931c8cc270793877f8d7bf9934ac9fa3fb7800be
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement FCVTL

Implement FCVTL, the only instruction in the 2-reg-misc group
which widens from size to 2*size elements.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a566da1b02704a79038043ddbe850f40b033cd63
      
https://github.com/qemu/qemu/commit/a566da1b02704a79038043ddbe850f40b033cd63
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: List unsupported shift-imm opcodes

Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 8f0c6758b0e1c3b9676e7c3ccea8a176537cf843
      
https://github.com/qemu/qemu/commit/8f0c6758b0e1c3b9676e7c3ccea8a176537cf843
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add FRECPX (reciprocal exponent)

These are fairly simple exponent only estimation functions using helpers.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 37a706adbf96fbb05abbb8b17b14aebee266f2d1
      
https://github.com/qemu/qemu/commit/37a706adbf96fbb05abbb8b17b14aebee266f2d1
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement SRI

Implement SRI (shift right and insert).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 03df01ed9a83a22790f3fd1cfbe7fc48caf9bfd0
      
https://github.com/qemu/qemu/commit/03df01ed9a83a22790f3fd1cfbe7fc48caf9bfd0
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement FRINT*

Implement the FRINT* round-to-integral operations from
the 2-reg-misc category.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 14dcdac82f398cbac874c8579b9583fab31c67bf
      
https://github.com/qemu/qemu/commit/14dcdac82f398cbac874c8579b9583fab31c67bf
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M include/exec/exec-all.h

  Log Message:
  -----------
  exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder

The ARM A64 decoder's worst case number of TCG ops per instruction
is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures
store). Raise the MAX_OP_PER_INSTR define accordingly.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: a847f32c04538e92675c7b27f5f60d2eaad3e56c
      
https://github.com/qemu/qemu/commit/a847f32c04538e92675c7b27f5f60d2eaad3e56c
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL

Implement the saturating left shift instructions SQSHL, SQSHLU
and UQSHL for the scalar-shift-imm and shift-imm categories.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2ed3ea110f47a7e3639281edb1d6483b1efce6c3
      
https://github.com/qemu/qemu/commit/2ed3ea110f47a7e3639281edb1d6483b1efce6c3
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories

Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm
categories; this completes the implementation of those two groups.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7baeabce1d25c667d0ec7e4e74a1312e0b887b54
      
https://github.com/qemu/qemu/commit/7baeabce1d25c667d0ec7e4e74a1312e0b887b54
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M fpu/softfloat.c
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: export squash_input_denormal functions

I need these available outside of softfloat for some of the reciprocal
processing in aarch64 helper functions.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: b6d4443a7bf607c5ca5d4b8dabffc421e571f4eb
      
https://github.com/qemu/qemu/commit/b6d4443a7bf607c5ca5d4b8dabffc421e571f4eb
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE

Implement URECPE and FRECPE instructions in both scalar and vector forms.
The actual reciprocal estimate function is shared with the A32/T32 Neon
code. However in A64 we aren't using the Neon "standard FPSCR value"
so extra checks are necessary to handle non-squashed denormal inputs
which can never happen for A32/T32. Calling conventions for the helpers
are thus modified to pass the fpst directly; we mark the helpers as
TCG_CALL_NO_RWG since we're changing the declarations anyway.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 8b092ca9ef06fd308ecf1d46c805f938a95acc21
      
https://github.com/qemu/qemu/commit/8b092ca9ef06fd308ecf1d46c805f938a95acc21
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Move handle_2misc_narrow function

Move the handle_2misc_narrow() function up the file so that it can
be called from disas_simd_scalar_two_reg_misc().

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 5201c13654c35e5e0173a9947848f3a9f9a5a8bc
      
https://github.com/qemu/qemu/commit/5201c13654c35e5e0173a9947848f3a9f9a5a8bc
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement scalar saturating narrow ops

This completes the set of integer narrowing saturating ops including:
     SQXTN, SQXTN2
     SQXTUN, SQXTUN2
     UQXTN, UQXTN2

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 5553955eb6ec890f324a2ff6c6cc1365b98b981f
      
https://github.com/qemu/qemu/commit/5553955eb6ec890f324a2ff6c6cc1365b98b981f
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement FCVTXN

Implement the FCVTXN operation, which does a narrowing fp precision
conversion using the "round to odd" (von Neumann) mode. This can
conveniently be implemented as "do operation using round to zero;
then set the LSB of the mantissa to 1 if the Inexact flag was set".

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: c2fb418e35be3eb1f60987174f94c029f7d4dd7d
      
https://github.com/qemu/qemu/commit/c2fb418e35be3eb1f60987174f94c029f7d4dd7d
  Author: Alex Bennée <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)

This adds support for [UF]RSQRTE instructions. It utilises the existing
NEON helpers with some changes. The changes include an explicit passing
of fpstatus (so the correct one is used between arm32 and aarch64),
denormilzation, more correct error handling and also proper scaling of
the fraction going into the estimate.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1ed27a17cd9d9ebec8963bc358d74060b1dd6127
      
https://github.com/qemu/qemu/commit/1ed27a17cd9d9ebec8963bc358d74060b1dd6127
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-17 (Mon, 17 Mar 2014)

  Changed paths:
    M scripts/qemu-binfmt-conf.sh

  Log Message:
  -----------
  scripts/qemu-binfmt-conf.sh: Add AArch64 registration

Add the binfmt-misc magic needed to register QEMU for handling AArch64
ELF binaries.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2dda43bacc79f8e283702614745cd700c637de64
      
https://github.com/qemu/qemu/commit/2dda43bacc79f8e283702614745cd700c637de64
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-18 (Tue, 18 Mar 2014)

  Changed paths:
    M fpu/softfloat.c
    M hw/arm/exynos4210.c
    M hw/arm/realview.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M include/exec/exec-all.h
    M include/fpu/softfloat.h
    M scripts/qemu-binfmt-conf.sh
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140317' 
into staging

target-arm queue:
 * more A64 Neon instructions
 * fixes to reset CBAR values for A9 and A15 boards
 * fix accesses to PMCR register in -icount mode

# gpg: Signature made Mon 17 Mar 2014 22:04:52 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140317: (30 commits)
  scripts/qemu-binfmt-conf.sh: Add AArch64 registration
  target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
  target-arm: A64: Implement FCVTXN
  target-arm: A64: Implement scalar saturating narrow ops
  target-arm: A64: Move handle_2misc_narrow function
  target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
  softfloat: export squash_input_denormal functions
  target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
  target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
  exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
  target-arm: A64: Implement FRINT*
  target-arm: A64: Implement SRI
  target-arm: A64: Add FRECPX (reciprocal exponent)
  target-arm: A64: List unsupported shift-imm opcodes
  target-arm: A64: Implement FCVTL
  target-arm: A64: Implement FCVTN
  target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
  target-arm: A64: Implement SHLL, SHLL2
  target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
  target-arm: A64: Saturating and narrowing shift ops
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/315b59344126...2dda43bacc79