qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] af5199: target-arm: Fix incorrect setting of


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] af5199: target-arm: Fix incorrect setting of E bit in CPSR
Date: Tue, 11 Mar 2014 07:30:04 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: af5199347a874db2214bf818151bad71b856ff37
      
https://github.com/qemu/qemu/commit/af5199347a874db2214bf818151bad71b856ff37
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix incorrect setting of E bit in CPSR

Commit 4cc35614a moved the exception mask bits out of env->uncached_cpsr
and into env->daif. However the env->daif contents are AArch64 style
mask bits, which include not just the AArch32 AIF bits but also the
new D bit (masks debug exceptions). This means that when reconstructing
the AArch32 CPSR value we must not allow the D bit in env->daif to get
into the CPSR, because the corresponding bit in the CPSR is E, the
endianness bit.

This bug didn't affect execution under TCG because we don't implement
endianness-swapping and so simply ignored the E bit; however it meant
that kernel booting under KVM failed, because KVM does honour the E bit.

Reported-by: Alexey Ignatov <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7c2cb42b5033a851aa2a81de8d8a9e75bb65c2b6
      
https://github.com/qemu/qemu/commit/7c2cb42b5033a851aa2a81de8d8a9e75bb65c2b6
  Author: Alistair Francis <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implements the ARM PMCCNTR register

This patch implements the ARM PMCCNTR register including
the disable and reset components of the PMCR register.

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0624976f6166fe3d59477f4c08d5cdd7c1edc7d1
      
https://github.com/qemu/qemu/commit/0624976f6166fe3d59477f4c08d5cdd7c1edc7d1
  Author: Richard Henderson <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Fix intptr_t vs tcg_target_long

Fixes a build error when these are different, e.g. x32.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b29c8f115de5f48f0019afc2c779cf64e5fcefaf
      
https://github.com/qemu/qemu/commit/b29c8f115de5f48f0019afc2c779cf64e5fcefaf
  Author: Stefan Weil <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M disas/libvixl/a64/disasm-a64.cc

  Log Message:
  -----------
  libvixl: Fix format strings for several int64_t values

"%d" or "%x" won't work on hosts where int values are smaller than 64 bit.

Signed-off-by: Stefan Weil <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 43a32ed68f3aac5ccde4fa6fa4a158e9e8153c94
      
https://github.com/qemu/qemu/commit/43a32ed68f3aac5ccde4fa6fa4a158e9e8153c94
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M hw/arm/pxa2xx.c
    M hw/arm/pxa2xx_gpio.c
    M hw/arm/pxa2xx_pic.c

  Log Message:
  -----------
  pxa2xx: Don't shift into sign bit

Add  missing 'U' suffixes to avoid potentially shifting into
the sign bit of a signed integer.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: d2f41a1169bb0357bd863296b1a664fe2af10acd
      
https://github.com/qemu/qemu/commit/d2f41a1169bb0357bd863296b1a664fe2af10acd
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M hw/arm/omap1.c

  Log Message:
  -----------
  hw/arm/omap1.c: Avoid shifting left into sign bit

Add missing 'U' suffix to avoid shifting left into sign bit.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: c8f8f9fb2b8bd832be7e87c548929e40113e8e3d
      
https://github.com/qemu/qemu/commit/c8f8f9fb2b8bd832be7e87c548929e40113e8e3d
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit

Add missing 'U' suffix to avoid shifting left into sign bit of
a signed integer.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 2b194951c592ad670ddf3bc5764216408ade46f8
      
https://github.com/qemu/qemu/commit/2b194951c592ad670ddf3bc5764216408ade46f8
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M hw/arm/musicpal.c

  Log Message:
  -----------
  hw/arm/musicpal: Avoid shifting left into sign bit

Add missing 'U' suffixes to avoid shifting left into sign
bit of a signed integer.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 72c1d3af6e9c2745edfeaa71918a68bcee4b79db
      
https://github.com/qemu/qemu/commit/72c1d3af6e9c2745edfeaa71918a68bcee4b79db
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-10 (Mon, 10 Mar 2014)

  Changed paths:
    M include/exec/cpu-defs.h
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Implement WFE as a yield operation

Implement WFE to yield our timeslice to the next CPU.
This avoids slowdowns in multicore configurations caused
by one core busy-waiting on a spinlock which can't possibly
be unlocked until the other core has an opportunity to run.
This speeds up my test case A15 dual-core boot by a factor
of three (though it is still four or five times slower than
a single-core boot).

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Rob Herring <address@hidden>


  Commit: 0ca540dbaea142ec5c3e7a1d12db7139b8317f37
      
https://github.com/qemu/qemu/commit/0ca540dbaea142ec5c3e7a1d12db7139b8317f37
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-11 (Tue, 11 Mar 2014)

  Changed paths:
    M disas/libvixl/a64/disasm-a64.cc
    M hw/arm/musicpal.c
    M hw/arm/omap1.c
    M hw/arm/pxa2xx.c
    M hw/arm/pxa2xx_gpio.c
    M hw/arm/pxa2xx_pic.c
    M hw/ssi/xilinx_spips.c
    M include/exec/cpu-defs.h
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140310' 
into staging

target-arm queue:
 * implement WFE as yield (improves performance with emulated SMP)
 * fixes to avoid undefined behaviour shifting left into sign bit
 * libvixl format string fixes for 32 bit hosts
 * fix build error when intptr_t and tcg_target_long are different
   sizes (eg x32)
 * implement PMCCNTR register
 * fix incorrect setting of E bit in CPSR (broke booting under
   KVM on ARM)

# gpg: Signature made Mon 10 Mar 2014 15:05:25 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140310:
  target-arm: Implement WFE as a yield operation
  hw/arm/musicpal: Avoid shifting left into sign bit
  hw/ssi/xilinx_spips.c: Avoid shifting left into sign bit
  hw/arm/omap1.c: Avoid shifting left into sign bit
  pxa2xx: Don't shift into sign bit
  libvixl: Fix format strings for several int64_t values
  target-arm: Fix intptr_t vs tcg_target_long
  target-arm: Implements the ARM PMCCNTR register
  target-arm: Fix incorrect setting of E bit in CPSR

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/ed9b103d3e31...0ca540dbaea1

reply via email to

[Prev in Thread] Current Thread [Next in Thread]