qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] a5100e: target-ppc: fix compile error when PP


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] a5100e: target-ppc: fix compile error when PPC_DUMP_CPU is...
Date: Fri, 07 Mar 2014 09:30:13 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a5100e752b4ed1027b6db27d3fbcb0e3c62b3f94
      
https://github.com/qemu/qemu/commit/a5100e752b4ed1027b6db27d3fbcb0e3c62b3f94
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: fix compile error when PPC_DUMP_CPU is enabled

Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became
a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU
breaks compile.

This fixes compiler errors.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6475c9f05ca89d76635108dca64a11759838e03c
      
https://github.com/qemu/qemu/commit/6475c9f05ca89d76635108dca64a11759838e03c
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: fix LPCR SPR number

PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of
316.

This fixes the definition of LPCR SPR.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 81d2fb4dfdf34889676410ff61753b351e3d67fb
      
https://github.com/qemu/qemu/commit/81d2fb4dfdf34889676410ff61753b351e3d67fb
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/STATUS
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: remove powerpc 970gx

The 970GX definition was added in 2007 and it made sense then but this
version has never been released to the markets and it does not exist in
the real world so there is no point in emulating it.

This removes 970GX.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0bfe9299dae5c92498a4f503e6d5786bdbc7c4d7
      
https://github.com/qemu/qemu/commit/0bfe9299dae5c92498a4f503e6d5786bdbc7c4d7
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers

Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:
                  priviledged
#   spr5-9 spr0-4 name mtspr mfspr len cat
136 00100  01000  CTRL   -    no    32  S
152 00100  11000  CTRL  yes    -    32  S

This swaps the numbers. No effect from this change is expected though.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 401949176c00029692378d83b0dcc638ccbd7b6e
      
https://github.com/qemu/qemu/commit/401949176c00029692378d83b0dcc638ccbd7b6e
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8

PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so
remove it from POWER7/8 class as it is "S" (server) category.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 88ccd23a0c99155ff1eb5162d3685fde9c679b3d
      
https://github.com/qemu/qemu/commit/88ccd23a0c99155ff1eb5162d3685fde9c679b3d
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: remove unsupported SPRs from 970 and P5+

SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5
bookIV nor PowerISA 2.04, the numbers assigned to them are not defined
either so remove them.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9c06a1f79f959fffd09bfb7efc3d76051a6cd2da
      
https://github.com/qemu/qemu/commit/9c06a1f79f959fffd09bfb7efc3d76051a6cd2da
  Author: Alexander Graf <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M include/hw/boards.h
    M include/hw/xen/xen.h
    M include/sysemu/kvm.h
    A include/sysemu/qemumachine.h
    M include/sysemu/qtest.h
    M kvm-stub.c

  Log Message:
  -----------
  KVM: Split QEMUMachine typedef into separate header

Older gcc versions (such as the one in SLES11) get confused when you declare
a typedef on the same struct twice.

To work around that limitation, let's extract the QEMUMachine typedef into a
separate header file that is guarded by preprocessor duplicate include checks.

This fixes the following type of compile errors for me:

  In file included from vl.c:125:
  include/hw/xen/xen.h:39: error: redefinition of typedef "QEMUMachine"
  include/sysemu/kvm.h:155: error: previous declaration of "QEMUMachine" was 
here

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 135a129a1cd047cc913e88c795eda859a0ebb81f
      
https://github.com/qemu/qemu/commit/135a129a1cd047cc913e88c795eda859a0ebb81f
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M include/hw/boards.h
    M include/hw/xen/xen.h
    M include/sysemu/kvm.h
    M include/sysemu/qtest.h
    M kvm-all.c
    M kvm-stub.c
    M qtest.c
    M vl.c
    M xen-all.c
    M xen-stub.c

  Log Message:
  -----------
  kvm: Add a new machine option kvm-type

Targets like ppc64 support different types of KVM, one which use
hypervisor mode and the other which doesn't. Add a new machine
option kvm-type that helps in selecting the respective ones
We also add a new QEMUMachine callback get_vm_type that helps
in mapping the string representation of kvm type specified.

Signed-off-by: Aneesh Kumar K.V <address@hidden>
[agraf: spelling fixes, use error_report(), use qemumachine.h]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ca480de66400c4fcaf59100b813e402f9edb08f7
      
https://github.com/qemu/qemu/commit/ca480de66400c4fcaf59100b813e402f9edb08f7
  Author: Anton Blanchard <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: dump DAR and DSISR

The DAR and DSISR can be very useful when debugging issues, so add
them to ppc_cpu_dump_state. We had another bug in this area: all
of the v2.06 MMU types were missing.

Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0dc083fe10c5cc848f36498b9157a336cbc8c7c1
      
https://github.com/qemu/qemu/commit/0dc083fe10c5cc848f36498b9157a336cbc8c7c1
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: fix Authority Mask Register init value

The existing default value (-1) of the AMR register forbids data access
to all 32 classes. Since the guest linux does not change this register,
we end up with the guest hanging right after switching from the real to
protected mode.

This sets the default AMR value to zero what enables data access for all
classes.

The only reason for not hitting this bug before is that
kvm_arch_put_registers() did not put any SPR to KVM due to missing
assignment of @one_reg_id in _spr_register() (which is going to be fixed
by a separate patch).

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 363248e8c92c6331253e2a768884c69183805050
      
https://github.com/qemu/qemu/commit/363248e8c92c6331253e2a768884c69183805050
  Author: Cédric Le Goater <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/mmu-hash64.c

  Log Message:
  -----------
  mmu-hash64: fix Virtual Page Class Key Protection

commit f80872e21c07edd06eb343eeeefc8af404b518a6 (mmu-hash64: Implement
Virtual Page Class Key Protection) added a new page protection
mechanism based on page keys and the AMR register to control access.

The AMR register allows or prohibits reads and/or writes on a page
depending on the control bits associated to the key. A store or a load
is only permitted if the associate bit is 0 (Power ISA), and not 1 as
the code is currently doing. This patch modifies ppc_hash64_amr_prot()
to correct the protection check.

This issue was unvailed by commit ccfb53ed6360cac0d5f6f7915ca9ae7eed866412
(target-ppc: fix Authority Mask Register init value) which changed the
initialisation value of the AMR register to 0.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7a7c05d77d60f6a23705da4005e96d379fd49ddb
      
https://github.com/qemu/qemu/commit/7a7c05d77d60f6a23705da4005e96d379fd49ddb
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  PPC: KVM: fix "set one register"

Due to missing @one_reg_id assignment in _spr_register(),
the kvm_get_one_reg/kvm_set_one_reg API has never really been working.

This reenables the API by assigning the @one_reg_id field in the SPR
descriptor.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6cd8712c5fd74a8ec0aae1b7cc34af026354f06a
      
https://github.com/qemu/qemu/commit/6cd8712c5fd74a8ec0aae1b7cc34af026354f06a
  Author: Greg Kurz <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  PPC: KVM: add support for LPCR

The LPCR special purpose register was introduced with the PowerPC 970MP family.

This patch initializes LPCR for the following families:
- 970 MP
- POWER5+
- POWER7
- POWER8

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 09aa9a526a86fd2e380e86157c55dfd180661c64
      
https://github.com/qemu/qemu/commit/09aa9a526a86fd2e380e86157c55dfd180661c64
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr-pci: enable adding PHB via -device

Recent changes introduced cannot_instantiate_with_device_add_yet
and removed capability of adding yet another PCI host bridge via
command line for SPAPR platform (POWERPC64 server).

This brings the capability back and puts SPAPR PHB into "bridge"
category.

This is not much use for emulated PHB but it is absolutely required
for VFIO as we put an IOMMU group onto a separate PHB on SPAPR.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3052f0d59426a1f8120ffbf66fd438973bfd2912
      
https://github.com/qemu/qemu/commit/3052f0d59426a1f8120ffbf66fd438973bfd2912
  Author: Nathan Whitehorn <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/scsi/spapr_vscsi.c

  Log Message:
  -----------
  spapr_vscsi: Fix REPORT_LUNS handling

Intercept REPORT_LUNS commands addressed either to SRP LUN 0 or the well-known
LUN for REPORT_LUNS commands. This is required to implement the SAM and SPC
specifications.

Since SRP implements only a single SCSI target port per connection, the SRP
target is required to report all available LUNs in response to a REPORT_LUNS
command addressed either to LUN 0 or the well-known LUN. Instead, QEMU was
forwarding such requests to the first QEMU SCSI target, with the result that
initiators that relied on this feature would only see LUNs on the first QEMU
SCSI target.

Behavior for REPORT_LUNS commands addressed to any other LUN is not specified
by the standard and so is left unchanged. This preserves behavior under Linux
and SLOF, which enumerate possible LUNs by hand and so address no commands
either to LUN 0 or the well-known REPORT_LUNS LUN.

Signed-off-by: Nathan Whitehorn <address@hidden>
Acked-by: Paolo Bonzini <address@hidden>
[agraf: define constant as ULL for 32bit hosts]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4e38181979ec4bc80c75f0c181f9df2d4e933c13
      
https://github.com/qemu/qemu/commit/4e38181979ec4bc80c75f0c181f9df2d4e933c13
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: disable unsupported modes for SPR_CTRL/SPR_UCTRL

The Figure 17 "SPR encodings" of the PowerISA 2.07 describes CTRL SPR as:
                  priviledged
#   spr5-9 spr0-4 name mtspr mfspr len cat
136 00100  01000  CTRL   -    no    32  S
152 00100  11000  CTRL  yes    -    32  S

According to this chart, the hypervisor's CTRL (#152) does not support
reading, the user-space's CTRL (UCTRL, #136) does not support writing.

This replaces unsupported operations with the default SPR_NOACCESS hook.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 59800ec8e52bcfa271fa61fb0aae19205ef1b7f1
      
https://github.com/qemu/qemu/commit/59800ec8e52bcfa271fa61fb0aae19205ef1b7f1
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Add set_fprf Argument to fload_invalid_op_excp()

The fload_invalid_op_excp() function sets assorted invalid
operation status bits.  However, it also implicitly modifies
the FPRF field of the PowerPC FPSCR.  Many VSX instructions
set invalid operation bits but do not alter FPRF.  Thus the
function is more generally useful if the setting of the FPRF
field is made conditional via a parameter.

All invocations of this routine in existing instructions are
modified to pass 1 and thus retain their current behavior.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3c3cbbdc84dbe594b4fa4df52eb8ed6f42d640d8
      
https://github.com/qemu/qemu/commit/3c3cbbdc84dbe594b4fa4df52eb8ed6f42d640d8
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: General Support for VSX Helpers

This patch adds general support that will be used by the VSX helper
routines:

  - a union describing the various VSR subfields.
  - access routines to get and set VSRs
  - VSX decoders
  - a general routine to generate a handler that invokes a VSX
    helper.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ee6e02c0aca020a1934a14c36cff258545dc29b5
      
https://github.com/qemu/qemu/commit/ee6e02c0aca020a1934a14c36cff258545dc29b5
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xadd/xsub Instructions

This patch adds the floating point addition and subtraction
instructions defined by V2.06 of the PowerPC ISA: xssubdp,
xvsubdp and xvsubsp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5e591d8812df5efa38518b6bf933d02c61fa1c10
      
https://github.com/qemu/qemu/commit/5e591d8812df5efa38518b6bf933d02c61fa1c10
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xmul Instructions

This patch adds the VSX floating point multiply instructions defined
by V2.06 of the PowerPC ISA: xsmuldp, xvmuldp, xvmulsp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4b98eeef50c1bb619dc32bddc9d54ed03c365c5f
      
https://github.com/qemu/qemu/commit/4b98eeef50c1bb619dc32bddc9d54ed03c365c5f
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xdiv Instructions

This patch adds the VSX floating point divide instructions defined
by V2.06 of the PowerPC ISA: xsdivdp, xvdivdp, xvdivsp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2009227fbe868979d6a0518ef34972462f140404
      
https://github.com/qemu/qemu/commit/2009227fbe868979d6a0518ef34972462f140404
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xre Instructions

This patch adds the VSX floating point reciprocal estimate instructions
defined by V2.06 of the PowerPC ISA: xsredp, xvredp, xvresp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d32404fe42ec67beee7d26aef8571e5e9c1e39b3
      
https://github.com/qemu/qemu/commit/d32404fe42ec67beee7d26aef8571e5e9c1e39b3
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xsqrt Instructions

This patch adds the VSX floating point square root instructions
defined by V2.06 of the PowerPC ISA: xssqrtdp, xvsqrtdp, xvsqrtsp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: d3f9df8fb83f72947a44bc773bec92105db731ff
      
https://github.com/qemu/qemu/commit/d3f9df8fb83f72947a44bc773bec92105db731ff
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xrsqrte Instructions

This patch adds the VSX floating point reciprocal square root
estimate instructions defined by V2.06 of the PowerPC ISA: xsrsqrtedp,
xvrsqrtedp, xvrsqrtesp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bc80838f86375c420d37c6c20e6a9098904932ce
      
https://github.com/qemu/qemu/commit/bc80838f86375c420d37c6c20e6a9098904932ce
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xtdiv Instructions

This patch adds the VSX floating point test for software divide
instructions defined by V2.06 of the PowerPC ISA: xstdivdp, xvtdivdp,
and xvtdivsp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5cb151acb18ab247f1e7c703e242b430551e3129
      
https://github.com/qemu/qemu/commit/5cb151acb18ab247f1e7c703e242b430551e3129
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 xtsqrt Instructions

This patch adds the VSX floating point test for software square
root instructions defined by V2.06 of the PowerPC ISA: xstsqrtdp,
xvtsqrtdp, xvtsqrtsp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 595c6eefb79a77a650dd7a49e812920ed53b0e9c
      
https://github.com/qemu/qemu/commit/595c6eefb79a77a650dd7a49e812920ed53b0e9c
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 Multiply Add Instructions

This patch adds the VSX floating point multiply/add instructions
defined by V2.06 of the PowerPC ISA:

  - xsmaddadp,  xvmaddadp,  xvmaddasp
  - xsmaddmdp,  xvmaddmdp,  xvmaddmsp
  - xsmsubadp,  xvmsubadp,  xvmsubasp
  - xsmsubmdp,  xvmsubmdp,  xvmsubmsp
  - xsnmaddadp, xvnmaddadp, xvnmaddasp
  - xsnmaddmdp, xvnmaddmdp, xvnmaddmsp
  - xsnmsubadp, xvnmsubadp, xvnmsubasp
  - xsnmsubmdp, xvnmsubmdp, xvnmsubmsp

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4f17e9c738321151e6b7aa4d2c25c3f1e2443cca
      
https://github.com/qemu/qemu/commit/4f17e9c738321151e6b7aa4d2c25c3f1e2443cca
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX xscmp*dp Instructions

This patch adds the VSX scalar floating point compare ordered
and unordered instructions.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 959e9c9d1e5507a6c68d0b875d71ef967d3cfd6c
      
https://github.com/qemu/qemu/commit/959e9c9d1e5507a6c68d0b875d71ef967d3cfd6c
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX xmax/xmin Instructions

This patch adds the VSX floating point maximum and minimum
instructions:

  - xsmaxdp, xvmaxdp, xvmaxsp
  - xsmindp, xvmindp, xvminsp

Because of the Power ISA definitions of maximum and minimum
on various boundary cases, the standard softfloat comparison
routines (e.g. float64_lt) do not work as well as one might
think.  Therefore specific routines for comparing 64 and 32
bit floating point numbers are implemented in the PowerPC
helper code.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 354a6decf1508f15fb1b4b419efcd05d209bece4
      
https://github.com/qemu/qemu/commit/354a6decf1508f15fb1b4b419efcd05d209bece4
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX Vector Compare Instructions

This patch adds the VSX floating point compare vector instructions:

  - xvcmpeqdp[.], xvcmpgedp[.], xvcmpgtdp[.]
  - xvcmpeqsp[.], xvcmpgesp[.], xvcmpgtsp[.]

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ed8ac5686a8e1aba7ddc5d8ca3a56a7496a2a536
      
https://github.com/qemu/qemu/commit/ed8ac5686a8e1aba7ddc5d8ca3a56a7496a2a536
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX Floating Point to Floating Point Conversion Instructions

This patch adds the VSX instructions that convert between floating
point formats: xscvdpsp, xscvspdp, xvcvdpsp, xvcvspdp.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5177d2ca938496f060448f71f9edd9145231d9af
      
https://github.com/qemu/qemu/commit/5177d2ca938496f060448f71f9edd9145231d9af
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX ISA2.06 Integer Conversion Instructions

This patch adds the VSX Integer Conversion instructions defined by
V2.06 of the PowerPC ISA:

  - xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws
  - xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws
  - xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws
  - xscvsxddp, xscvuxddp
  - xvcvsxddp, xscvsxwdp, xvcvuxddp, xvcvuxwdp
  - xvcvsxdsp, xscvsxwsp, xvcvuxdsp, xvcvuxwsp

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 88e33d08c9c2fc0aabc9b832719324bd2d454db9
      
https://github.com/qemu/qemu/commit/88e33d08c9c2fc0aabc9b832719324bd2d454db9
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add VSX Rounding Instructions

This patch adds the VSX Round to Floating Point Integer instructions:

  - xsrdpi, xsrdpic, xsrdpim, xsrdpip, xsrdpiz
  - xvrdpi, xvrdpic, xvrdpim, xvrdpip, xvrdpiz
  - xvrspi, xvrspic, xvrspim, xvrspip, xvrspiz

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: dbcc48fa8fc534c240129fcdece9c3fb0434e82c
      
https://github.com/qemu/qemu/commit/dbcc48fa8fc534c240129fcdece9c3fb0434e82c
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add VSX 2.07 Flag

This patch adds a flag to identify those VSX instructions that are
new to Power ISA V2.07.  The flag is added to the Power 8 processor
initialization so that the P8 models understand how to decode and
emulate instructions in this category.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e072fe796ee2b5f43e0dba259d0706e1b296138a
      
https://github.com/qemu/qemu/commit/e072fe796ee2b5f43e0dba259d0706e1b296138a
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Refactor lxsdx

This patch refactors the lxsdx generator. Resuable code is isolated
into a macro.  The macro will be used in subsequent patches in this
series to implement other scalar load instructions.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: cac7f0ba4a5a47050a249ef085bc846630224d0d
      
https://github.com/qemu/qemu/commit/cac7f0ba4a5a47050a249ef085bc846630224d0d
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx

This patch adds the scalar load instructions introduced in ISA
V2.07:

  - Load VSX Scalar as Integer Word Algebraic Indexd (lxsiwax)
  - Load VSX Scalar as Integer Word and Zero Indexed (lxsiwzx)
  - Load VSX Scalar Single-Precision Indexed (lxsspx)

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f026da78308ea468d26d78792a6655bb34431f18
      
https://github.com/qemu/qemu/commit/f026da78308ea468d26d78792a6655bb34431f18
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Refactor stxsdx

This patch refactors the stxsdx instruction.  Reusable code is
extracted into a macro which will be used in subsequent patches
in this series.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e16a626b8280cfcf3de385c59ddd1fde2840c2c3
      
https://github.com/qemu/qemu/commit/e16a626b8280cfcf3de385c59ddd1fde2840c2c3
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add stxsiwx and stxsspx

This patch adds two store scalar instructions:

  - Store VSX Scalar as Integer Word Indexed (stxsiwx)
  - Store VSX Scalar Single-Precision Indexed (stxsspx)

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3fd0aadfc19ba146ed6ced27b4e6ff6afc08473a
      
https://github.com/qemu/qemu/commit/3fd0aadfc19ba146ed6ced27b4e6ff6afc08473a
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xsaddsp and xssubsp

This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.

The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ab9408a2d11670d15b2692ca60646d8da8158d6f
      
https://github.com/qemu/qemu/commit/ab9408a2d11670d15b2692ca60646d8da8158d6f
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xsmulsp

This patch adds the VSX Scalar Multiply Single-Precision (xsmulsp)
instruction.

The existing VSX_MUL macro is modified to support rounding of the
intermediate result to single precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b24d0b472b0d471e93ccc7fc7d4fd6ed30e7e434
      
https://github.com/qemu/qemu/commit/b24d0b472b0d471e93ccc7fc7d4fd6ed30e7e434
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xsdivsp

This patch adds the VSX Scalar Divide Single Precision (xsdivsp)
instruction.

The existing VSX_DIV macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2c0c52ae620cf121a8b9084c7c1168d867564ee8
      
https://github.com/qemu/qemu/commit/2c0c52ae620cf121a8b9084c7c1168d867564ee8
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xsresp

This patch adds the VSX Scalar Reciprocal Estimate Single Precision
(xsresp) instruction.

The existing VSX_RE macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: cea4e57473efc2fad1d241e87984eba4e5d9690c
      
https://github.com/qemu/qemu/commit/cea4e57473efc2fad1d241e87984eba4e5d9690c
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xssqrtsp

This patch adds the VSX Scalar Square Root Single Precision (xssqrtsp)
instruction.

The existing VSX_SQRT() macro is modified to support rounding of the
intermediate double-precision result to single-precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 968e76bcab9a3c40f37c9a52822b6daa90ae7cd8
      
https://github.com/qemu/qemu/commit/968e76bcab9a3c40f37c9a52822b6daa90ae7cd8
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: add xsrsqrtesp

This patch adds the VSX Scalar Reciprocal Square Root Estimate
Single Precision (xsrsqrtesp) instruction.

The existing VSX_RSQRTE() macro is modified to support rounding
of the intermediate double-precision result to single precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f53f81e08bd0192121c4e0c3f1fdc53832631b4b
      
https://github.com/qemu/qemu/commit/f53f81e08bd0192121c4e0c3f1fdc53832631b4b
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds

This patch adds the Single Precision VSX Scalar Fused Multiply-Add
instructions: xsmaddasp, xsmaddmsp, xssubasp, xssubmsp, xsnmaddasp,
xsnmaddmsp, xsnmsubasp, xsnmsubmsp.

The existing VSX_MADD() macro is modified to support rounding of the
intermediate double precision result to single precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 74698350ca1bc95eda751f8c5a93268f20f7214e
      
https://github.com/qemu/qemu/commit/74698350ca1bc95eda751f8c5a93268f20f7214e
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp

This patch adds the VSX Scalar Convert Unsigned Integer Doubleword
to Floating Point Format and Round to Single Precision (xscvuxdsp)
and VSX Scalar Convert Signed Integer Douglbeword to Floating Point
Format and Round to Single Precision (xscvsxdsp) instructions.

The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP)
is modified to support the rounding of the intermediate floating point
result to single precision.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 67a33f37277e29355239c7cb80af14f914f201f3
      
https://github.com/qemu/qemu/commit/67a33f37277e29355239c7cb80af14f914f201f3
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc

This patchs adds the VSX Logical instructions that are new with
ISA V2.07:

  - VSX Logical Equivalence (xxleqv)
  - VSX Logical NAND (xxlnand)
  - VSX Logical ORC (xxlorc)

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f5c0f7f981333da59cc35c3210d05ec1775c97c1
      
https://github.com/qemu/qemu/commit/f5c0f7f981333da59cc35c3210d05ec1775c97c1
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Move To/From VSR Instructions

This patch adds the Move To VSR instructions (mfvsrd, mfvsrwz)
and Move From VSR instructions (mtvsrd, mtvsrwa, mtvsrwz).  These
instructions are unusual in that they are considered a floating
point instruction if the indexed VSR is in the first half of the
array (0-31) but they are considered vector instructions if the
indexed VSR is in the second half of the array (32-63).

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 097ec5d850df7dd1da87220726ce87a6ab3566c4
      
https://github.com/qemu/qemu/commit/097ec5d850df7dd1da87220726ce87a6ab3566c4
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Floating Merge Word Instructions

This patch adds the Floating Merge Even Word (fmrgew) and Floating
Merge Odd Word (fmrgow) instructions.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3d1140bf3e73e4fd244914bdf2867fe634759c71
      
https://github.com/qemu/qemu/commit/3d1140bf3e73e4fd244914bdf2867fe634759c71
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Scalar Round to Single Precision

This patch adds the VSX Scalar Round to Single Precision (xsrsp)
instruction.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7ee19fb9d682689d36c849576c808cf92e3bae40
      
https://github.com/qemu/qemu/commit/7ee19fb9d682689d36c849576c808cf92e3bae40
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Scalar Non-Signalling Conversions

This patch adds the non-signalling scalar conversion instructions:

  - VSX Scalar Convert Single Precision to Double Precision
    Non-Signalling (xscvspdpn)
  - VSX Scalar Convert Double Precision to Single Precision
    Non-Signalling (xscvdpspn)

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 86ba37edcb6556b124840f04d180a34ffcc71086
      
https://github.com/qemu/qemu/commit/86ba37edcb6556b124840f04d180a34ffcc71086
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add ISA2.06 bpermd Instruction

This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a824bc191a90d86980a9ed090cb1d1219faaf8e7
      
https://github.com/qemu/qemu/commit/a824bc191a90d86980a9ed090cb1d1219faaf8e7
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Flag for ISA2.06 Divide Extended Instructions

This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B.  The flag is added to the
Power7 and Power8 models.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 98d1eb2748e84f9e3118d1bd2495f0cc917ac18d
      
https://github.com/qemu/qemu/commit/98d1eb2748e84f9e3118d1bd2495f0cc917ac18d
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M include/qemu/host-utils.h
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c
    M util/host-utils.c

  Log Message:
  -----------
  target-ppc: Add ISA2.06 divdeu[o] Instructions

This patch adds the Divide Doubleword Extended Unsigned
instructions.  This instruction requires dividing a 128-bit
value by a 64 bit value.  Since 128 bit integer division is
not supported in TCG, a helper is used.  An architecture
independent 128-bit division routine is added to host-utils.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
[agraf: use ||]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e44259b6d4f4de69a868510a198b2696f24118a1
      
https://github.com/qemu/qemu/commit/e44259b6d4f4de69a868510a198b2696f24118a1
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M include/qemu/host-utils.h
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c
    M util/host-utils.c

  Log Message:
  -----------
  target-ppc: Add ISA2.06 divde[o] Instructions

This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6a4fda3358ca5a21e17d553074f74d512745c4f6
      
https://github.com/qemu/qemu/commit/6a4fda3358ca5a21e17d553074f74d512745c4f6
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA 2.06 divweu[o] Instructions

This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a98eb9e99df4c11966fcd56cbcb6f06e6f413a89
      
https://github.com/qemu/qemu/commit/a98eb9e99df4c11966fcd56cbcb6f06e6f413a89
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA 2.06 divwe[o] Instructions

This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1fa6c533047b4447cef693a1f54babc6a69fe19d
      
https://github.com/qemu/qemu/commit/1fa6c533047b4447cef693a1f54babc6a69fe19d
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Flag for ISA2.06 Atomic Instructions

This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5c77a786e21e9dc12efc0f0590221e67dd5143da
      
https://github.com/qemu/qemu/commit/5c77a786e21e9dc12efc0f0590221e67dd5143da
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA2.06 lbarx, lharx Instructions

This patch adds the byte and halfword variants of the Load and
Reserve instructions.   Since there is much commonality among
all forms of Load and Reserve, a macro is provided and the existing
implementations of lwarx and ldarx are refactoried to use this
macro.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 587c51f74bcf2f9aa03b7d8e1cff229f74d02860
      
https://github.com/qemu/qemu/commit/587c51f74bcf2f9aa03b7d8e1cff229f74d02860
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions

This patch adds the byte and halfword variants of the Store Conditional
instructions.   A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1b0bd0029f16649a7f3d8ba021191bc6ca3a471f
      
https://github.com/qemu/qemu/commit/1b0bd0029f16649a7f3d8ba021191bc6ca3a471f
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Flag for ISA V2.06 Floating Point Conversion

This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: fab7fe426fa5325f93c931ffbe25f4e024b1ced4
      
https://github.com/qemu/qemu/commit/fab7fe426fa5325f93c931ffbe25f4e024b1ced4
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA2.06 Float to Integer Instructions

This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:

  - Floating Convert to Integer Word Unsigned (fctiwu)
  - Floating Convert to Integer Word Unsigned with Round Toward
    Zero (fctiwuz)
  - Floating Convert to Integer Doubleword Unsigned (fctidu)
  - Floating Convert to Integer Doubleword Unsigned with Round
    Toward Zero (fctiduz)

A common macro is developed to eliminate repetitious code.  Existing 
instructions
are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz).

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 28288b48a83e903198ee22d8558c43b021e39a17
      
https://github.com/qemu/qemu/commit/28288b48a83e903198ee22d8558c43b021e39a17
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA 2.06 fcfid[u][s] Instructions

This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B.  A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c73860803f8f8f56ee01b6e796507bfb4ea073ec
      
https://github.com/qemu/qemu/commit/c73860803f8f8f56ee01b6e796507bfb4ea073ec
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Fix and enable fri[mnpz]

The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware.  However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.

Also, the existing helper is modified to correctly handle some of
the boundary cases (NaNs and the inexact flag).

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 29a0e4e9a1adfaf8864cfb7a79e5bb0f28aac282
      
https://github.com/qemu/qemu/commit/29a0e4e9a1adfaf8864cfb7a79e5bb0f28aac282
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Flag for Power ISA V2.06 Floating Point Test Instructions

This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: da29cb7bc7b62c14a69a104f91867edf9ce88543
      
https://github.com/qemu/qemu/commit/da29cb7bc7b62c14a69a104f91867edf9ce88543
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA 2.06 ftdiv Instruction

This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6d41d146c92e99e21ef267be4c4b9893940e0838
      
https://github.com/qemu/qemu/commit/6d41d146c92e99e21ef267be4c4b9893940e0838
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA 2.06 ftsqrt

This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ce8ca30b398fb74e522be1a9ea87aa7868f27428
      
https://github.com/qemu/qemu/commit/ce8ca30b398fb74e522be1a9ea87aa7868f27428
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Enable frsqrtes on Power7 and Power8

The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors.  However, this
instruction is handled as illegal in the current QEMU emulation
machines.  This patch enables the existing implemention of frsqrtes
in the P7 and P8 machines.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 66c3e32841f185243efa59381ab7721b24deca35
      
https://github.com/qemu/qemu/commit/66c3e32841f185243efa59381ab7721b24deca35
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add ISA2.06 lfiwzx Instruction

This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 69b31b907b1114b4ee24faa00582fd5ecaaccf5c
      
https://github.com/qemu/qemu/commit/69b31b907b1114b4ee24faa00582fd5ecaaccf5c
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  PPC: KVM: store SLB slot number

When ppc_store_slb() is called from kvm_arch_get_registers(), it stores
a SLB in CPUPPCState::slb[slot]. However it drops the slot number from
ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not
have correct "index" field anymore. This broke migration with LPCR_AIR
enabled as now the guest is handling interrupts in virtual mode and unable
to reconstruct correct SLBs anymore.

This adds "index" field for valid SLBs when putting them to KVM.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Aneesh Kumar K.V <address@hidden>
Cc: address@hidden
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0658aa9cbacdfd40fffd23bfd6608870d12602c1
      
https://github.com/qemu/qemu/commit/0658aa9cbacdfd40fffd23bfd6608870d12602c1
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/virtex_ml507.c

  Log Message:
  -----------
  virtex_ml507: Add support for loading initrd images

Signed-off-by: Edgar E. Iglesias <address@hidden>
[agraf: fix up stray quotes and newlines in strings]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b36f100e17c8e2e737b48d78c9049b96752e4adf
      
https://github.com/qemu/qemu/commit/b36f100e17c8e2e737b48d78c9049b96752e4adf
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/kvm.c
    M trace-events

  Log Message:
  -----------
  PPC: KVM: suppress warnings about not supported SPRs

PR KVM lacks support of many SPRs in set/get one register API but it does
really break PR KVM. So convert them to switchable traces for now.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: eb1e7c3e514665bb948357ef39845efd9af29de1
      
https://github.com/qemu/qemu/commit/eb1e7c3e514665bb948357ef39845efd9af29de1
  Author: Fabien Chouteau <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M hw/net/Makefile.objs
    A hw/net/fsl_etsec/etsec.c
    A hw/net/fsl_etsec/etsec.h
    A hw/net/fsl_etsec/miim.c
    A hw/net/fsl_etsec/registers.c
    A hw/net/fsl_etsec/registers.h
    A hw/net/fsl_etsec/rings.c

  Log Message:
  -----------
  Add Enhanced Three-Speed Ethernet Controller (eTSEC)

This implementation doesn't include ring priority, TCP/IP Off-Load, QoS.

Signed-off-by: Fabien Chouteau <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 133e70ee8831992e309f74c20084bc50e3bcf8e0
      
https://github.com/qemu/qemu/commit/133e70ee8831992e309f74c20084bc50e3bcf8e0
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: support only ELF kernel images

Currently everybody uses ELF kernel images with "-kernel" option on
pseries machine but QEMU still tries to boot from an image even it
fails to recognize it is ELF. This produces undefined behaviour if
the user tries a kernel image compiled for another architecture.

This removes support of raw kernel images.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6a2331d12ee7ca9fbcf2a3c22109513ca561a51e
      
https://github.com/qemu/qemu/commit/6a2331d12ee7ca9fbcf2a3c22109513ca561a51e
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/moxie/moxiesim.c

  Log Message:
  -----------
  moxie: fix load_elf() usage

At the moment in the case of error, load_elf() returns -1 so load_kernel()
will not signal error at all.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 18674b26788a9e47f1157170234e32ece2044367
      
https://github.com/qemu/qemu/commit/18674b26788a9e47f1157170234e32ece2044367
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/core/loader.c
    M hw/s390x/ipl.c
    M include/hw/elf_ops.h
    M include/hw/loader.h

  Log Message:
  -----------
  elf-loader: add more return codes

The existing load_elf() just returns -1 if it fails to load ELF. However
it could be smarter than this and tell more about the failure such as
wrong endianness or incompatible platform.

This adds additional return codes for wrong architecture, wrong
endianness and if the image is not ELF at all.

This adds a load_elf_strerror() helper to convert return codes into
string messages.

This fixes handling of what load_elf() returns for s390x, other
callers just check the return value for <0 and this remains unchanged.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3b66da82cebf3ddd1c2e06233c647369f617a6bc
      
https://github.com/qemu/qemu/commit/3b66da82cebf3ddd1c2e06233c647369f617a6bc
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: print more detailed error message on failed load_elf()

This makes use of new error codes which load_elf() can return and
prints more informative error message.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5736245c80bb277f3de7f37d9482c906743612ad
      
https://github.com/qemu/qemu/commit/5736245c80bb277f3de7f37d9482c906743612ad
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  target-ppc: Update external_htab even when HTAB is managed by kernel

We will use this in later patches to make sure we use the right load
functions when copying hpte entries.

Signed-off-by: Aneesh Kumar K.V <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 61de36761b565a4138d8ad7ec75489ab28fe84b6
      
https://github.com/qemu/qemu/commit/61de36761b565a4138d8ad7ec75489ab28fe84b6
  Author: Alexander Graf <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/core/qdev.c
    M hw/i386/pc_piix.c
    M include/hw/qdev-core.h

  Log Message:
  -----------
  qdev: Keep global allocation counter per bus

When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:

  dev: macio-ide, id ""
    bus: ide.0
      type IDE
  dev: macio-ide, id ""
    bus: ide.0
      type IDE

If we now spawn a device that connects to a ide.0 the last created
bus gets the device, with the first created bus inaccessible to the
command line.

After some discussion on IRC we concluded that the best quick fix way
forward for this is to make automated bus-class type based allocation
count a global counter. That's what this patch implements. With this
we instead get

  dev: macio-ide, id ""
    bus: ide.1
      type IDE
  dev: macio-ide, id ""
    bus: ide.0
      type IDE

on the example mentioned above.

This also means that if you did -device ...,bus=ide.0 you got a device
on the first bus (the last created one) before this patch and get that
device on the second one (the first created one) now.  Breaks
migration unless you change bus=ide.0 to bus=ide.1 on the destination.

This is intended and makes the bus enumeration work as expected.

As per review request follows a list of otherwise affected boards and
the reasoning for the conclusion that they are ok:

   target      machine         bus id              times
   ------      -------         ------              -----

   aarch64     n800            i2c-bus.0           2
   aarch64     n810            i2c-bus.0           2
   arm         n800            i2c-bus.0           2
   arm         n810            i2c-bus.0           2

-> Devices are only created explicitly on one of the two buses, using
   s->mpu->i2c[0], so no change to the guest.

   aarch64     vexpress-a15    virtio-mmio-bus.0   4
   aarch64     vexpress-a9     virtio-mmio-bus.0   4
   aarch64     virt            virtio-mmio-bus.0   32
   arm         vexpress-a15    virtio-mmio-bus.0   4
   arm         vexpress-a9     virtio-mmio-bus.0   4
   arm         virt            virtio-mmio-bus.0   32

-> Makes -device bus= work for all virtio-mmio buses.  Breaks
   migration.  Workaround for migration from old to new: specify
   virtio-mmio-bus.4 or .32 respectively rather than .0 on the
   destination.

   aarch64     xilinx-zynq-a9  usb-bus.0           2
   arm         xilinx-zynq-a9  usb-bus.0           2
   mips64el    fulong2e        usb-bus.0           2

-> Normal USB operation not affected. Migration driver needs command
   line to use the other bus.

   i386        isapc           ide.0               2
   x86_64      isapc           ide.0               2
   mips        mips            ide.0               2
   mips64      mips            ide.0               2
   mips64el    mips            ide.0               2
   mipsel      mips            ide.0               2
   ppc         g3beige         ide.0               2
   ppc         mac99           ide.0               2
   ppc         prep            ide.0               2
   ppc64       g3beige         ide.0               2
   ppc64       mac99           ide.0               2
   ppc64       prep            ide.0               2

-> Makes -device bus= work for all IDE buses.  Breaks migration.
   Workaround for migration from old to new: specify ide.1 rather than
   ide.0 on the destination.

Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Andreas Faerber <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3f34cf910cbc4e77d25a300d8c290ae50bdcc2ed
      
https://github.com/qemu/qemu/commit/3f34cf910cbc4e77d25a300d8c290ae50bdcc2ed
  Author: Cédric Le Goater <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: add extended opcodes for dcbt/dcbtst

The latest glibc provides a memrchr routine using an extended opcode
of the 'dcbt' instruction :

00000000000a7cc0 <memrchr>:
   a7cc0:       11 00 4c 3c     addis   r2,r12,17
   a7cc4:       b8 f8 42 38     addi    r2,r2,-1864
   a7cc8:       14 2a e3 7c     add     r7,r3,r5
   a7ccc:       d0 00 07 7c     neg     r0,r7
   a7cd0:       ff ff e7 38     addi    r7,r7,-1
   a7cd4:       78 1b 6a 7c     mr      r10,r3
   a7cd8:       24 06 e6 78     rldicr  r6,r7,0,56
   a7cdc:       60 00 20 39     li      r9,96
   a7ce0:       2c 32 09 7e     dcbtt   r9,r6
   ....

which breaks grep, and other commands, in TCG mode :

   invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0

This patch adds the extended opcodes for dcbt/dcbtst as no-ops just
like the 'dcbt' instruction.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f5bc1bfa35af5288fe43f459696e712474dafc66
      
https://github.com/qemu/qemu/commit/f5bc1bfa35af5288fe43f459696e712474dafc66
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Fix xxpermdi When T==A or T==B

The existing implementation of xxpermdi is defective if the target
VSR is also a source VSR.  This patch fixes the defect in this case
but also preserves the simpler, two TCG operation implementation
when the target is not once of the two sources.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 94840e0700a3cbd0b0d99ae9ddecf47b4bbcc5d7
      
https://github.com/qemu/qemu/commit/94840e0700a3cbd0b0d99ae9ddecf47b4bbcc5d7
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Flag for bctar

This patch adds a flag for the bctar instruction.  This instruction
is being introduced via Power ISA 2.07.

Also, the flag is added to the Power8 machine model since the P8
processor supports this instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 60511041d6b846c9b6804a2c552ceda27d4e1f06
      
https://github.com/qemu/qemu/commit/60511041d6b846c9b6804a2c552ceda27d4e1f06
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Target Address SPR (TAR) to Power8

This patch adds support for the Target Address Register (TAR) to the Power8
model.

Because supported SPRs are typically identified in an init_proc_*()
function and because the Power8 model is currently just using the
init_proc_POWER7() function, a new init_proc_POWER8() function
is added and plugged into the P8 model.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 52a4984d97a942f35debb1887cb53d7f09bf1e26
      
https://github.com/qemu/qemu/commit/52a4984d97a942f35debb1887cb53d7f09bf1e26
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add bctar Instruction

This patch adds the Branch Conditional to Address Register (bctar)
instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 38a853375e63ea7315e138d7016ed387d744e43d
      
https://github.com/qemu/qemu/commit/38a853375e63ea7315e138d7016ed387d744e43d
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions

This patch adds a flag to identify the load/store quadword instructions
that are introduced with Power ISA 2.07.

The flag is added to the Power8 model since P8 supports these
instructions.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 71a8c019c445377f0dd04881cbd7c7dfb6ff3e5c
      
https://github.com/qemu/qemu/commit/71a8c019c445377f0dd04881cbd7c7dfb6ff3e5c
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add is_user_mode Utility Routine

This patch adds a boolean function is_user_mode that can be re-used
in translation code that is sensitive to the MSR[PR] (user-mode)
state.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e0498daab50d42f3948fc5607683c971fe9416fd
      
https://github.com/qemu/qemu/commit/e0498daab50d42f3948fc5607683c971fe9416fd
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Load Quadword

This patch adds the Book I (user space) Load Quadword (lq) instruction.
This instruction was introduced into Book I in Power ISA V2.07.  Previous
versions of the architecture supported this as a privileged instruction.
Previous versions of the architecture also did not support Little Endian
mode.

Note that this patch also adds the PPC_64BX flag to the Power8 model,
which enables the lq instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 84cab1e2f5be3ea6eaa65c9fc0422fb992946ce0
      
https://github.com/qemu/qemu/commit/84cab1e2f5be3ea6eaa65c9fc0422fb992946ce0
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Store Quadword

This patch adds support for the Store Quadword instruction in user mode.  Prior
to Power ISA 2.07, stq was legal only in privileged mode.  Support for Little
Endian mode is also new in ISA 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9c294d5ab3eac0e600fa510becfa677d87b088bf
      
https://github.com/qemu/qemu/commit/9c294d5ab3eac0e600fa510becfa677d87b088bf
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add Load Quadword and Reserve

This patch adds the Load Quadword and Reserve (lqarx) instruction,
which is new in Power ISA 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 27b95bfe624af1ddfaf63c07f3f0a63049b8c9fc
      
https://github.com/qemu/qemu/commit/27b95bfe624af1ddfaf63c07f3f0a63049b8c9fc
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M linux-user/main.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Add Store Quadword Conditional

This patch adds the Store Quadword Conditionl (stqcx.) instruction
which is introduced in Power ISA 2.07.

Signed-off-by: Tom Musta <address@hidden>
[agraf: fix compile error when !TARGET_PPC64]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 32ea54ab5fe18954e05f33a5825ba088d6cd4163
      
https://github.com/qemu/qemu/commit/32ea54ab5fe18954e05f33a5825ba088d6cd4163
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add Instruction Flag

This patch adds a flag that will be used to tag the Altivec instructions
introduced in Power ISA Version 2.07.

The flag is added to Power8 model since P8 supports these instructions.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bb5275338daf1b64bf9677e0361057cfa6ff6a7d
      
https://github.com/qemu/qemu/commit/bb5275338daf1b64bf9677e0361057cfa6ff6a7d
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/cpu.h

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Update AVR Structure

This patch updates the ppc_avr_t data structure to include elements for
signed 64-bit integers and (conditionally) unsigned 128 bit integers.
These elements will be in instructions models later on in this patch series.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9b47bb490c1b272c16b8f5e216b74456a3e17322
      
https://github.com/qemu/qemu/commit/9b47bb490c1b272c16b8f5e216b74456a3e17322
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add GEN_VXFORM3

This patch adds generator macro for Altivec instructions that have 3
source AVR operands.  The macro is similar to the 2 operand form.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5dffff5a4746075a4609366440c2c67983eec106
      
https://github.com/qemu/qemu/commit/5dffff5a4746075a4609366440c2c67983eec106
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions

Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode bit.  However, QEMU for PowerPC uses
bits 0-5 and 21-30 for opcodes and not bit 31.

This patch introduces macros that will handle this situation by injecting
an auxiliary handler which decodes bit 31 in invokes one of two standard
handlers.  Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 50f5fc0cf24fbc12434a5ad6e3784341f92e23bd
      
https://github.com/qemu/qemu/commit/50f5fc0cf24fbc12434a5ad6e3784341f92e23bd
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions

This patch adds a macro to insert an entry into the opcode table for Altivec
Power ISA Version 2.07 instructions.  The macro is similar to the GEN_VXFORM 
macro
except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than
PPC_ALTIVEC.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a737d3ebc8ece5728c2d98b725652b7a0056d593
      
https://github.com/qemu/qemu/commit/a737d3ebc8ece5728c2d98b725652b7a0056d593
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions

Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31
(aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc
bit.  QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes.

This patch introduces a generator macro that injects an auxiliary handler
which decodes both bits 21 and 31 and invokes one of four standard
handlers.  Since the instructions are not, in general, from the same version
of the ISA, two sets of PPC_*/PPC2_* flags are supported.

This patch also introduces a macro to insert two entries into the opcode
table -- one for bit 21 equal to 0 and one for bit 21 equal to 1.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 111c5f54a1fda35ff3a35d5cb62cd5f0f3e9d5b2
      
https://github.com/qemu/qemu/commit/111c5f54a1fda35ff3a35d5cb62cd5f0f3e9d5b2
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Logical Instructions

This patch adds the Vector Logical Instructions that are introduced
in Power ISA Version 2.07: veqv, vnand and vorc.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 56eabc750862b985a6ddfc3905b534576eeee33e
      
https://github.com/qemu/qemu/commit/56eabc750862b985a6ddfc3905b534576eeee33e
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo

This patch adds two Altivec unsigned doublword modulo instructions that
are introduced in Power ISA Version V2.07:

  - vaddudm : Vector Add Unsigned Doubleword Modulo
  - vsubudm : Vector Subtrace Unsigned Doubleword Modulo

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: aa9e930c8870d06a20b356785d3ec7d9a942a29f
      
https://github.com/qemu/qemu/commit/aa9e930c8870d06a20b356785d3ec7d9a942a29f
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/int_helper.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers

This VMUL_DO macro provides support for the various vmule* and vmulo*
instructions.  These instructions multiply vector elements, producing
products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit
elements and produces a 16 bit unsigned element.

The existing macro works correctly for the existing instructions (8-bit,
and 16-bit source elements) but does not work correctly for 32-bit
source elements.

This patch adds an explicit cast to the multiplicands, forcing them to be
of the target element type.  This is required for the forthcoming patches
that add the vmul[eo][us]w instructions.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 63be09365a9a4658060e85ce013cc0beaeac25e5
      
https://github.com/qemu/qemu/commit/63be09365a9a4658060e85ce013cc0beaeac25e5
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions

This patch adds the Multilpy Even/Odd Word instructions that are introduced
in Power ISA Version 2.07:

  - Vector Multiply Even Unsigned Word (vmuleuw)
  - Vector Multiply Even Signed Word (vmulesw)
  - Vector Multiply Odd Unsigned Word (vmulouw)
  - Vector Multiply Odd Signed Word (vmulosw)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 953f0f5842a8515fd85ae28ebcdc219f8e7b76fe
      
https://github.com/qemu/qemu/commit/953f0f5842a8515fd85ae28ebcdc219f8e7b76fe
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: vmuluw Instruction

This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm)
instruction.

The existing VARITH_DO macro is re-used to (trivially) instantiate
the helper code.

Since bits 21-31 of any vmuluwm instruction is 137, the instruction
is coded as a dual to vmulouw (bits 21-31 = 136).

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f293f04ab5301f688ce7c9fe3006a787611c2485
      
https://github.com/qemu/qemu/commit/f293f04ab5301f688ce7c9fe3006a787611c2485
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes

This patch adds the Vector Count Leading Zeroes instructions introduced
in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e13500b3c36533e22842bac28f40b2c86ded8c0c
      
https://github.com/qemu/qemu/commit/e13500b3c36533e22842bac28f40b2c86ded8c0c
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Population Count Instructions

This patch adds the Vector Population Count instructions introduced in Power
ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8203e31b547d38a8ec0ce04fe19e6cefe75b4391
      
https://github.com/qemu/qemu/commit/8203e31b547d38a8ec0ce04fe19e6cefe75b4391
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions

This patch adds the Vector Minimum and Maximum Doubleword instructions
that are introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 024215b24210e7c7cbe129279ea94031dd55c791
      
https://github.com/qemu/qemu/commit/024215b24210e7c7cbe129279ea94031dd55c791
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Pack Doubleword Instructions

This patch adds the Vector Pack Doubleword instructions introduced in
Power ISA Version 2.07:

 - Vector Pack Signed Doubleword Signed Saturate (vpksdss)
 - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus)
 - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum)
 - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4430e076632bc904e041914e410c51d2a9a43a99
      
https://github.com/qemu/qemu/commit/4430e076632bc904e041914e410c51d2a9a43a99
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Unpack Signed Word Instructions

This patch adds the Unpack Signed Word instructions introduced in
Power ISA Version 2.07:

  - Vector Unpack High Signed Word (vupkusw)
  - Vector Unpack Low Signed Word (vupklsw)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e0ffe77f275e62a57eceda4c7fbb26e499e9ed86
      
https://github.com/qemu/qemu/commit/e0ffe77f275e62a57eceda4c7fbb26e499e9ed86
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Merge Instructions

This patch adds the Vector Merge Even Word (vmrgew) and Vector
Merge Odd Word (vmrgow) instructions introduced in Power ISA
Version 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 818692ff95f143e640b44726da59646ea7fbcc23
      
https://github.com/qemu/qemu/commit/818692ff95f143e640b44726da59646ea7fbcc23
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/int_helper.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and 
Shifts

Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and 
shift
helpers uses a formula to compute a bit mask used to extract the rotate/shift
amount from the VRB register.  What is desired is:

    mask = (1 << (3 + log2(sizeof(element)))) - 1

but what is implemented is:

    mask = (1 << (3 + (sizeof(element)/2))) - 1

This produces correct answers when "element" is uint8_t, uint16_t or uint_32t.  
But
it breaks down when element is uint64_t.

This patch corrects the situation.  Since the mask is known at compile time, the
macros are changed to simply accept the mask as an argument.

Subsequent patches in this series will add double-word variants of rotates and
shifts and thus take advantage of this fix.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 2fdf78e649b81a14e2c65770fdb0ac3e656a35c5
      
https://github.com/qemu/qemu/commit/2fdf78e649b81a14e2c65770fdb0ac3e656a35c5
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions

This patch adds the vector doublword rotate and shift instructions
introduced in Power ISA Version 2.07:

  - Vector Rotate Left Doubleword instruction (vrld)
  - Vector Shift Left Doubleword (vsld)
  - Vector Shift Right Doubleword (vsrd)
  - Vector Shift Right Algegbraic Doubleword (vsrad)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b41da4ebb2658c4abaaab01e64b9d0bb67dba003
      
https://github.com/qemu/qemu/commit/b41da4ebb2658c4abaaab01e64b9d0bb67dba003
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Quadword Addition and Subtracation

This patch adds the Vector Quadword Addition and Subtraction instructions
introduced in Power ISA Version 2.07:

  - Vector Add Unsigned Quadword Modulo (vadduqm)
  - Vector Add & Write Carry Unsigned Quadword (vaddcuq)
  - Vector Add Extended Unsigned Quadword (vaddeuqm)
  - Vector Add Extended & Write Carry Unsigned Quadword (vaddecuq)
  - Vector Subtract Unsigned Quadword Modulo (vsubuqm)
  - Vector Subtract & Write Carry Unsigned Quadword (vsubcuq)
  - Vector Subtract Extended Unsigned Quadword (vsubeuqm)
  - Vector Subtract Extended & Write Carry Unsigned Quadword (vsubecuq)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 4d82038e4198cdb8aacdf1d605c69cef29748761
      
https://github.com/qemu/qemu/commit/4d82038e4198cdb8aacdf1d605c69cef29748761
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: vbpermq Instruction

This patch adds the Vector Bit Permute Quadword (vbpermq) instruction
introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 6f3dab41fb9ecf1caf9779644e4267af6570dd71
      
https://github.com/qemu/qemu/commit/6f3dab41fb9ecf1caf9779644e4267af6570dd71
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Doubleword Compares

This patch adds the Vector Compare Doubleword instructions introduced
by Power ISA Version 2.07:

  - Vector Compare Equal to Unsigned Doubleword (vcmpequd)
  - Vector Compare Greater Than Signed Doubleword (vcmpgtsd)
  - Vector Compare Greater Than Unsigned Doubleword (vcmpgtud)

These instructions are encoded with bit 31 set to 1 and so are duals with
vcmpeqfp, vcmpgtfp and vcmpbfp respectively.

The helper macro for integer compares is enhanced to account for 64-bit
operands.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f1064f612c9783136f2c59b94a4a8da70d3a09e3
      
https://github.com/qemu/qemu/commit/f1064f612c9783136f2c59b94a4a8da70d3a09e3
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Gather Bits by Bytes

This patch adds the Vector Gather Bits by Bytes Doubleword (vgbbd)
instruction which is introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b8476fc7c6e205f0dc9fff3cfa199eee8af0fa27
      
https://github.com/qemu/qemu/commit/b8476fc7c6e205f0dc9fff3cfa199eee8af0fa27
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum

This patch adds the Vectory Polynomial Multiply Sum instructions
introduced in Power ISA Version 2.07:

  - Vectory Polynomial Multiply Sum Byte (vpmsumb)
  - Vectory Polynomial Multiply Sum Halfword (vpmsumh)
  - Vectory Polynomial Multiply Sum Word (vpmsumw)
  - Vectory Polynomial Multiply Sum Doubleword (vpmsumd)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e8f7b27b9942d02ece7df34ae2b2a09cb9da7196
      
https://github.com/qemu/qemu/commit/e8f7b27b9942d02ece7df34ae2b2a09cb9da7196
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Binary Coded Decimal Instructions

This patch add the Binary Coded Decimal instructions bcdadd. and
bcdsub.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 557d52fa697c938aeff2784b79df55952c3bfcc1
      
https://github.com/qemu/qemu/commit/557d52fa697c938aeff2784b79df55952c3bfcc1
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: AES Instructions

This patch adds the Vector AES instructions introduced in Power ISA
Version 2.07:

   - Vector AES Cipher (vcipher)
   - Vector AES Cipher Last (vcipherlast)
   - Vector AES Inverse Cipher (vncipher)
   - Vector AES Inverse Cipher Last (vncipherlast)
   - Vector AES SubBytes (vsbox)

Note that the implementation of vncipher deviates from the RTL in
ISA V2.07.  However it does match the verbal description in the
third paragraph.  The RTL will be fixed in ISA V2.07B.  The
implementation here has been tested against actual P8 hardware.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 57354f8f12d04efc3c38126b967fc178b56885f5
      
https://github.com/qemu/qemu/commit/57354f8f12d04efc3c38126b967fc178b56885f5
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector SHA Sigma Instructions

This patch adds the Vector SHA Sigma instructions introduced in Power
ISA Version 2.07:

  - Vector SHA-512 Sigma Doubleword (vshasigmad)
  - Vector SHA-256 Sigma Word (vshasigmaw)

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ac174549b730531a4d13c8281e2247e66ba0f46d
      
https://github.com/qemu/qemu/commit/ac174549b730531a4d13c8281e2247e66ba0f46d
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Altivec 2.07: Vector Permute and Exclusive OR

This patch adds the Vector Permuate and Exclusive OR (vpermxor)
instruction introduced in Power ISA Version 2.07.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0a61f3b4782d4dd431c8d6cca6d7fd48d68e1b59
      
https://github.com/qemu/qemu/commit/0a61f3b4782d4dd431c8d6cca6d7fd48d68e1b59
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/net/spapr_llan.c

  Log Message:
  -----------
  spapr-vlan: flush queue whenever can_receive can go from false to true

When the guests adds buffers to receive queue, the network device
should flush its queue of pending packets. This is done with
qemu_flush_queued_packets.

This adds a call to qemu_flush_queued_packets() which wakes up the main
loop and let QEMU update the network device status which now is "can
receive". The patch basically does the same thing as e8b4c68 does.

Suggested-by: Max Filippov <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: e5d7d2b0f55a3b90965044a0ea77e30700a5e136
      
https://github.com/qemu/qemu/commit/e5d7d2b0f55a3b90965044a0ea77e30700a5e136
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc/translate.c: Use ULL suffix for 64 bit constants

64 bit constants need the "ULL" suffix, not just "UL", because
on 32 bit platforms 'long' is not large enough and this will
cause a compiler warning.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Stefan Weil <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3c3b0ddefac9255f29f5e5c2eb346d0a27e6d022
      
https://github.com/qemu/qemu/commit/3c3b0ddefac9255f29f5e5c2eb346d0a27e6d022
  Author: Alexander Graf <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  PPC: sPAPR: Only use getpagesize() when we run with kvm

We currently size the msi window trap page according to the host's page
size so that we poke a working hole into a memory slot in case we overlap.

However, this is only ever necessary with KVM active. Without KVM, we should
rather try to be host platform agnostic and use a constant size: 4k.

This fixes a build breakage on win32 hosts.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7dff9abe639e5baa6faa78267cc10726504b8de5
      
https://github.com/qemu/qemu/commit/7dff9abe639e5baa6faa78267cc10726504b8de5
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/fpu_helper.c

  Log Message:
  -----------
  target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL

This patch fixes 64 bit constants that were erroneously declared as "ul" 
instead of
"ull".  The preferred form "ULL" is used.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3707cd62db79ba965a211b9e2bb808792ae7343a
      
https://github.com/qemu/qemu/commit/3707cd62db79ba965a211b9e2bb808792ae7343a
  Author: Tom Musta <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  target-ppc: Use Additional Temporary in stqcx Case

Per Alex Graf's suggestion, the recently added case to gen_conditional_store
for stqcx should use an additional temporary when accessing the second
doubleword.  This avoids the mutation of the EA argument to the function,
which is counter intuitive.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f3c75d42adbba553eaf218a832d4fbea32c8f7b8
      
https://github.com/qemu/qemu/commit/f3c75d42adbba553eaf218a832d4fbea32c8f7b8
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M target-ppc/cpu.h
    M target-ppc/kvm.c
    M target-ppc/machine.c
    M target-ppc/misc_helper.c
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu_helper.c

  Log Message:
  -----------
  target-ppc: Fix htab_mask calculation

Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. We check for external htab and if
found true, we don't need to update sdr1

Signed-off-by: Aneesh Kumar K.V <address@hidden>
[ fixed pte group offset computation in ppc_hash64_htab_lookup() that
  caused TCG to fail, Greg Kurz <address@hidden> ]
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 7c43bca004afdb2a86c20ab3131ec1eb7a78d80d
      
https://github.com/qemu/qemu/commit/7c43bca004afdb2a86c20ab3131ec1eb7a78d80d
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu-hash64.h

  Log Message:
  -----------
  target-ppc: Fix page table lookup with kvm enabled

With kvm enabled, we store the hash page table information in the hypervisor.
Use ioctl to read the htab contents. Without this we get the below error when
trying to read the guest address

 (gdb) x/10 do_fork
 0xc000000000098660 <do_fork>:   Cannot access memory at address 
0xc000000000098660
 (gdb)

Signed-off-by: Aneesh Kumar K.V <address@hidden>
[ fixes for 32 bit build (casts!), ldq_phys() API change,
  Greg Kurz <address@hidden ]
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3f94170be35e3d15d63498e9f0beeee6775be47d
      
https://github.com/qemu/qemu/commit/3f94170be35e3d15d63498e9f0beeee6775be47d
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr_hcall.c
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu-hash64.h

  Log Message:
  -----------
  target-ppc: Change the hpte store API

For updating in kernel htab we need to provide both pte0 and pte1, hence update
the interface to take pte0 and pte1 together

Signed-off-by: Aneesh Kumar K.V <address@hidden>
[ ldq_phys() API change, Greg Kurz <address@hidden> ]
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c1385933804bb432a53d7a49836250d61b6e48bd
      
https://github.com/qemu/qemu/commit/c1385933804bb432a53d7a49836250d61b6e48bd
  Author: Aneesh Kumar K.V <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu-hash64.h

  Log Message:
  -----------
  target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab

This support updating htab managed by the hypervisor. Currently we don't have
any user for this feature. This actually bring the store_hpte interface
in-line with the load_hpte one. We may want to use this when we want to
emulate henter hcall in qemu for HV kvm.

Signed-off-by: Aneesh Kumar K.V <address@hidden>
[ folded fix for the "warn_unused_result" build break in
  kvmppc_hash64_write_pte(), Greg Kurz <address@hidden> ]
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a0fcac9c21dcbf481eeb5573a738f55023f5a953
      
https://github.com/qemu/qemu/commit/a0fcac9c21dcbf481eeb5573a738f55023f5a953
  Author: Laurent Dufour <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/spapr_iommu.c
    M trace-events

  Log Message:
  -----------
  target-ppc: Introduce hypervisor call H_GET_TCE

This patch introduces the hypervisor call H_GET_TCE which is basically the
reverse of H_PUT_TCE, as defined in the Power Architecture Platform
Requirements (PAPR).

The hcall H_GET_TCE is required by the kdump kernel which is calling it to
retrieve the TCE set up by the panicing kernel.

Signed-off-by: Laurent Dufour <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0ce470cd4ca88e84e547a3b95159d23ce6be419e
      
https://github.com/qemu/qemu/commit/0ce470cd4ca88e84e547a3b95159d23ce6be419e
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/ppc/ppc.c
    M target-ppc/cpu-qom.h
    M target-ppc/cpu.h
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: add PowerPCCPU::cpu_dt_id

Normally CPUState::cpu_index is used to pick the right CPU for various
operations. However default consecutive numbering does not always work
for POWERPC.

These indexes are reflected in /proc/device-tree/cpus/PowerPC,address@hidden
and used to call KVM VCPU's ioctls. In order to achieve this,
kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies
cpu_index by the number of threads per core.

This approach has disadvantages such as:
1. NUMA configuration stays broken after the fixup;
2. CPU-targeted commands from the QEMU Monitor do not work properly as
CPU indexes have been fixed and there is no clear way for the user to
know what the new CPU indexes are.

This introduces a @cpu_dt_id field in the CPUPPCState struct which
is initialized from @cpu_index by default and can be fixed later
to meet the device tree requirements.

This adds an API to handle @cpu_dt_id.

This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id
is calculated in ppc_cpu_realize().

This will be used later in machine code.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Acked-by: Mike Day <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 0f20ba62c35e6a779ba4ea00616192ef2abb6896
      
https://github.com/qemu/qemu/commit/0f20ba62c35e6a779ba4ea00616192ef2abb6896
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2014-03-05 (Wed, 05 Mar 2014)

  Changed paths:
    M hw/intc/openpic_kvm.c
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/ppc/e500.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_rtas.c
    M target-ppc/kvm.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: spapr: e500: fix to use cpu_dt_id

This makes use of @cpu_dt_id and related API in:
1. emulated XICS hypercall handlers as they receive fixed CPU indexes;
2. XICS-KVM to enable in-kernel XICS on right CPU;
3. device-tree renderer.

This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor
can accept command-line CPU indexes again.

This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment
KVM CPU id and device tree ID are calculated using the same algorithm.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Acked-by: Mike Day <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: bb2b04503497608cdc5fa4c990d26e936f9d2102
      
https://github.com/qemu/qemu/commit/bb2b04503497608cdc5fa4c990d26e936f9d2102
  Author: Peter Maydell <address@hidden>
  Date:   2014-03-07 (Fri, 07 Mar 2014)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M hw/core/loader.c
    M hw/core/qdev.c
    M hw/i386/pc_piix.c
    M hw/intc/openpic_kvm.c
    M hw/intc/xics.c
    M hw/intc/xics_kvm.c
    M hw/moxie/moxiesim.c
    M hw/net/Makefile.objs
    A hw/net/fsl_etsec/etsec.c
    A hw/net/fsl_etsec/etsec.h
    A hw/net/fsl_etsec/miim.c
    A hw/net/fsl_etsec/registers.c
    A hw/net/fsl_etsec/registers.h
    A hw/net/fsl_etsec/rings.c
    M hw/net/spapr_llan.c
    M hw/ppc/e500.c
    M hw/ppc/ppc.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_hcall.c
    M hw/ppc/spapr_iommu.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/virtex_ml507.c
    M hw/s390x/ipl.c
    M hw/scsi/spapr_vscsi.c
    M include/hw/boards.h
    M include/hw/elf_ops.h
    M include/hw/loader.h
    M include/hw/qdev-core.h
    M include/hw/xen/xen.h
    M include/qemu/host-utils.h
    M include/sysemu/kvm.h
    A include/sysemu/qemumachine.h
    M include/sysemu/qtest.h
    M kvm-all.c
    M kvm-stub.c
    M linux-user/main.c
    M qtest.c
    M target-ppc/STATUS
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu-qom.h
    M target-ppc/cpu.h
    M target-ppc/fpu_helper.c
    M target-ppc/helper.h
    M target-ppc/int_helper.c
    M target-ppc/kvm.c
    M target-ppc/kvm_ppc.h
    M target-ppc/machine.c
    M target-ppc/misc_helper.c
    M target-ppc/mmu-hash64.c
    M target-ppc/mmu-hash64.h
    M target-ppc/mmu_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c
    M trace-events
    M util/host-utils.c
    M vl.c
    M xen-all.c
    M xen-stub.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' 
into staging

Patch queue for ppc - 2014-03-05

This pull request includes:

  - VSX emulation support
  - book3s pr/hv selection
  - some bug fixes
  - qdev stable numbering
  - eTSEC emulation

# gpg: Signature made Wed 05 Mar 2014 02:14:19 GMT using RSA key ID 03FEDC60
# gpg: Can't check signature: public key not found

* remotes/agraf/tags/signed-ppc-for-upstream: (130 commits)
  target-ppc: spapr: e500: fix to use cpu_dt_id
  target-ppc: add PowerPCCPU::cpu_dt_id
  target-ppc: Introduce hypervisor call H_GET_TCE
  target-ppc: Update ppc_hash64_store_hpte to support updating in-kernel htab
  target-ppc: Change the hpte store API
  target-ppc: Fix page table lookup with kvm enabled
  target-ppc: Fix htab_mask calculation
  target-ppc: Use Additional Temporary in stqcx Case
  target-ppc: Fix Compiler Warnings Due to 64-Bit Constants Declared as UL
  PPC: sPAPR: Only use getpagesize() when we run with kvm
  target-ppc/translate.c: Use ULL suffix for 64 bit constants
  spapr-vlan: flush queue whenever can_receive can go from false to true
  target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
  target-ppc: Altivec 2.07: Vector SHA Sigma Instructions
  target-ppc: Altivec 2.07: AES Instructions
  target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
  target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
  target-ppc: Altivec 2.07: Vector Gather Bits by Bytes
  target-ppc: Altivec 2.07: Doubleword Compares
  target-ppc: Altivec 2.07: vbpermq Instruction
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c3f8d28e455b...bb2b04503497

reply via email to

[Prev in Thread] Current Thread [Next in Thread]