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[Qemu-commits] [qemu/qemu] ec1efa: hw/misc/arm_sysctl: Fix bad boundary


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] ec1efa: hw/misc/arm_sysctl: Fix bad boundary check on mb c...
Date: Thu, 27 Feb 2014 03:30:06 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ec1efab95767312ff4afb816d0d4b548e093b031
      
https://github.com/qemu/qemu/commit/ec1efab95767312ff4afb816d0d4b548e093b031
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/misc/arm_sysctl.c

  Log Message:
  -----------
  hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses

Fix incorrect use of sizeof() rather than ARRAY_SIZE() to guard
accesses into the mb_clock[] array, which was allowing a malicious
guest to overwrite the end of the array.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Message-id: address@hidden
Cc: address@hidden


  Commit: 106a73b6d200035c5156f90b5f9b6a53d3adb43b
      
https://github.com/qemu/qemu/commit/106a73b6d200035c5156f90b5f9b6a53d3adb43b
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/net/stellaris_enet.c

  Log Message:
  -----------
  hw/net/stellaris_enet: Avoid unintended sign extension

Add a cast to avoid an unintended sign extension that
would mean we returned 0xffffffff in the high 32 bits
for an IA0 read if bit 31 in the MAC address was 1.
(This is harmless since we'll only be doing 4 byte
reads, but it could be confusing, so best avoided.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Message-id: address@hidden


  Commit: cba933b2257ef0ad241756a0ff86bc0acda685ca
      
https://github.com/qemu/qemu/commit/cba933b2257ef0ad241756a0ff86bc0acda685ca
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/timer/arm_timer.c

  Log Message:
  -----------
  hw/timer/arm_timer: Avoid array overrun for bad addresses

The integrator's timer read/write functions log an error for
bad addresses in guest accesses, but were falling through and
using an out of bounds array index rather than returning early.
Fix this.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Message-id: address@hidden
Cc: address@hidden


  Commit: 775fda92a1b52c784cd51c095d67fcca7250e1e5
      
https://github.com/qemu/qemu/commit/775fda92a1b52c784cd51c095d67fcca7250e1e5
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops

Correct some obviously nonsensical bit manipulation spotted by Coverity
when constructing the short-form PAR value for ATS operations.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: fce0a826083e0416981e2ea9518ce5faa75b81a3
      
https://github.com/qemu/qemu/commit/fce0a826083e0416981e2ea9518ce5faa75b81a3
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/intc/exynos4210_combiner.c

  Log Message:
  -----------
  hw/intc/exynos4210_combiner: Don't overrun output_irq array in init

The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs;
use the correct constant in the loop initializing our output
sysbus IRQs so that we don't overrun the output_irq[] array.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Andreas Färber <address@hidden>
Cc: address@hidden


  Commit: cf143ad35018c5fc1da6365b45acda2b34aba90a
      
https://github.com/qemu/qemu/commit/cf143ad35018c5fc1da6365b45acda2b34aba90a
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/arm/musicpal.c

  Log Message:
  -----------
  hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registers

The ethernet device in the musicpal only has two tx queues,
but we modelled it with four CTDP registers, presumably a
cut and paste from the rx queue registers. Since the tx_queue[]
array is only 2 entries long this allowed a guest to overrun
this buffer. Remove the nonexistent registers.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Acked-by: Jan Kiszka <address@hidden>
Cc: address@hidden


  Commit: c10f7fc3d167799f19d2184f05012b24cc56878d
      
https://github.com/qemu/qemu/commit/c10f7fc3d167799f19d2184f05012b24cc56878d
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Load correct access bits from ARMv5 level 2 page table descriptors

In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into
four subpages, each of which can have different access permission settings,
which are specified by four two-bit fields in the l2 descriptor. A
long-standing cut-and-paste error meant we were using the wrong bits in
the virtual address to select the access-permission field for 4K pages.

The error has presumably not been noticed before because most guests don't
make use of the ability to set the access permissions differently for
each 1K subpage: if the guest gives the whole page the same access
permissions it doesn't matter which of the 4 AP fields we select.
(The whole issue is irrelevant for ARMv7 CPUs anyway because subpages
aren't supported there.)

Reported-by: Vivek Rai <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 6453fa998a11e133e673c0a613b88484a8231d1d
      
https://github.com/qemu/qemu/commit/6453fa998a11e133e673c0a613b88484a8231d1d
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/intc/gic_internal.h

  Log Message:
  -----------
  hw/intc/arm_gic: Fix GIC_SET_LEVEL

The GIC_SET_LEVEL macro unfortunately overwrote the entire level
bitmask instead of just or'ing on the necessary bits, causing active
level PPIs on a core to clear PPIs on other cores.

Cc: address@hidden
Reported-by: Rob Herring <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 876074c228ddccffe9bfcf31920202d68777545b
      
https://github.com/qemu/qemu/commit/876074c228ddccffe9bfcf31920202d68777545b
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M linux-headers/asm-arm/kvm.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-powerpc/kvm.h
    M linux-headers/asm-x86/hyperv.h
    M linux-headers/linux/kvm.h

  Log Message:
  -----------
  linux-headers: Update from v3.14-rc3

Update to tag v3.14-rc3 (6d0abeca3242a88cab8232e4acd7e2bf088f3bc2)

Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d6032e06d10d20e91729816a8c9c6792e5774ab1
      
https://github.com/qemu/qemu/commit/d6032e06d10d20e91729816a8c9c6792e5774ab1
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c
    M stubs/Makefile.objs
    A stubs/kvm.c

  Log Message:
  -----------
  kvm: Introduce kvm_arch_irqchip_create

Introduce kvm_arch_irqchip_create an arch-specific hook in preparation
for architecture-specific use of the device control API to create IRQ
chips.

Following patches will implement the ARM irqchip create method to prefer
the device control API over the older KVM_CREATE_IRQCHIP API.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0a6a7ccaae4015aa02bdbce75bafb9d868636655
      
https://github.com/qemu/qemu/commit/0a6a7ccaae4015aa02bdbce75bafb9d868636655
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M include/sysemu/kvm.h
    M kvm-all.c
    M trace-events

  Log Message:
  -----------
  kvm: Common device control API functions

Introduces two simple functions:
    int kvm_device_ioctl(int fd, int type, ...);
    int kvm_create_device(KVMState *s, uint64_t type, bool test);

These functions wrap the basic ioctl-based interactions with KVM in a
way similar to other KVM ioctl wrappers.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1da41cc1c6c3efbe2ed47228068bd80dbdc49d0e
      
https://github.com/qemu/qemu/commit/1da41cc1c6c3efbe2ed47228068bd80dbdc49d0e
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic_kvm.c
    M include/hw/intc/arm_gic_common.h
    M target-arm/kvm.c
    M target-arm/kvm_arm.h

  Log Message:
  -----------
  arm: vgic device control api support

Support creating the ARM vgic device through the device control API and
setting the base address for the distributor and cpu interfaces in KVM
VMs using this API.

Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be
created prior to creating the VCPUs, we first test if we can use the
device control API in kvm_arch_irqchip_create (using the test flag from
the device control API).  If we cannot, it means we have to fall back to
KVM_CREATE_IRQCHIP and use the older ioctl at this point in time.  If
however, we can use the device control API, we don't do anything and
wait until the arm_gic_kvm driver initializes and let that use the
device control API.

Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 855011be05fad72e17e0280d0bab87a4bc840695
      
https://github.com/qemu/qemu/commit/855011be05fad72e17e0280d0bab87a4bc840695
  Author: Christoffer Dall <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic_kvm.c

  Log Message:
  -----------
  hw: arm_gic_kvm: Add KVM VGIC save/restore logic

Save and restore the ARM KVM VGIC state from the kernel.  We rely on
QEMU to marshal the GICState data structure and therefore simply
synchronize the kernel state with the QEMU emulated state in both
directions.

We take some care on the restore path to check the VGIC has been
configured with enough IRQs and CPU interfaces that we can properly
restore the state, and for separate set/clear registers we first fully
clear the registers and then set the required bits.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 67ed771dedd2a7c6f094e0d70fb1fde8f5fb79da
      
https://github.com/qemu/qemu/commit/67ed771dedd2a7c6f094e0d70fb1fde8f5fb79da
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix raw read and write functions on AArch64 registers

The raw read and write functions were using the ARM_CP_64BIT flag in
ri->type to determine whether to treat the register's state field as
uint32_t or uint64_t; however AArch64 register info structs don't use
that flag. Abstract out the "how big is the field?" test into a
function and fix it to work for AArch64 registers. For this to work
we must ensure that the reginfo structs put into the hashtable have
the correct state field for their use, not the placeholder STATE_BOTH.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7da845b0f42a791d65045284f90977d636c654cc
      
https://github.com/qemu/qemu/commit/7da845b0f42a791d65045284f90977d636c654cc
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: A64: Make cache ID registers visible to AArch64

Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementation in favour of using the CPU-specified
reset value, and implement the system-mode-required semantics of
restricting its EL0 accessibility if SCTLR.UCT is not set.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 0eef9d9833df1c2376bd3b761abc6580df15af3b
      
https://github.com/qemu/qemu/commit/0eef9d9833df1c2376bd3b761abc6580df15af3b
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Implement AArch64 CurrentEL sysreg

Implement the CurrentEL sysreg.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: cd4da6317748e3ae2bed5fcc5fb3f81e5c853446
      
https://github.com/qemu/qemu/commit/cd4da6317748e3ae2bed5fcc5fb3f81e5c853446
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 MIDR_EL1

Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 8af35c37d296daa463c0d4ed575a51729afc7f6d
      
https://github.com/qemu/qemu/commit/8af35c37d296daa463c0d4ed575a51729afc7f6d
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 cache invalidate/clean ops

Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 168aa23bb01a1f6266ba9228dfd248617872ca5c
      
https://github.com/qemu/qemu/commit/168aa23bb01a1f6266ba9228dfd248617872ca5c
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 TLB invalidate ops

Implement the AArch64 TLB invalidate operations. This is
the full set of TLBI ops defined for a CPU which doesn't
implement EL2 or EL3.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 91e240698f6a82cb73893ee0ce26369aa6232f7b
      
https://github.com/qemu/qemu/commit/91e240698f6a82cb73893ee0ce26369aa6232f7b
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 dummy MDSCR_EL1

We don't support letting the guest do debug, but Linux prods the
monitor debug system control register anyway, so implement a dummy
RAZ/WI version.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: b0fe2427511232f361942f672511970e5c75eb4b
      
https://github.com/qemu/qemu/commit/b0fe2427511232f361942f672511970e5c75eb4b
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 memory attribute registers

Implement the AArch64 memory attribute registers. Since QEMU doesn't
model caches it does not need to care about memory attributes at all,
and we can simply make these read-as-written.

We did not previously implement the AArch32 versions of the MAIR
registers, which went unnoticed because of the overbroad TLB_LOCKDOWN
reginfo definition; provide them now to keep the 64<->32 register
relationship clear.

We already provided AMAIR registers for 32 bit as simple RAZ/WI;
extend that to provide a 64 bit RAZ/WI AMAIR_EL1.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e
      
https://github.com/qemu/qemu/commit/5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 SCTLR_EL1

Implement the AArch64 view of the system control register SCTLR_EL1.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: cb2e37dffaab38e962b86b3ca6f4cf0de22d9e69
      
https://github.com/qemu/qemu/commit/cb2e37dffaab38e962b86b3ca6f4cf0de22d9e69
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 TCR_EL1

Implement the AArch64 TCR_EL1, which is the 64 bit view of
the AArch32 TTBCR. (The uses of the bits in the register are
completely different, but in any given situation the CPU will
always interpret them one way or the other. In fact for QEMU EL1
is always 64 bit, but we share the state field because this
is the correct mapping to permit a future implementation of EL2.)
We also make the AArch64 view the 'master' as far as migration
and reset is concerned.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: a505d7fe5f638c4aaba93150f71968147f7c2b3a
      
https://github.com/qemu/qemu/commit/a505d7fe5f638c4aaba93150f71968147f7c2b3a
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 VBAR_EL1

Implement the A64 view of the VBAR system register.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 327ed10fa2331384c1a58c794e0356e6d88089c8
      
https://github.com/qemu/qemu/commit/327ed10fa2331384c1a58c794e0356e6d88089c8
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/arm/pxa2xx.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 TTBR*

Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the architectural name.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 4b7fff2fabeaa3d13e23b249b855f39f0921048d
      
https://github.com/qemu/qemu/commit/4b7fff2fabeaa3d13e23b249b855f39f0921048d
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 MPIDR

Implement the AArch64 MPIDR system register.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: a7adc4b779d24e75d05d43fb6311ab9e6449523a
      
https://github.com/qemu/qemu/commit/a7adc4b779d24e75d05d43fb6311ab9e6449523a
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 generic timers

Implement the AArch64 view of the generic timer system registers.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: e60cef860f76cd558ee70e1d145eea1c24de20e7
      
https://github.com/qemu/qemu/commit/e60cef860f76cd558ee70e1d145eea1c24de20e7
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 ID and feature registers

Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 0b45451e588e35965175c06b832a799a159716f0
      
https://github.com/qemu/qemu/commit/0b45451e588e35965175c06b832a799a159716f0
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 dummy breakpoint and watchpoint registers

In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: cd5c11b84b2539049e0fdc2c4c5f3e86e88a8bff
      
https://github.com/qemu/qemu/commit/cd5c11b84b2539049e0fdc2c4c5f3e86e88a8bff
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI

Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: d9ea7d290b685844d3603103bc53ad977e6f68a3
      
https://github.com/qemu/qemu/commit/d9ea7d290b685844d3603103bc53ad977e6f68a3
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Get MMU index information correct for A64 code

Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in
AArch64 mode.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 1ed69e82b8f1dc69eb4c3e556a6417885a5dd49c
      
https://github.com/qemu/qemu/commit/1ed69e82b8f1dc69eb4c3e556a6417885a5dd49c
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement WFI

Implement the WFI instruction for A64; this just involves wiring
up the instruction, and adding a gen_a64_set_pc_im() which was
accidentally omitted from the A64 decoder top loop.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 4cc35614a056839df8b0675cd16f55e758cd570d
      
https://github.com/qemu/qemu/commit/4cc35614a056839df8b0675cd16f55e758cd570d
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M cpu-exec.c
    M hw/arm/pxa2xx.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Store AIF bits in env->pstate for AArch32

To avoid complication in code that otherwise would not need to
care about whether EL1 is AArch32 or AArch64, we should store
the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF
in AArch64) in one place consistently regardless of EL1's mode.
Since AArch64 has an extra enable bit (D for debug exceptions)
which isn't visible in AArch32, this means we need to keep
the enables in env->pstate. (This is also consistent with the
general approach we're taking that we handle 32 bit CPUs as
being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 9cfa0b4e4c3076683b6c528a1a3b43d5a202a497
      
https://github.com/qemu/qemu/commit/9cfa0b4e4c3076683b6c528a1a3b43d5a202a497
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement MSR (immediate) instructions

Implement the MSR (immediate) instructions, which can update the
PSTATE SP and DAIF fields.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 34222fb8101298ead0e43766340843b469597580
      
https://github.com/qemu/qemu/commit/34222fb8101298ead0e43766340843b469597580
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Implement AArch64 view of CPACR

Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole register this way.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 1f79ee32b556cad0b6db6f7c866ac4e6b4244cc1
      
https://github.com/qemu/qemu/commit/1f79ee32b556cad0b6db6f7c866ac4e6b4244cc1
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Add utility function for checking AA32/64 state of an EL

There are various situations where we need to behave differently
depending on whether a given exception level is in AArch64 or
AArch32 state. The state of the current exception level is stored
in env->aarch64, but there's no equivalent guest-visible architected
state bits for the status of the exception levels "above" the
current one which may still affect execution. At the moment we
only support EL1 (ie no EL2 or EL3) and insist that AArch64
capable CPUs run with EL1 in AArch64 state, but these may change
in the future, so abstract out the "what state is this?" check
into a utility function which can be enhanced later if necessary.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 0956ff5a4e1fceb33e098133dd2b083647bb8eaa
      
https://github.com/qemu/qemu/commit/0956ff5a4e1fceb33e098133dd2b083647bb8eaa
  Author: Will Newton <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M include/qemu/crc32c.h

  Log Message:
  -----------
  include/qemu/crc32c.h: Rename include guards to match filename

Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: eb0ecd5ad908b72dfe4fadf84272616b2de101d1
      
https://github.com/qemu/qemu/commit/eb0ecd5ad908b72dfe4fadf84272616b2de101d1
  Author: Will Newton <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M configure
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 ARMv8 CRC32 instructions

Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8
and add a CPU feature flag to enable these instructions.

The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ensure it is linked for the linux-user binary.

Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 63a31905cbce5e7c2503dd22bf5977636df271e5
      
https://github.com/qemu/qemu/commit/63a31905cbce5e7c2503dd22bf5977636df271e5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: Delete overly verbose debug printf

When using event synchronisation, this particular debug printf floods.
Just delete it.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 024c6e2ea575d6ca2e3e1cfb8fcff7f218bb5daf
      
https://github.com/qemu/qemu/commit/024c6e2ea575d6ca2e3e1cfb8fcff7f218bb5daf
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: Fix misleading type

This type really should just be a regular int as no usages rely on it's
32 bitness (it's only meaningful as a bit position and not a bit mask).
This also fixes a printf which uses the variable with a regular %d.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c3143ba87768cbbedece32b90aa5eb5485d6d23b
      
https://github.com/qemu/qemu/commit/c3143ba87768cbbedece32b90aa5eb5485d6d23b
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: printf format type sweep.

Use PRI formats as appropriate rather than raw %x and %d. This fixes
debug printfery on some host platforms. Fix types of debug only
variables as appropriate.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1c8be73d4ec576450f315d6a94fc0c89e200c479
      
https://github.com/qemu/qemu/commit/1c8be73d4ec576450f315d6a94fc0c89e200c479
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: Rename parent_obj

As per current QOM conventions.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 432a0a130e203e18656e54f59e817271bf1c078f
      
https://github.com/qemu/qemu/commit/432a0a130e203e18656e54f59e817271bf1c078f
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: Add event debugging printfs

These are helpful to anyone trying to debug event sequencing.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a5ae7e3984d4bb624d6e8ec95c64fa272deb07fc
      
https://github.com/qemu/qemu/commit/a5ae7e3984d4bb624d6e8ec95c64fa272deb07fc
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: Fix buffer depth

This is the product of the data-width and the depth arguments, I.e the
depth of the FIFO is in terms of data entries and not bytes (which is
what the original implementation was suggesting). Fix.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c04018e93390e31b40044f3db92c173fb0ccb3d2
      
https://github.com/qemu/qemu/commit/c04018e93390e31b40044f3db92c173fb0ccb3d2
  Author: Peter Crosthwaite <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M hw/dma/pl330.c

  Log Message:
  -----------
  dma/pl330: implement dmaadnh instruction

Implement the missing DMAADNH instruction. This is a minor variant
of the DMAADDH instruction, so factor out to a common implementation
for both (dmaadxh).

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2ce5868ca1457d1dcbaa917df98ca1ba28593e40
      
https://github.com/qemu/qemu/commit/2ce5868ca1457d1dcbaa917df98ca1ba28593e40
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-26 (Wed, 26 Feb 2014)

  Changed paths:
    M configure
    M cpu-exec.c
    M hw/arm/musicpal.c
    M hw/arm/pxa2xx.c
    M hw/dma/pl330.c
    M hw/intc/arm_gic_kvm.c
    M hw/intc/exynos4210_combiner.c
    M hw/intc/gic_internal.h
    M hw/misc/arm_sysctl.c
    M hw/net/stellaris_enet.c
    M hw/timer/arm_timer.c
    M include/hw/intc/arm_gic_common.h
    M include/qemu/crc32c.h
    M include/sysemu/kvm.h
    M kvm-all.c
    M linux-headers/asm-arm/kvm.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-powerpc/kvm.h
    M linux-headers/asm-x86/hyperv.h
    M linux-headers/linux/kvm.h
    M stubs/Makefile.objs
    A stubs/kvm.c
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/kvm.c
    M target-arm/kvm_arm.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140226' 
into staging

target-arm queue:
 * fixes for various Coverity-spotted bugs
 * support new KVM device control API for VGIC
 * support KVM VGIC save/restore/migration
 * more AArch64 system mode foundations
 * support ARMv8 CRC instructions for A32/T32
 * PL330 minor fixes and cleanup

# gpg: Signature made Wed 26 Feb 2014 17:51:32 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140226: (45 commits)
  dma/pl330: implement dmaadnh instruction
  dma/pl330: Fix buffer depth
  dma/pl330: Add event debugging printfs
  dma/pl330: Rename parent_obj
  dma/pl330: printf format type sweep.
  dma/pl330: Fix misleading type
  dma/pl330: Delete overly verbose debug printf
  target-arm: Add support for AArch32 ARMv8 CRC32 instructions
  include/qemu/crc32c.h: Rename include guards to match filename
  target-arm: Add utility function for checking AA32/64 state of an EL
  target-arm: Implement AArch64 view of CPACR
  target-arm: A64: Implement MSR (immediate) instructions
  target-arm: Store AIF bits in env->pstate for AArch32
  target-arm: A64: Implement WFI
  target-arm: Get MMU index information correct for A64 code
  target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
  target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
  target-arm: Implement AArch64 ID and feature registers
  target-arm: Implement AArch64 generic timers
  target-arm: Implement AArch64 MPIDR
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/6f6831f61a44...2ce5868ca145

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