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[Qemu-commits] [qemu/qemu] e0db90: hw/xtensa: add support for ML605 and
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[Qemu-commits] [qemu/qemu] e0db90: hw/xtensa: add support for ML605 and KC705 FPGA bo... |
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Tue, 25 Feb 2014 04:30:05 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e0db904d1dc97be0eed7fbb52954d03ec05bee07
https://github.com/qemu/qemu/commit/e0db904d1dc97be0eed7fbb52954d03ec05bee07
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M hw/xtensa/xtensa_lx60.c
Log Message:
-----------
hw/xtensa: add support for ML605 and KC705 FPGA board
Signed-off-by: Max Filippov <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Commit: b807b5ff894b79e31ccd2ff5bd023577ecf45a6a
https://github.com/qemu/qemu/commit/b807b5ff894b79e31ccd2ff5bd023577ecf45a6a
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M hw/net/opencores_eth.c
Log Message:
-----------
opencores_eth: flush queue whenever can_receive can go from false to true
The following registers control whether MAC can receive frames:
- MODER.RXEN bit that enables/disables receiver;
- TX_BD_NUM register that specifies number of RX descriptors.
Notify QEMU networking core when the MAC is ready to receive frames.
Discard frame and raise BUSY interrupt when the frame arrives but the
current RX descriptor is not empty.
Signed-off-by: Max Filippov <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Commit: 6502668237a27985dd386c6e42b46e8977b4f2c0
https://github.com/qemu/qemu/commit/6502668237a27985dd386c6e42b46e8977b4f2c0
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: add RRRI4 opcode format fields
This encoding is used by cache instructions.
Signed-off-by: Max Filippov <address@hidden>
Commit: 7c84259019a945e4ff275994b96c0de4496d2a5e
https://github.com/qemu/qemu/commit/7c84259019a945e4ff275994b96c0de4496d2a5e
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: add basic checks to dcache opcodes
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.
Signed-off-by: Max Filippov <address@hidden>
Commit: e848dd4248230c0463841a16d1fa9eb054a2d211
https://github.com/qemu/qemu/commit/e848dd4248230c0463841a16d1fa9eb054a2d211
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M target-xtensa/helper.h
M target-xtensa/op_helper.c
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: add basic checks to icache opcodes
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.
Signed-off-by: Max Filippov <address@hidden>
Commit: d0fa1f0df3c8c269df083e2c8a10dfad09dffcf3
https://github.com/qemu/qemu/commit/d0fa1f0df3c8c269df083e2c8a10dfad09dffcf3
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M tests/tcg/xtensa/macros.inc
M tests/tcg/xtensa/test_mmu.S
Log Message:
-----------
target-xtensa: add overridable test_init macro
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.
Signed-off-by: Max Filippov <address@hidden>
Commit: a2e67072b7c3b2abf70d0a11918723a5dd841a05
https://github.com/qemu/qemu/commit/a2e67072b7c3b2abf70d0a11918723a5dd841a05
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M tests/tcg/xtensa/Makefile
M tests/tcg/xtensa/macros.inc
M tests/tcg/xtensa/test_b.S
M tests/tcg/xtensa/test_bi.S
M tests/tcg/xtensa/test_boolean.S
M tests/tcg/xtensa/test_break.S
M tests/tcg/xtensa/test_bz.S
M tests/tcg/xtensa/test_clamps.S
M tests/tcg/xtensa/test_extui.S
M tests/tcg/xtensa/test_fail.S
M tests/tcg/xtensa/test_interrupt.S
M tests/tcg/xtensa/test_loop.S
M tests/tcg/xtensa/test_mac16.S
M tests/tcg/xtensa/test_max.S
M tests/tcg/xtensa/test_min.S
M tests/tcg/xtensa/test_mmu.S
M tests/tcg/xtensa/test_mul16.S
M tests/tcg/xtensa/test_mul32.S
M tests/tcg/xtensa/test_nsa.S
M tests/tcg/xtensa/test_pipeline.S
M tests/tcg/xtensa/test_quo.S
M tests/tcg/xtensa/test_rem.S
M tests/tcg/xtensa/test_rst0.S
M tests/tcg/xtensa/test_s32c1i.S
M tests/tcg/xtensa/test_sar.S
M tests/tcg/xtensa/test_sext.S
M tests/tcg/xtensa/test_shift.S
M tests/tcg/xtensa/test_sr.S
M tests/tcg/xtensa/test_timer.S
M tests/tcg/xtensa/test_windowed.S
Log Message:
-----------
target-xtensa: allow using core configuration in tests
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.
Signed-off-by: Max Filippov <address@hidden>
Commit: 2c09eee112677c64a5e060eb9d491981843d7531
https://github.com/qemu/qemu/commit/2c09eee112677c64a5e060eb9d491981843d7531
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M tests/tcg/xtensa/Makefile
A tests/tcg/xtensa/test_cache.S
Log Message:
-----------
target-xtensa: add basic tests for cache opcodes
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.
Signed-off-by: Max Filippov <address@hidden>
Commit: 676056d4f1598f3f368da26fdc43371e8ab3a7fb
https://github.com/qemu/qemu/commit/676056d4f1598f3f368da26fdc43371e8ab3a7fb
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M target-xtensa/core-dc232b.c
M target-xtensa/core-dc233c.c
M target-xtensa/core-fsf.c
M target-xtensa/overlay_tool.h
Log Message:
-----------
target-xtensa: refactor standard core configuration
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov <address@hidden>
Commit: 604e1f9cd0602e92ba49a27dd3a46db3d29f882e
https://github.com/qemu/qemu/commit/604e1f9cd0602e92ba49a27dd3a46db3d29f882e
Author: Max Filippov <address@hidden>
Date: 2014-02-23 (Sun, 23 Feb 2014)
Changed paths:
M target-xtensa/cpu.c
M target-xtensa/cpu.h
M target-xtensa/overlay_tool.h
M target-xtensa/translate.c
Log Message:
-----------
target-xtensa: provide HW confg ID registers
Signed-off-by: Max Filippov <address@hidden>
Commit: 05fd3bf2a1c9fc26414d3cf608732c40d0d9eb23
https://github.com/qemu/qemu/commit/05fd3bf2a1c9fc26414d3cf608732c40d0d9eb23
Author: Peter Maydell <address@hidden>
Date: 2014-02-25 (Tue, 25 Feb 2014)
Changed paths:
M hw/net/opencores_eth.c
M hw/xtensa/xtensa_lx60.c
M target-xtensa/core-dc232b.c
M target-xtensa/core-dc233c.c
M target-xtensa/core-fsf.c
M target-xtensa/cpu.c
M target-xtensa/cpu.h
M target-xtensa/helper.h
M target-xtensa/op_helper.c
M target-xtensa/overlay_tool.h
M target-xtensa/translate.c
M tests/tcg/xtensa/Makefile
M tests/tcg/xtensa/macros.inc
M tests/tcg/xtensa/test_b.S
M tests/tcg/xtensa/test_bi.S
M tests/tcg/xtensa/test_boolean.S
M tests/tcg/xtensa/test_break.S
M tests/tcg/xtensa/test_bz.S
A tests/tcg/xtensa/test_cache.S
M tests/tcg/xtensa/test_clamps.S
M tests/tcg/xtensa/test_extui.S
M tests/tcg/xtensa/test_fail.S
M tests/tcg/xtensa/test_interrupt.S
M tests/tcg/xtensa/test_loop.S
M tests/tcg/xtensa/test_mac16.S
M tests/tcg/xtensa/test_max.S
M tests/tcg/xtensa/test_min.S
M tests/tcg/xtensa/test_mmu.S
M tests/tcg/xtensa/test_mul16.S
M tests/tcg/xtensa/test_mul32.S
M tests/tcg/xtensa/test_nsa.S
M tests/tcg/xtensa/test_pipeline.S
M tests/tcg/xtensa/test_quo.S
M tests/tcg/xtensa/test_rem.S
M tests/tcg/xtensa/test_rst0.S
M tests/tcg/xtensa/test_s32c1i.S
M tests/tcg/xtensa/test_sar.S
M tests/tcg/xtensa/test_sext.S
M tests/tcg/xtensa/test_shift.S
M tests/tcg/xtensa/test_sr.S
M tests/tcg/xtensa/test_timer.S
M tests/tcg/xtensa/test_windowed.S
Log Message:
-----------
Merge remote-tracking branch 'remotes/xtensa/tags/20140224-xtensa' into
staging
Xtensa fixes and improvements queue 2014-02-24:
- add support for ML605 and KC705 FPGA boards;
- flush opencores_eth queue when new RX descriptor is available;
- add basic checks to cache opcodes;
- make core configuration available to tests;
- implement HW config ID special registers.
# gpg: Signature made Mon 24 Feb 2014 00:52:42 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <address@hidden>"
# gpg: aka "Max Filippov <address@hidden>"
* remotes/xtensa/tags/20140224-xtensa:
target-xtensa: provide HW confg ID registers
target-xtensa: refactor standard core configuration
target-xtensa: add basic tests for cache opcodes
target-xtensa: allow using core configuration in tests
target-xtensa: add overridable test_init macro
target-xtensa: add basic checks to icache opcodes
target-xtensa: add basic checks to dcache opcodes
target-xtensa: add RRRI4 opcode format fields
opencores_eth: flush queue whenever can_receive can go from false to true
hw/xtensa: add support for ML605 and KC705 FPGA board
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/e7a1d6c52a3a...05fd3bf2a1c9
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