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[Qemu-commits] [qemu/qemu] 873169: hw/intc/arm_gic: Fix NVIC assertion f


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 873169: hw/intc/arm_gic: Fix NVIC assertion failure
Date: Fri, 21 Feb 2014 08:00:06 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 873169022aa58daabd10979002f8009c7e5f3f05
      
https://github.com/qemu/qemu/commit/873169022aa58daabd10979002f8009c7e5f3f05
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  hw/intc/arm_gic: Fix NVIC assertion failure

Commit 40d225009ef accidentally changed the behaviour of
gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,
so this meant we hit an assertion:
  gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed.

Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>


  Commit: f5e51e7f10d6dbbeac268a7defc89831c62eff12
      
https://github.com/qemu/qemu/commit/f5e51e7f10d6dbbeac268a7defc89831c62eff12
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement plain vector SIMD indexed element insns

Implement all the SIMD vector x indexed element instructions
in the subcategory which are not 'long' ops.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: c44ad1fddcf5a3deea3fb5cc340935bb11ccfb8e
      
https://github.com/qemu/qemu/commit/c44ad1fddcf5a3deea3fb5cc340935bb11ccfb8e
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement long vector x indexed insns

Implement the 'long' operations in the vector x indexed
element category.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 9f82e0ff4b21b3fce86115597e92b01fba448635
      
https://github.com/qemu/qemu/commit/9f82e0ff4b21b3fce86115597e92b01fba448635
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement SIMD scalar indexed instructions

Implement the SIMD scalar indexed instructions. The encoding
here is nearly identical to the vector indexed grouping, so
we combine the two.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: b033cd3d0021bee24931d0118fbd34e8c8d8b5af
      
https://github.com/qemu/qemu/commit/b033cd3d0021bee24931d0118fbd34e8c8d8b5af
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement scalar three different instructions

Implement the scalar three different instruction group:
it only has three instructions in it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 8908f4d1850dbfd0de442e8deaed2f41821cdb89
      
https://github.com/qemu/qemu/commit/8908f4d1850dbfd0de442e8deaed2f41821cdb89
  Author: Alex Bennée <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement SIMD FP compare and set insns

This adds all forms of the SIMD floating point and set instructions:

  FCM(GT|GE|EQ|LE|LT)

Most of the heavy lifting is done by either the existing neon helpers or
some new helpers for the 64bit double cases. Most of the code paths are
common although the 2misc versions are a little special as they compare
against zero.

Signed-off-by: Alex Bennée <address@hidden>
[PMM: fixed some minor bugs, added the 2-misc-scalar encoding]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: bc242f9bb6324a50e7572c0997904b66b630f73a
      
https://github.com/qemu/qemu/commit/bc242f9bb6324a50e7572c0997904b66b630f73a
  Author: Alex Bennée <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement floating point pairwise insns

Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the call tree, so we can also call it from
the floating-point section of the decoder.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 67d43538aee10b6cfe8f3606c69187a3e142a2ba
      
https://github.com/qemu/qemu/commit/67d43538aee10b6cfe8f3606c69187a3e142a2ba
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M fpu/softfloat.c
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: Support halving the result of muladd operation

The ARMv8 instruction set includes a fused floating point
reciprocal square root step instruction which demands an
"(x * y + z) / 2" fused operation. Support this by adding
a flag to the softfloat muladd operations which requests
that the result is halved before rounding.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 057d5f62f822c4789ca0af9c9e9b42322679c793
      
https://github.com/qemu/qemu/commit/057d5f62f822c4789ca0af9c9e9b42322679c793
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/helper.h
    M target-arm/neon_helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement remaining 3-same instructions

Implement the remaining instructions in the SIMD 3-reg-same
and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,
FACGT, FMLA and FMLS.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 83e9a4aec9ffcbcb86ca9d39d2c5aae8176411fb
      
https://github.com/qemu/qemu/commit/83e9a4aec9ffcbcb86ca9d39d2c5aae8176411fb
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/kvm-consts.h

  Log Message:
  -----------
  target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs

Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*
constant to include all the ones currently supported by the kernel
headers we are using.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 76e3e1bcaefe0da394f328854cb72f9449f23732
      
https://github.com/qemu/qemu/commit/76e3e1bcaefe0da394f328854cb72f9449f23732
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Define names for SCTLR bits

The SCTLR is full of bits for enabling or disabling various things, and so
there are many places in the code which check if certain bits are set.
Define some named constants for the SCTLR bits so these checks are easier
to read.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 99f678a679857d83b9709127b0f047551d7e3c45
      
https://github.com/qemu/qemu/commit/99f678a679857d83b9709127b0f047551d7e3c45
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Restrict check_ap() use of S and R bits to v6 and earlier

The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 1456364ff0900893f81f8d06fb1b42e5c2ad8a23
      
https://github.com/qemu/qemu/commit/1456364ff0900893f81f8d06fb1b42e5c2ad8a23
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: Remove unused ARMCPUState sr substruct

Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 626187d86b037c89367f2f94785717b75e0e4440
      
https://github.com/qemu/qemu/commit/626187d86b037c89367f2f94785717b75e0e4440
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Log bad system register accesses with LOG_UNIMP

Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: e508a92b621c7160122e99d3754e568f2b8e255e
      
https://github.com/qemu/qemu/commit/e508a92b621c7160122e99d3754e568f2b8e255e
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Stop underdecoding ARM946 PRBS registers

The ARM946 has 8 PRBS (protection region base and size) registers.
Currently we implement these with a CP_ANY reginfo; however this
underdecodes (since there are 16 possible values of CRm but only
8 registers) and we catch the invalid values in the read and
write functions. However this causes issues with migration since
we only migrate the first of a wildcard register set, so we only
migrate c6_region[0]. It also makes it awkward to pull reginfo
access checks out into their own function.

Avoid all these problems by just defining separate reginfo structs
for each of the 8 registers; this also lets us avoid having any
read or write functions and will result in more efficient direct
field accesses from generated code.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: f59df3f2354982ee0381b87d1ce561f1eb0ed505
      
https://github.com/qemu/qemu/commit/f59df3f2354982ee0381b87d1ce561f1eb0ed505
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.h
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Split cpreg access checks out from read/write functions

Several of the system registers handled via the ARMCPRegInfo
mechanism have access trap control bits controlling whether the
registers are accessible to lower privilege levels. Replace
the existing mechanism (allowing the read and write functions
to return EXCP_UDEF if access is denied) with a dedicated
"check access rights" function pointer in the ARMCPRegInfo.
This will allow us to simplify some of the register definitions,
which no longer need read/write functions purely to handle
the access checks.

We take the opportunity to define the return value from the
access checking function in a way that allows us to set the
correct exception syndrome information for exceptions taken
to AArch64 (which may need to distinguish access failures due
to a configurable trap or enable from other kinds of access
failure).

This commit defines the new mechanism but does not move any
of the registers across to use it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: fcd252062a018380e9ce14ed4d71f6d557018e2b
      
https://github.com/qemu/qemu/commit/fcd252062a018380e9ce14ed4d71f6d557018e2b
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Convert performance monitor reginfo to accessfn

Convert the performance monitor reginfo definitions to use
an accessfn rather than returning EXCP_UDEF from read and
write functions. This also allows us to fix a couple of XXX
cases where we weren't imposing the access restrictions on
RAZ/WI or constant registers.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 00108f2d4d86f41694bafe173271528f7e69b0b7
      
https://github.com/qemu/qemu/commit/00108f2d4d86f41694bafe173271528f7e69b0b7
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Convert generic timer reginfo to accessfn

Convert the reginfo structs for the generic timer registers
to use access functions rather than returning EXCP_UDEF from
their read handlers. In some cases this allows us to remove
a read handler completely.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 92611c0019c38c860e6926dd2073c4448c382859
      
https://github.com/qemu/qemu/commit/92611c0019c38c860e6926dd2073c4448c382859
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Convert miscellaneous reginfo structs to accessfn

Convert the remaining miscellaneous cases of reginfo read/write
functions returning EXCP_UDEF to use an accessfn instead:
TEEHBR, and the ATS address-translation operations.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4241c7d381086819131fba4fc8123848d83de8a
      
https://github.com/qemu/qemu/commit/c4241c7d381086819131fba4fc8123848d83de8a
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M hw/arm/pxa2xx.c
    M hw/arm/pxa2xx_pic.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/op_helper.c

  Log Message:
  -----------
  target-arm: Drop success/fail return from cpreg read and write functions

All cpreg read and write functions now return 0, so we can clean up
their prototypes:
 * write functions return void
 * read functions return the value rather than taking a pointer
   to write the value to

This is a fairly mechanical change which makes only the bare
minimum set of changes to the callers of read and write functions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: ea4571eb8768c39bf6cacd64fdcb6ef405b18b18
      
https://github.com/qemu/qemu/commit/ea4571eb8768c39bf6cacd64fdcb6ef405b18b18
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Remove unnecessary code now read/write fns can't fail

Now that cpreg read and write functions can't fail and throw an
exception, we can remove the code from the translator that synchronises
the guest PC in case an exception is thrown.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 59a1c327d72683e80fa1b886d42a3a5c17729484
      
https://github.com/qemu/qemu/commit/59a1c327d72683e80fa1b886d42a3a5c17729484
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Remove failure status return from read/write_raw_cp_reg

The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns void and the
read function returns the value read, which in turn lets us
simplify the callers.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 7900e9f1f963184967594f4518c97ea682a9605f
      
https://github.com/qemu/qemu/commit/7900e9f1f963184967594f4518c97ea682a9605f
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Fix incorrect type for value argument to write_raw_cp_reg

The write_raw_cp_reg's value argument should be a uint64_t, since
that's what all its callers hand it and what all the functions it
calls take. A (harmless) typo meant we were accidentally declaring
it as int64_t.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: d324b36ad93b84509aeee41f05ee17a6c5de7826
      
https://github.com/qemu/qemu/commit/d324b36ad93b84509aeee41f05ee17a6c5de7826
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement store-exclusive for system mode

System mode store-exclusive use a different code path to usermode ones;
implement this missing code, in a similar way to the 32 bit version.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 13caf1fd2bdc4d8799098d73001caf7d8924073e
      
https://github.com/qemu/qemu/commit/13caf1fd2bdc4d8799098d73001caf7d8924073e
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add opcode comments to disas_simd_three_reg_diff

The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 70d7f984a0a9e03c1327487aed9877a4eca0e709
      
https://github.com/qemu/qemu/commit/70d7f984a0a9e03c1327487aed9877a4eca0e709
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add most remaining three-reg-diff widening ops

Add the remainder of the 64x64->128 operations in the three-reg-diff
category except for PMULL, PMULL2.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: dfc15c7cebaa467de7ada96d2688d4f5f4d3e532
      
https://github.com/qemu/qemu/commit/dfc15c7cebaa467de7ada96d2688d4f5f4d3e532
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement the wide 3-reg-different operations

Implement the wide three-reg-different operations:
SADDW, UADDW, SSUBW and USUBW.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e4b998d47df70450f5aafc0fd7b3d56fa4920369
      
https://github.com/qemu/qemu/commit/e4b998d47df70450f5aafc0fd7b3d56fa4920369
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement narrowing three-reg-diff operations

Implement the narrowing three-reg-diff operations: ADDHN,
RADDHN, SUBHN and RSUBHN.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 60510aed69f69bfd44bf6e58c571dbba8b1b43a0
      
https://github.com/qemu/qemu/commit/60510aed69f69bfd44bf6e58c571dbba8b1b43a0
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Implement unprivileged load/store

Implement the unprivileged load and store instructions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 2ea5a2ca1f1dc302652d2ad5035e0b209ccaa177
      
https://github.com/qemu/qemu/commit/2ea5a2ca1f1dc302652d2ad5035e0b209ccaa177
  Author: Janne Grunau <address@hidden>
  Date:   2014-02-20 (Thu, 20 Feb 2014)

  Changed paths:
    M linux-user/main.c

  Log Message:
  -----------
  linux-user: AArch64: Fix exclusive store of the zero register

Signed-off-by: Janne Grunau <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 105a060188dc6fdd4551571a966514d1a5f6815a
      
https://github.com/qemu/qemu/commit/105a060188dc6fdd4551571a966514d1a5f6815a
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-21 (Fri, 21 Feb 2014)

  Changed paths:
    M fpu/softfloat.c
    M hw/arm/pxa2xx.c
    M hw/arm/pxa2xx_pic.c
    M hw/intc/arm_gic.c
    M include/fpu/softfloat.h
    M linux-user/main.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/kvm-consts.h
    M target-arm/neon_helper.c
    M target-arm/op_helper.c
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140220' 
into staging

target-arm queue:
 * Fix a bug causing an assertion in the NVIC on ARMv7M models
 * More A64 Neon instructions
 * Refactor cpreg API to separate out access check functions, as
   groundwork for AArch64 system mode
 * Fix bug in linux-user A64 store-exclusive of XZR

# gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits)
  linux-user: AArch64: Fix exclusive store of the zero register
  target-arm: A64: Implement unprivileged load/store
  target-arm: A64: Implement narrowing three-reg-diff operations
  target-arm: A64: Implement the wide 3-reg-different operations
  target-arm: A64: Add most remaining three-reg-diff widening ops
  target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
  target-arm: A64: Implement store-exclusive for system mode
  target-arm: Fix incorrect type for value argument to write_raw_cp_reg
  target-arm: Remove failure status return from read/write_raw_cp_reg
  target-arm: Remove unnecessary code now read/write fns can't fail
  target-arm: Drop success/fail return from cpreg read and write functions
  target-arm: Convert miscellaneous reginfo structs to accessfn
  target-arm: Convert generic timer reginfo to accessfn
  target-arm: Convert performance monitor reginfo to accessfn
  target-arm: Split cpreg access checks out from read/write functions
  target-arm: Stop underdecoding ARM946 PRBS registers
  target-arm: Log bad system register accesses with LOG_UNIMP
  target-arm: Remove unused ARMCPUState sr substruct
  target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
  target-arm: Define names for SCTLR bits
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3e890c77cf03...105a060188dc

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