[Qemu-commits] [qemu/qemu] e52752: target-mips: add CPU definition for MIPS32R5

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e527526d355570615533d38236818c759f29d889
      
https://github.com/qemu/qemu/commit/e527526d355570615533d38236818c759f29d889
  Author: Petar Jovanovic <address@hidden>
  Date:   2014-02-10 (Mon, 10 Feb 2014)

  Changed paths:
    M target-mips/mips-defs.h
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add CPU definition for MIPS32R5

Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.

Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>


  Commit: b4160af160ba045e3a25013b4def4a39f09cbb78
      
https://github.com/qemu/qemu/commit/b4160af160ba045e3a25013b4def4a39f09cbb78
  Author: Petar Jovanovic <address@hidden>
  Date:   2014-02-10 (Mon, 10 Feb 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add support for CP0_Config4

Add CP0_Config4, define rw_bitmask.

Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>


  Commit: b4dd99a3636f5a3044dfd9dba7653ca377a9aeba
      
https://github.com/qemu/qemu/commit/b4dd99a3636f5a3044dfd9dba7653ca377a9aeba
  Author: Petar Jovanovic <address@hidden>
  Date:   2014-02-10 (Mon, 10 Feb 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add support for CP0_Config5

Add CP0_Config5, define rw_bitmask and enable modifications.

Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>


  Commit: 736d120af4bf5f3e13b2f90c464b3a24847f78f0
      
https://github.com/qemu/qemu/commit/736d120af4bf5f3e13b2f90c464b3a24847f78f0
  Author: Petar Jovanovic <address@hidden>
  Date:   2014-02-10 (Mon, 10 Feb 2014)

  Changed paths:
    M target-mips/helper.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  target-mips: add user-mode FR switch support for MIPS32r5

Description of UFR feature:

Required in MIPS32r5 if floating point is implemented and user-mode FR
switching is supported. The UFR register allows user-mode to clear StatusFR
by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by
executing a CFC1 to UFR.

helper_ctc1 has been extended with an additional parameter rt to check
requirements for UFR feature.
Definition of mips32r5-generic has been modified to include support for UFR.

Signed-off-by: Petar Jovanovic <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>


  Commit: 5631e69c269c6b832837715a3bd4d685120a2713
      
https://github.com/qemu/qemu/commit/5631e69c269c6b832837715a3bd4d685120a2713
  Author: Richard Henderson <address@hidden>
  Date:   2014-02-11 (Tue, 11 Feb 2014)

  Changed paths:
    M target-openrisc/translate.c

  Log Message:
  -----------
  target-openrisc: Use new qemu_ld/st opcodes

Signed-off-by: Richard Henderson <address@hidden>
Acked-by: Jia Liu <address@hidden>
Signed-off-by: Jia Liu <address@hidden>


  Commit: a50f98b0665289fd37720f287943e86f23b01f45
      
https://github.com/qemu/qemu/commit/a50f98b0665289fd37720f287943e86f23b01f45
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-15 (Sat, 15 Feb 2014)

  Changed paths:
    M target-mips/cpu.h
    M target-mips/helper.h
    M target-mips/mips-defs.h
    M target-mips/op_helper.c
    M target-mips/translate.c
    M target-mips/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/jovanovic/mips-ufrp' into staging

* remotes/jovanovic/mips-ufrp:
  target-mips: add user-mode FR switch support for MIPS32r5
  target-mips: add support for CP0_Config5
  target-mips: add support for CP0_Config4
  target-mips: add CPU definition for MIPS32R5

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 90ce3d76eb917d25ecec4d3cb9ad8da7576a1505
      
https://github.com/qemu/qemu/commit/90ce3d76eb917d25ecec4d3cb9ad8da7576a1505
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-15 (Sat, 15 Feb 2014)

  Changed paths:
    M target-openrisc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/jliu/or32-ld-st' into staging

* remotes/jliu/or32-ld-st:
  target-openrisc: Use new qemu_ld/st opcodes

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/933b19ea9784...90ce3d76eb91