[Qemu-commits] [qemu/qemu] 69252c: object_add: consolidate error handlin

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[Qemu-commits] [qemu/qemu] 69252c: object_add: consolidate error handlin

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 69252c: object_add: consolidate error handling
Date:	Sat, 01 Feb 2014 16:00:05 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 69252c046741a0955ddb90250f416a2199305091
      
https://github.com/qemu/qemu/commit/69252c046741a0955ddb90250f416a2199305091
  Author: Igor Mammedov <address@hidden>
  Date:   2014-01-28 (Tue, 28 Jan 2014)

  Changed paths:
    M qmp.c

  Log Message:
  -----------
  object_add: consolidate error handling

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Luiz Capitulino <address@hidden>


  Commit: 90e9cf28e57a3e1d6caa0a28b0a332ff982ccb0b
      
https://github.com/qemu/qemu/commit/90e9cf28e57a3e1d6caa0a28b0a332ff982ccb0b
  Author: Igor Mammedov <address@hidden>
  Date:   2014-01-28 (Tue, 28 Jan 2014)

  Changed paths:
    M vl.c

  Log Message:
  -----------
  vl.c: -object: don't ignore duplicate 'id'

object_property_add_child() may fail if 'id' matches
an already existing object. Which means an incorrect
command line.
So instead of silently ignoring error, report it and
terminate QEMU.

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Luiz Capitulino <address@hidden>


  Commit: 269e09f3fc922b800d118d9c8a721be46b5462a3
      
https://github.com/qemu/qemu/commit/269e09f3fc922b800d118d9c8a721be46b5462a3
  Author: Igor Mammedov <address@hidden>
  Date:   2014-01-28 (Tue, 28 Jan 2014)

  Changed paths:
    M backends/rng.c
    A include/qom/object_interfaces.h
    M qmp.c
    M qom/Makefile.objs
    A qom/object_interfaces.c
    M vl.c

  Log Message:
  -----------
  add optional 2nd stage initialization to -object/object-add commands

Introduces USER_CREATABLE interface that must be implemented by
objects which are designed to created with -object CLI option or
object-add QMP command.

Interface provides an ability to do an optional second stage
initialization of the object created with -object/object-add
commands. By providing complete() callback, which is called
after the object properties were set.

It allows to:
 * prevents misusing of -object/object-add by filtering out
   objects that are not designed for it.
 * generalize second stage backend initialization instead of
   adding custom APIs to perform it
 * early error detection of backend initialization at -object/
   object-add time rather than through a proxy DEVICE object
   that tries to use backend.

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Luiz Capitulino <address@hidden>


  Commit: 57d3e1b3f52d07d215ed96df946ee01f8d9f9526
      
https://github.com/qemu/qemu/commit/57d3e1b3f52d07d215ed96df946ee01f8d9f9526
  Author: Igor Mammedov <address@hidden>
  Date:   2014-01-28 (Tue, 28 Jan 2014)

  Changed paths:
    M backends/rng.c
    M hw/virtio/virtio-rng.c
    M include/sysemu/rng.h

  Log Message:
  -----------
  virtio_rng: replace custom backend API with UserCreatable.complete() callback

in addition fix default backend leak by releasing it if its
initialization failed.

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Luiz Capitulino <address@hidden>


  Commit: 056f49ff2cf645dc484956b00b65a3aa18a1a9a3
      
https://github.com/qemu/qemu/commit/056f49ff2cf645dc484956b00b65a3aa18a1a9a3
  Author: Stratos Psomadakis <address@hidden>
  Date:   2014-01-28 (Tue, 28 Jan 2014)

  Changed paths:
    M monitor.c

  Log Message:
  -----------
  monitor: Cleanup mon->outbuf on write error

In case monitor_flush() fails to write the contents of mon->outbuf to
the output device, mon->outbuf is not cleaned up properly. Check the
return code of the qemu_chr_fe_write() function and cleanup the outbuf
if it fails.

References: 
http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02890.html

Signed-off-by: Stratos Psomadakis <address@hidden>
Signed-off-by: Dimitris Aragiorgis <address@hidden>
Signed-off-by: Luiz Capitulino <address@hidden>


  Commit: 72430bf5eb7f7309e705705af9798d13aa94e80d
      
https://github.com/qemu/qemu/commit/72430bf5eb7f7309e705705af9798d13aa94e80d
  Author: Alex Bennée <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD ld/st multiple

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:

  * do_vec_get - fetch value from a slice of a vector register
  * do_vec_set - set a slice of a vector register

which use vec_reg_offset for consistent processing of offsets in an
endian aware manner. There are also additional helpers:

  * do_vec_ld - load value into SIMD
  * do_vec_st - store value from SIMD

which load or store a slice of a vector register to memory.
These don't zero extend like the fp variants.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: df54e47d2b86c636b4d22f663dbffce6a3cffd81
      
https://github.com/qemu/qemu/commit/df54e47d2b86c636b4d22f663dbffce6a3cffd81
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD ld/st single

Implement the SIMD ld/st single structure instructions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 384b26fb06f72e822730d3b8f51fd71a5fec5eee
      
https://github.com/qemu/qemu/commit/384b26fb06f72e822730d3b8f51fd71a5fec5eee
  Author: Alex Bennée <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add decode skeleton for SIMD data processing insns

Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very
quickly, so we use a simple data-driven pattern-and-mask approach.

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 5c73747f3cc29471f9fbfe630ef15902e65f53b3
      
https://github.com/qemu/qemu/commit/5c73747f3cc29471f9fbfe630ef15902e65f53b3
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD EXT

Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 7c51048fa918f64806adf0f76166e9940d772eb1
      
https://github.com/qemu/qemu/commit/7c51048fa918f64806adf0f76166e9940d772eb1
  Author: Michael Matz <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD TBL/TBLX

Add support for the SIMD TBL/TBLX instructions (group C3.6.2).

Signed-off-by: Michael Matz <address@hidden>
[PMM: rewritten to do more of the decode in translate-a64.c,
 and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 5fa5469c08f6e51eed26d6d54e0be8682723d3df
      
https://github.com/qemu/qemu/commit/5fa5469c08f6e51eed26d6d54e0be8682723d3df
  Author: Michael Matz <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD ZIP/UZP/TRN

Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).

Signed-off-by: Michael Matz <address@hidden>
[PMM: use new do_vec_get/set etc functions and generally update to new
 codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 4a0ff1ce73a9e06ecb655019820229de74244432
      
https://github.com/qemu/qemu/commit/4a0ff1ce73a9e06ecb655019820229de74244432
  Author: Michael Matz <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD across-lanes instructions

Add support for the SIMD "across lanes" instruction group (C3.6.4).

Signed-off-by: Michael Matz <address@hidden>
[PMM: Updated to current codebase, added fp min/max ops,
 added unallocated encoding checks]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 67bb93890d7b435f294f1e47ee7adc5662cc0842
      
https://github.com/qemu/qemu/commit/67bb93890d7b435f294f1e47ee7adc5662cc0842
  Author: Alex Bennée <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD copy operations

This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: f3f8c4f4d2fc7dda192393f998e63c7a83fb7554
      
https://github.com/qemu/qemu/commit/f3f8c4f4d2fc7dda192393f998e63c7a83fb7554
  Author: Alex Bennée <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD modified immediate group

This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf <address@hidden>
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 360a6f2dbde39211107620a3d38b8cc8cc5281ee
      
https://github.com/qemu/qemu/commit/360a6f2dbde39211107620a3d38b8cc8cc5281ee
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD scalar copy instructions

Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 83bfffec72ad447dfc80a4eab320403175ffe4e3
      
https://github.com/qemu/qemu/commit/83bfffec72ad447dfc80a4eab320403175ffe4e3
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting

The code which decides whether to set up the ATAGS data structure on
reset was using the wrong conditional, which meant we were creating
an ATAGS structure when doing a device-tree boot if the dtb was
autogenerated by the board. This is harmless, but unnecessary, so
bring it in to line with user-provided-dtb boots.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden


  Commit: 51a9b04bd3b01e11a1db4fc2ac2f1d324fbd30aa
      
https://github.com/qemu/qemu/commit/51a9b04bd3b01e11a1db4fc2ac2f1d324fbd30aa
  Author: Alistair Francis <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  ARM: Convert MIDR to a property

Convert the MIDR register to a property. This allows boards to later set
a custom MIDR value. This has been done in such a way to maintain
compatibility with all existing CPUs and boards

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b48adc0d301464d627d6d0f83dee911a2138187f
      
https://github.com/qemu/qemu/commit/b48adc0d301464d627d6d0f83dee911a2138187f
  Author: Alistair Francis <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  ZYNQ: Implement board MIDR control for Zynq

This patch uses the fact that the midr variable is now a property
This patch sets the midr variable to the boards custom midr

Signed-off-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2cdaca90ddf3291f308a10623c1a802ef760bac1
      
https://github.com/qemu/qemu/commit/2cdaca90ddf3291f308a10623c1a802ef760bac1
  Author: Paolo Bonzini <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M hw/display/blizzard_template.h
    M hw/display/pl110_template.h
    M hw/display/pxa2xx_template.h
    M hw/display/tc6393xb_template.h

  Log Message:
  -----------
  display: avoid multi-statement macro

For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xx
Coverity noticed that it is used inside an "if" statement.
Fix it because it's the file with the highest number of defects
in the whole QEMU tree!  Use "do...while (0)", or just remove the
semicolon if there's a single statement in the macro.

Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9972da669fd3d3e3423d2bf6cb2c11fa9239f862
      
https://github.com/qemu/qemu/commit/9972da669fd3d3e3423d2bf6cb2c11fa9239f862
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/cpu.h
    M target-arm/helper.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Move arm_rmode_to_sf to a shared location.

This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.

Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7655f39bde5de92b4a3c154a5a8735476c34f458
      
https://github.com/qemu/qemu/commit/7655f39bde5de92b4a3c154a5a8735476c34f458
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM

Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 664c6733d72c589cd9f6ccee305e7b7ce36ea06d
      
https://github.com/qemu/qemu/commit/664c6733d72c589cd9f6ccee305e7b7ce36ea06d
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 FP VRINTR

Add support for the AArch32 floating-point VRINTR instruction.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a290c62a7521a5695e12bb9022f8b953c2f50f54
      
https://github.com/qemu/qemu/commit/a290c62a7521a5695e12bb9022f8b953c2f50f54
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 FP VRINTZ

Add support for the AArch32 floating-point VRINTZ instruction.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4e82bc01ecc46e90346f731065528b1d47971eba
      
https://github.com/qemu/qemu/commit/4e82bc01ecc46e90346f731065528b1d47971eba
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 FP VRINTX

Add support for the AArch32 floating-point VRINTX instruction.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2ce7062501c715aae0ad37c3923a3710dd8914df
      
https://github.com/qemu/qemu/commit/2ce7062501c715aae0ad37c3923a3710dd8914df
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add support for AArch32 SIMD VRINTX

Add support for the AArch32 Advanced SIMD VRINTX instruction.

Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 43630e585300465b72ecf328822c8611724307de
      
https://github.com/qemu/qemu/commit/43630e585300465b72ecf328822c8611724307de
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/helper.c
    M target-arm/helper.h

  Log Message:
  -----------
  target-arm: Add set_neon_rmode helper

This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.

Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 34f7b0a276ed2679c5e420ed1bc6525689ac5abd
      
https://github.com/qemu/qemu/commit/34f7b0a276ed2679c5e420ed1bc6525689ac5abd
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ

Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c9975a838736c9479b2e17fff7e50a2a83b1009e
      
https://github.com/qemu/qemu/commit/c9975a838736c9479b2e17fff7e50a2a83b1009e
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 901ad5259fab785537f8c6b3713fce85d2ebceb1
      
https://github.com/qemu/qemu/commit/901ad5259fab785537f8c6b3713fce85d2ebceb1
  Author: Will Newton <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a08582f41e94b5a7ee3e53ad1e719d24431aa675
      
https://github.com/qemu/qemu/commit/a08582f41e94b5a7ee3e53ad1e719d24431aa675
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD three-different multiply accumulate insns

Add support for the multiply-accumulate instructions from the
SIMD three-different instructions group (C3.6.15):
 * skeleton decode of unallocated encodings and split of
   the group into its three sub-parts
 * framework for handling the 64x64->128 widening subpart
 * implementation of the multiply-accumulate instructions
   SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2,
   UMULL, UMULL2, SMULL, SMULL2

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 0ae39320bd0783f1a1d4ac63ec9ba48ca41764dc
      
https://github.com/qemu/qemu/commit/0ae39320bd0783f1a1d4ac63ec9ba48ca41764dc
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD three-different ABDL instructions

Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: b305dba6cf2957bc67aa6072978c65026ce478fb
      
https://github.com/qemu/qemu/commit/b305dba6cf2957bc67aa6072978c65026ce478fb
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops

Implement the add, sub and compare ops from the SIMD "scalar three same"
group.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e1cea1144aff6498ddbcd60e2bff4172869b10d4
      
https://github.com/qemu/qemu/commit/e1cea1144aff6498ddbcd60e2bff4172869b10d4
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add top level decode for SIMD 3-same group

Add top level decode for the A64 SIMD three regs same group
(C3.6.16), splitting it into the pairwise, logical, float and
integer subgroups.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 956d272eb2996e4d95f8a674256f8a63a0c1e8d4
      
https://github.com/qemu/qemu/commit/956d272eb2996e4d95f8a674256f8a63a0c1e8d4
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add logic ops from SIMD 3 same group

Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,
BIT and BIF) from the SIMD 3 register same group (C3.6.16).

Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 1f8a73af12ddfb9cf9a90261338b466b7dbf7ab9
      
https://github.com/qemu/qemu/commit/1f8a73af12ddfb9cf9a90261338b466b7dbf7ab9
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add integer ops from SIMD 3-same group

Add some of the integer operations in the SIMD 3-same group:
specifically, the comparisons, addition and subtraction.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 845ea09acc4b5ab8335530aaaf94531c368ba934
      
https://github.com/qemu/qemu/commit/845ea09acc4b5ab8335530aaaf94531c368ba934
  Author: Peter Maydell <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add simple SIMD 3-same floating point ops

Implement a simple subset of the SIMD 3-same floating point
operations. This includes a common helper function used for both
scalar and vector ops; FABD is the only currently implemented
shared op.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 4d1cef840d526c80244175c208260f165f9226db
      
https://github.com/qemu/qemu/commit/4d1cef840d526c80244175c208260f165f9226db
  Author: Alex Bennée <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: Add SIMD shift by immediate

This implements a subset of the AdvSIMD shift operations (namely all the
none saturating or narrowing ones). The actual shift generation code
itself is common for both the scalar and vector cases but wrapped with
either vector element iteration or the fp reg access.

The rounding operations need to take special care to correctly reflect
the result of adding rounding bits on high bits as the intermediates do
not truncate.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 41ab7b55108e2699e7c2e77788465cb52a0b2c08
      
https://github.com/qemu/qemu/commit/41ab7b55108e2699e7c2e77788465cb52a0b2c08
  Author: Christoffer Dall <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M hw/intc/arm_gic.c
    M include/hw/intc/arm_gic_common.h

  Log Message:
  -----------
  arm_gic: Introduce define for GIC_NR_SGIS

Instead of hardcoding 16 various places in the code, use a define to
make it more clear what is going on.

Signed-off-by: Christoffer Dall <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5b0adce156216fb24dcc5f1683e8b686f3793fff
      
https://github.com/qemu/qemu/commit/5b0adce156216fb24dcc5f1683e8b686f3793fff
  Author: Christoffer Dall <address@hidden>
  Date:   2014-01-31 (Fri, 31 Jan 2014)

  Changed paths:
    M hw/intc/arm_gic.c

  Log Message:
  -----------
  arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes

Fix two bugs that would allow changing the state of SGIs through the
ICPENDR and ISPENDRs.

Signed-off-by: Christoffer Dall <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b4a8c9ae9758efb6873097f415e9972127ccf418
      
https://github.com/qemu/qemu/commit/b4a8c9ae9758efb6873097f415e9972127ccf418
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-01 (Sat, 01 Feb 2014)

  Changed paths:
    M hw/arm/boot.c
    M hw/arm/xilinx_zynq.c
    M hw/display/blizzard_template.h
    M hw/display/pl110_template.h
    M hw/display/pxa2xx_template.h
    M hw/display/tc6393xb_template.h
    M hw/intc/arm_gic.c
    M include/hw/intc/arm_gic_common.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/translate-a64.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into 
staging

target-arm queue:
 * implementation of first part of the A64 Neon instruction set
 * v8 AArch32 rounding and 16<->64 fp conversion instructions
 * fix MIDR value on Zynq boards
 * some minor bugfixes/code cleanups

# gpg: Signature made Fri 31 Jan 2014 15:06:34 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"

* pmaydell/tags/pull-target-arm-20140131: (34 commits)
  arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
  arm_gic: Introduce define for GIC_NR_SGIS
  target-arm: A64: Add SIMD shift by immediate
  target-arm: A64: Add simple SIMD 3-same floating point ops
  target-arm: A64: Add integer ops from SIMD 3-same group
  target-arm: A64: Add logic ops from SIMD 3 same group
  target-arm: A64: Add top level decode for SIMD 3-same group
  target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
  target-arm: A64: Add SIMD three-different ABDL instructions
  target-arm: A64: Add SIMD three-different multiply accumulate insns
  target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
  target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
  target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
  target-arm: Add set_neon_rmode helper
  target-arm: Add support for AArch32 SIMD VRINTX
  target-arm: Add support for AArch32 FP VRINTX
  target-arm: Add support for AArch32 FP VRINTZ
  target-arm: Add support for AArch32 FP VRINTR
  target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
  target-arm: Move arm_rmode_to_sf to a shared location.
  ...

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2f61120c10da9128357510debc8e66880cd2bfdc
      
https://github.com/qemu/qemu/commit/2f61120c10da9128357510debc8e66880cd2bfdc
  Author: Peter Maydell <address@hidden>
  Date:   2014-02-01 (Sat, 01 Feb 2014)

  Changed paths:
    M backends/rng.c
    M hw/virtio/virtio-rng.c
    A include/qom/object_interfaces.h
    M include/sysemu/rng.h
    M monitor.c
    M qmp.c
    M qom/Makefile.objs
    A qom/object_interfaces.c
    M vl.c

  Log Message:
  -----------
  Merge remote-tracking branch 'qmp-unstable/queue/qmp' into staging

* qmp-unstable/queue/qmp:
  monitor: Cleanup mon->outbuf on write error
  virtio_rng: replace custom backend API with UserCreatable.complete() callback
  add optional 2nd stage initialization to -object/object-add commands
  vl.c: -object: don't ignore duplicate 'id'
  object_add: consolidate error handling

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/850bbe1b9444...2f61120c10da
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