[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] efec3d: qdev: Replace no_user by cannot_insta
|
From: |
GitHub |
|
Subject: |
[Qemu-commits] [qemu/qemu] efec3d: qdev: Replace no_user by cannot_instantiate_with_d... |
|
Date: |
Thu, 09 Jan 2014 12:00:06 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: efec3dd631d94160288392721a5f9c39e50fb2bc
https://github.com/qemu/qemu/commit/efec3dd631d94160288392721a5f9c39e50fb2bc
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/acpi/piix4.c
M hw/alpha/typhoon.c
M hw/arm/versatilepb.c
M hw/audio/pcspk.c
M hw/audio/pl041.c
M hw/block/fdc.c
M hw/display/pl110.c
M hw/dma/pl080.c
M hw/i2c/smbus_ich9.c
M hw/i386/kvm/clock.c
M hw/i386/kvmvapic.c
M hw/i386/pc.c
M hw/ide/piix.c
M hw/ide/via.c
M hw/input/pckbd.c
M hw/input/vmmouse.c
M hw/intc/apic_common.c
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gic_kvm.c
M hw/intc/i8259_common.c
M hw/intc/ioapic_common.c
M hw/intc/pl190.c
M hw/isa/isa-bus.c
M hw/isa/lpc_ich9.c
M hw/isa/piix4.c
M hw/isa/vt82c686.c
M hw/misc/arm_l2x0.c
M hw/misc/vmport.c
M hw/nvram/fw_cfg.c
M hw/pci-host/bonito.c
M hw/pci-host/grackle.c
M hw/pci-host/piix.c
M hw/pci-host/prep.c
M hw/ppc/spapr_vio.c
M hw/s390x/ipl.c
M hw/s390x/s390-virtio-bus.c
M hw/s390x/virtio-ccw.c
M hw/sd/pl181.c
M hw/timer/arm_mptimer.c
M hw/timer/hpet.c
M hw/timer/i8254_common.c
M hw/timer/m48t59.c
M hw/timer/mc146818rtc.c
M hw/timer/pl031.c
M include/hw/qdev-core.h
M qdev-monitor.c
M qom/cpu.c
Log Message:
-----------
qdev: Replace no_user by cannot_instantiate_with_device_add_yet
In an ideal world, machines can be built by wiring devices together
with configuration, not code. Unfortunately, that's not the world we
live in right now. We still have quite a few devices that need to be
wired up by code. If you try to device_add such a device, it'll fail
in sometimes mysterious ways. If you're lucky, you get an
unmysterious immediate crash.
To protect users from such badness, DeviceClass member no_user used to
make device models unavailable with -device / device_add, but that
regressed in commit 18b6dad. The device model is still omitted from
help, but is available anyway.
Attempts to fix the regression have been rejected with the argument
that the purpose of no_user isn't clear, and it's prone to misuse.
This commit clarifies no_user's purpose. Anthony suggested to rename
it cannot_instantiate_with_device_add_yet_due_to_internal_bugs, which
I shorten somewhat to keep checkpatch happy. While there, make it
bool.
Every use of cannot_instantiate_with_device_add_yet gets a FIXME
comment asking for rationale. The next few commits will clean them
all up, either by providing a rationale, or by getting rid of the use.
With that done, the regression fix is hopefully acceptable.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 837d37167dc446af8a91189108b363c04609e296
https://github.com/qemu/qemu/commit/837d37167dc446af8a91189108b363c04609e296
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/alpha/typhoon.c
M hw/arm/versatilepb.c
M hw/audio/pl041.c
M hw/core/sysbus.c
M hw/display/pl110.c
M hw/dma/pl080.c
M hw/i386/kvm/clock.c
M hw/i386/kvmvapic.c
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gic_kvm.c
M hw/intc/ioapic_common.c
M hw/intc/pl190.c
M hw/isa/isa-bus.c
M hw/misc/arm_l2x0.c
M hw/nvram/fw_cfg.c
M hw/pci-host/bonito.c
M hw/pci-host/grackle.c
M hw/pci-host/piix.c
M hw/pci-host/prep.c
M hw/ppc/spapr_vio.c
M hw/s390x/ipl.c
M hw/s390x/s390-virtio-bus.c
M hw/s390x/virtio-ccw.c
M hw/sd/pl181.c
M hw/timer/arm_mptimer.c
M hw/timer/hpet.c
M hw/timer/pl031.c
Log Message:
-----------
sysbus: Set cannot_instantiate_with_device_add_yet
device_add plugs devices into suitable bus. For "real" buses, that
actually connects the device. For sysbus, the connections need to be
made separately, and device_add can't do that. The device would be
left unconnected, and could not possibly work.
Quite a few, but not all sysbus devices already set
cannot_instantiate_with_device_add_yet in their class init function.
Set it in their abstract base's class init function
sysbus_device_class_init(), and remove the now redundant assignments
from device class init functions.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: ffa957148698eec9cfdaf6e0c1b43cda8828cd61
https://github.com/qemu/qemu/commit/ffa957148698eec9cfdaf6e0c1b43cda8828cd61
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M qom/cpu.c
Log Message:
-----------
cpu: Document why cannot_instantiate_with_device_add_yet
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: f37a4374bae20ca678b808b5ee32319e943b1b4b
https://github.com/qemu/qemu/commit/f37a4374bae20ca678b808b5ee32319e943b1b4b
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/intc/apic_common.c
Log Message:
-----------
apic: Document why cannot_instantiate_with_device_add_yet
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 08c58f92f66dcf0a9097c3a6a65bcc4ffd71268f
https://github.com/qemu/qemu/commit/08c58f92f66dcf0a9097c3a6a65bcc4ffd71268f
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/mips/gt64xxx_pci.c
M hw/pci-bridge/dec.c
M hw/pci-host/apb.c
M hw/pci-host/bonito.c
M hw/pci-host/grackle.c
M hw/pci-host/piix.c
M hw/pci-host/ppce500.c
M hw/pci-host/prep.c
M hw/pci-host/q35.c
M hw/pci-host/uninorth.c
M hw/pci-host/versatile.c
M hw/ppc/ppc4xx_pci.c
M hw/sh4/sh_pci.c
Log Message:
-----------
pci-host: Consistently set cannot_instantiate_with_device_add_yet
Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, these bridges should
be modelled as a single, composite devices instead of pairs of
seemingly independent devices you can only use together, but we're not
there, yet.
Since the sysbus part can't be instantiated with device_add, yet,
permitting it with the PCI part is useless. We shouldn't offer
useless options to the user, so let's set
cannot_instantiate_with_device_add_yet for them.
It's already set for Bonito, Grackle, i440FX and Raven. Document why.
Set it for the others: dec-21154, e500-host-bridge, gt64120_pci, mch,
pbm-pci, ppc4xx-host-bridge, sh_pci_host, u3-agp, uni-north-agp,
uni-north-internal-pci, uni-north-pci, and versatile_pci_host.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: bfa6dfd070f0cb5be37ae3bd6b90bdd67849c311
https://github.com/qemu/qemu/commit/bfa6dfd070f0cb5be37ae3bd6b90bdd67849c311
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/i2c/smbus_ich9.c
M hw/isa/lpc_ich9.c
Log Message:
-----------
ich9: Document why cannot_instantiate_with_device_add_yet
An ICH9 southbridge contains several PCI devices, some of them with
multiple functions. We model each function as a separate qdev. Two
of them need some special wiring set up in pc_q35_init() to work: the
LPC controller at 00:1f.0, and the SMBus controller at 00:1f.3.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 81aab2ff1118a4de8fd92ae89380ccfbc2870574
https://github.com/qemu/qemu/commit/81aab2ff1118a4de8fd92ae89380ccfbc2870574
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/acpi/piix4.c
M hw/ide/piix.c
M hw/isa/piix4.c
M hw/pci-host/piix.c
Log Message:
-----------
piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet
A PIIX3/PIIX4 southbridge has multiple functions. We model each
function as a separate qdev. Two of them need some special wiring set
up in pc_init1() or mips_malta_init() to work: the ISA bridge at 01.0,
and the SMBus controller at 01.3.
The IDE controller at 01.1 (piix3-ide, piix3-ide-xen, piix4-ide) has
always had cannot_instantiate_with_device_add_yet set, but there is no
obvious reason why device_add could not work for them. Drop it.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 04916ee9fb8ff4be4d9f612b85aef009ec57b0b4
https://github.com/qemu/qemu/commit/04916ee9fb8ff4be4d9f612b85aef009ec57b0b4
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/ide/via.c
M hw/isa/vt82c686.c
Log Message:
-----------
vt82c686: Clean up use of cannot_instantiate_with_device_add_yet
A VT82C686B southbridge has multiple functions. We model each
function as a separate qdev. One of them need some special wiring set
up in mips_fulong2e_init() to work: the ISA bridge at 05.0.
The IDE controller at 05.1 (via-ide) has always had
cannot_instantiate_with_device_add_yet set, but there is no obvious
reason why device_add could not work for them. Drop it.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: f3b176402fa92149320dcd5479916ccb39cfa0a8
https://github.com/qemu/qemu/commit/f3b176402fa92149320dcd5479916ccb39cfa0a8
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M hw/audio/pcspk.c
M hw/block/fdc.c
M hw/i386/pc.c
M hw/input/pckbd.c
M hw/input/vmmouse.c
M hw/intc/i8259_common.c
M hw/misc/vmport.c
M hw/timer/i8254_common.c
M hw/timer/m48t59.c
M hw/timer/mc146818rtc.c
Log Message:
-----------
isa: Clean up use of cannot_instantiate_with_device_add_yet
Drop it when there's no obvious reason why device_add could not work.
Else keep and document why.
* isa-fdc: drop
* i8042: drop, even though its I/O base is hardcoded (because you
could conceivably still add one to a board that has none), and even
though PC board code wires up the A20 line (because that wiring is
optional)
* port92: keep because it needs additional wiring by port92_init()
* mc146818rtc: keep because it needs to be wired up by rtc_init()
* m48t59_isa: keep because needs to be wired up by m48t59_init_isa()
* isa-pit, kvm-pit: keep (in their abstract base pic-common) because
the PIT needs additional wiring by board code, depending on HPET
presence
* pcspk: keep because of pointer property pit, and because realize
sets global pcspk_state
* vmmouse: keep because of pointer property ps2_mouse
* vmport: keep because realize sets global port_state
* isa-i8259, kvm-i8259: keep (in their abstract base pic-common),
because the PICs' IRQ input lines are set up by board code, and the
wiring of the slave to the master is hard-coded in device model code
Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 7ea5e78f3d8d64e99c4017ea211b7518f2629756
https://github.com/qemu/qemu/commit/7ea5e78f3d8d64e99c4017ea211b7518f2629756
Author: Markus Armbruster <address@hidden>
Date: 2013-12-22 (Sun, 22 Dec 2013)
Changed paths:
M qdev-monitor.c
Log Message:
-----------
qdev: Do not let the user try to device_add when it cannot work
Such devices have always been unavailable and omitted from the list of
available devices shown by device_add help. Until commit 18b6dad
silently broke the former, setting up nasty traps for unwary users,
like this one:
$ qemu-system-x86_64 -nodefaults -monitor stdio -display none
QEMU 1.6.50 monitor - type 'help' for more information
(qemu) device_add apic
Segmentation fault (core dumped)
I call that a regression. Fix it.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 112f2ac98d8bd4edafc4a4c84d0abcd9ba98a736
https://github.com/qemu/qemu/commit/112f2ac98d8bd4edafc4a4c84d0abcd9ba98a736
Author: Stefan Weil <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M hw/arm/highbank.c
Log Message:
-----------
hw/arm/highbank: Simplify code (memory region in device state)
The memory region can be included by value instead of by reference in the
device state.
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 2e0fc3a488ef12c4e0e3ad4e1a07efec3a19169e
https://github.com/qemu/qemu/commit/2e0fc3a488ef12c4e0e3ad4e1a07efec3a19169e
Author: Stefan Weil <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-openrisc/translate.c
Log Message:
-----------
openrisc: Fix spelling in comment (transaltion -> translation)
I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Jia Liu <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: dff7424dc09635c33b42193fbb40c90fc9a971f4
https://github.com/qemu/qemu/commit/dff7424dc09635c33b42193fbb40c90fc9a971f4
Author: Stefan Weil <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M hw/audio/intel-hda.c
M net/net.c
M qemu-char.c
Log Message:
-----------
misc: Use macro ARRAY_SIZE where possible
This improves readability and simplifies the code.
Cc: Anthony Liguori <address@hidden>
Cc: Gerd Hoffmann <address@hidden>
Cc: Stefan Hajnoczi <address@hidden>
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 5d70192bcb80a5355323a4736e0fb44d8e2b6743
https://github.com/qemu/qemu/commit/5d70192bcb80a5355323a4736e0fb44d8e2b6743
Author: Stefan Weil <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M ui/cocoa.m
Log Message:
-----------
ui/cocoa: Use macro ARRAY_SIZE where possible
This improves readability and simplifies the code.
Cc: Andreas Färber <address@hidden>
Cc: Anthony Liguori <address@hidden>
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: c46b07f0d7a826ea0bb5811dd49450c2497fb926
https://github.com/qemu/qemu/commit/c46b07f0d7a826ea0bb5811dd49450c2497fb926
Author: Stefan Weil <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M hw/char/exynos4210_uart.c
M hw/misc/exynos4210_pmu.c
Log Message:
-----------
exynos4210: Use macro ARRAY_SIZE where possible
This improves readability and simplifies the code.
Cc: Dmitry Solodkiy <address@hidden>
Cc: Evgeny Voevodin <address@hidden>
Cc: Igor Mitsyanko <address@hidden>
Cc: Maksim Kozlov <address@hidden>
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 0d9e61c2619eeead4de6afa8fedec2ad9311b642
https://github.com/qemu/qemu/commit/0d9e61c2619eeead4de6afa8fedec2ad9311b642
Author: Stefan Weil <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: Use macro TARGET_NSIG_WORDS where possible
This improves readability and simplifies the code.
Cc: Riku Voipio <address@hidden>
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 33dfdb56f2f3c8686d218395b871ec12fd5bf30b
https://github.com/qemu/qemu/commit/33dfdb56f2f3c8686d218395b871ec12fd5bf30b
Author: Alexander Graf <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-i386/helper.c
Log Message:
-----------
x86: only allow real mode to access 32bit without LMA
When we're running in non-64bit mode with qemu-system-x86_64 we can
still end up with virtual addresses that are above the 32bit boundary
if a segment offset is set up.
GNU Hurd does exactly that. It sets the segment offset to 0x80000000 and
puts its EIP value to 0x8xxxxxxx to access low memory.
This doesn't hit us when we enable paging, as there we just mask away the
unused bits. But with real mode, we assume that vaddr == paddr which is
wrong in this case. Real hardware wraps the virtual address around at the
32bit boundary. So let's do the same.
This fixes booting GNU Hurd in qemu-system-x86_64 for me.
Reported-by: Michael Tokarev <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 6f2bfda35cf1c7b8a5913570b808396ab9299873
https://github.com/qemu/qemu/commit/6f2bfda35cf1c7b8a5913570b808396ab9299873
Author: Michael Tokarev <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M vl.c
Log Message:
-----------
vl: make boot_strict variable static (not used outside vl.c)
Signed-off-by: Michael Tokarev <address@hidden>
Reviewed-by: Amos Kong <address@hidden>
Commit: e5187b561ff7b241d609a2848131879072169565
https://github.com/qemu/qemu/commit/e5187b561ff7b241d609a2848131879072169565
Author: Amos Kong <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M vl.c
Log Message:
-----------
fix -boot strict regressed in commit 6ef4716
Commit 6ef4716 cleaned up parsing of -boot option argument, but
accidentally dropped parameter strict. It should have been updated
exactly like parameter menu. Do that.
Signed-off-by: Amos Kong <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 4a08d4758faf4d6497a5f6fa6be6f048a5359420
https://github.com/qemu/qemu/commit/4a08d4758faf4d6497a5f6fa6be6f048a5359420
Author: Peter Maydell <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for ld/st pair
This patch support the basic load and store pair instructions and
includes the generic helper functions:
* do_gpr_st()
* do_fp_st()
* do_gpr_ld()
* do_fp_ld()
* read_cpu_reg_sp()
* gen_check_sp_alignment()
The last function gen_check_sp_alignment() is a NULL op currently but
put in place to make it easy to add SP alignment checking later.
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: d5612f10a1a92afd390d4950b9f8af00ec30ad3e
https://github.com/qemu/qemu/commit/d5612f10a1a92afd390d4950b9f8af00ec30ad3e
Author: Alex Bennée <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for ld/st unsigned imm
This adds support for the forms of ld/st with a 12 bit
unsigned immediate offset.
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 229b7a05e3abd3def309a04b5d1c14f3a3cb9236
https://github.com/qemu/qemu/commit/229b7a05e3abd3def309a04b5d1c14f3a3cb9236
Author: Alex Bennée <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for ld/st with reg offset
This adds support for the load/store forms using a register offset.
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: a5e94a9d767b2111608fe2013492392c7117cef5
https://github.com/qemu/qemu/commit/a5e94a9d767b2111608fe2013492392c7117cef5
Author: Alex Bennée <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for ld/st with index
This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form (which are all
variations on the same 9-bit immediate instruction form).
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: b0ff21b4f96fa8223ec252ec3e99a8a9af86cf0c
https://github.com/qemu/qemu/commit/b0ff21b4f96fa8223ec252ec3e99a8a9af86cf0c
Author: Alex Bennée <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for add, addi, sub, subi
Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This includes the code to calculate NZCV if the instruction
calls for setting the flags.
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: ed6ec679a8706af4eedd7b3aa132f13bb2329abe
https://github.com/qemu/qemu/commit/ed6ec679a8706af4eedd7b3aa132f13bb2329abe
Author: Alex Bennée <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for move wide instructions
This patch adds emulation for the mov wide instructions
(MOVN, MOVZ, MOVK).
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 52c8b9afcd019df799f5eb779395b46a610348b8
https://github.com/qemu/qemu/commit/52c8b9afcd019df799f5eb779395b46a610348b8
Author: Alexander Graf <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for 3 src data proc insns
This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.
Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 9618e80938d38eeee765dd23fc0b7475ae536e77
https://github.com/qemu/qemu/commit/9618e80938d38eeee765dd23fc0b7475ae536e77
Author: Alexander Graf <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: implement SVC, BRK
Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).
Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: faa0ba465b772200e9775c1f5af886cfc83d0da6
https://github.com/qemu/qemu/commit/faa0ba465b772200e9775c1f5af886cfc83d0da6
Author: Peter Maydell <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add decoder skeleton for FP instructions
Add a top level decoder skeleton for FP instructions.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: ce5458e82e250c66fe31c716d0e44fac5b1bc349
https://github.com/qemu/qemu/commit/ce5458e82e250c66fe31c716d0e44fac5b1bc349
Author: Peter Maydell <address@hidden>
Date: 2013-12-23 (Mon, 23 Dec 2013)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: implement FMOV
Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a subtype of
the floating point <-> integer instruction class.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 061e84f7a469ad1f94f3b5f6a5361b346ab990e8
https://github.com/qemu/qemu/commit/061e84f7a469ad1f94f3b5f6a5361b346ab990e8
Author: Markus Armbruster <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M qdev-monitor.c
Log Message:
-----------
qdev-monitor: Avoid device_add crashing on non-device driver name
Watch this:
$ upstream-qemu -nodefaults -S -display none -monitor stdio
QEMU 1.7.50 monitor - type 'help' for more information
(qemu) device_add rng-egd
/work/armbru/qemu/qdev-monitor.c:491:qdev_device_add: Object 0x2089b00 is
not an instance of type device
Aborted (core dumped)
Crashes because "rng-egd" exists, but isn't a subtype of TYPE_DEVICE.
Broken in commit 18b6dad.
Cc: address@hidden
Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 1b111dc1216be2a89770fdc1ab3dfa8025957442
https://github.com/qemu/qemu/commit/1b111dc1216be2a89770fdc1ab3dfa8025957442
Author: Markus Armbruster <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/audio/marvell_88w8618.c
M hw/dma/sparc32_dma.c
M hw/gpio/omap_gpio.c
M hw/i2c/omap_i2c.c
M hw/i2c/smbus_eeprom.c
M hw/intc/etraxfs_pic.c
M hw/intc/grlib_irqmp.c
M hw/intc/omap_intc.c
M hw/net/etraxfs_eth.c
M hw/net/lance.c
Log Message:
-----------
hw: cannot_instantiate_with_device_add_yet due to pointer props
Pointer properties can be set only by code, not by device_add. A
device with a pointer property can work with device_add only when the
property may remain null.
This is the case for property "interrupt_vector" of device
"etraxfs,pic". Add a comment there.
Set cannot_instantiate_with_device_add_yet for the other devices with
pointer properties, with a comment explaining why.
Juha Riihimäki and Peter Maydell deserve my thanks for making "pointer
property must not remain null" blatantly obvious in the OMAP devices.
Only device "smbus-eeprom" is actually changed. The others are all
sysbus devices, which get cannot_instantiate_with_device_add_yet set
in their abstract base's class init function. Setting it again in
their class init function is technically redundant, but serves as
insurance for when sysbus devices become available with device_add,
and as documentation.
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden> (for ETRAX)
Signed-off-by: Andreas Färber <address@hidden>
Commit: c272758f93b9c88c884461a2baa37b8f4008bf02
https://github.com/qemu/qemu/commit/c272758f93b9c88c884461a2baa37b8f4008bf02
Author: Markus Armbruster <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M include/hw/qdev-properties.h
Log Message:
-----------
qdev: Document that pointer properties kill device_add
Ask users of DEFINE_PROP_PTR() to set
cannot_instantiate_with_device_add_yet, or explain why it's not
needed.
Signed-off-by: Markus Armbruster <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 0ab4c94c844cb3953adedbd27adc378b3cf31d9e
https://github.com/qemu/qemu/commit/0ab4c94c844cb3953adedbd27adc378b3cf31d9e
Author: Peter Crosthwaite <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M include/qom/object.h
M qom/object.c
Log Message:
-----------
qom: Split out object and class caches
The object-cast and class-cast caches cannot be shared because class
caching is conditional on the target type not being an interface and
object caching is unconditional. Leads to a bug when a class cast
to an interface follows an object cast to the same interface type:
FooObject = FOO(obj);
FooClass = FOO_GET_CLASS(obj);
Where TYPE_FOO is an interface. The first (object) cast will be
successful and cache the casting result (i.e. TYPE_FOO will be cached).
The second (class) cast will then check the shared cast cache
and register a hit. The issue is, when a class cast hits in the cache
it just returns a pointer cast of the input class (i.e. the concrete
class).
When casting to an interface, the cast itself must return the
interface class, not the concrete class. The implementation of class
cast caching already ensures that the returned cast result is only
a pointer cast before caching. The object cast logic however does
not have this check.
Resolve by just splitting the object and class caches.
Cc: address@hidden
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Tested-by: Nathan Rossi <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: b061dc41f62048acd4a34c6570c0ea396cd9d0b4
https://github.com/qemu/qemu/commit/b061dc41f62048acd4a34c6570c0ea396cd9d0b4
Author: Paolo Bonzini <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M include/qom/object.h
M qom/object.c
Log Message:
-----------
qom: Do not register interface "types" in the type table and fix names
There should be no need to look up nor enumerate the interface "types",
whose "classes" are really just vtables. Just create the types and
add them to the interface list of the parent type.
Interfaces not registering their type anymore means that accessing
superclass::interface by type name will fail when initializing
subclass::interface. Thus, we need to pre-initialize the subclass's
parent_type field before calling type_initialize. Apart from this, the
interface "types" should never be used and thus it is harmless to leave
them out of the hashtable.
Further, the interface types had a bug with interfaces that are
inherited from a superclass: The implementation type name was wrong
(for example it was subclass::superclass::interface rather than
just subclass::interface). This patch fixes this as well.
Reported-by: Igor Mammedov <address@hidden>
Tested-by: Igor Mammedov <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 14389dbd0281e901176319f5868166c706485c5e
https://github.com/qemu/qemu/commit/14389dbd0281e901176319f5868166c706485c5e
Author: Igor Mammedov <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M tests/Makefile
A tests/check-qom-interface.c
Log Message:
-----------
tests: Test QOM interface casting
Add basic regression testing for QOM Interface usage.
Test checks casting to interface type/class for following cases:
- interface implementation in leaf class
- interface implementation in intermediate (parent) class
Signed-off-by: Igor Mammedov <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: f54c19cacb44d2fad14aca6be08e4aa9b8423217
https://github.com/qemu/qemu/commit/f54c19cacb44d2fad14aca6be08e4aa9b8423217
Author: Hervé Poussineau <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M qom/object.c
Log Message:
-----------
qom: Detect bad reentrance during object_class_foreach()
We should not modify the type hash table while it is being iterated on.
Assert that it does not happen.
Signed-off-by: Hervé Poussineau <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 6780a22cc71227068925e7b70faa71d6641a9b1b
https://github.com/qemu/qemu/commit/6780a22cc71227068925e7b70faa71d6641a9b1b
Author: Stefan Hajnoczi <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/core/qdev.c
M hw/pci/pci_bridge.c
M include/hw/qdev-core.h
Log Message:
-----------
qdev: Drop misleading qbus_free() function
Same reasoning as commit 02a5c4c97422b40034f31265e0f139f7846172a8
("qdev: Drop misleading qdev_free() function"). The qbus_free()
function removes the child from the namespace and decrements the
reference count. It does not, however, guarantee to free the child
since the refcount may still be held.
Just call object_unparent() directly.
Suggested-by: Markus Armbruster <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: d3b0c9e90a9853984c60478dae45bedf8aadf42a
https://github.com/qemu/qemu/commit/d3b0c9e90a9853984c60478dae45bedf8aadf42a
Author: xiaoqiang zhao <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/i386/kvm/apic.c
M hw/intc/apic.c
M hw/intc/apic_common.c
Log Message:
-----------
apic: Cleanup for QOM'ification
Do some cleanup, including:
1. Remove DO_UPCAST() for APICCommonState
2. Change DeviceState pointers from 'd' to 'dev', better to understand
3. Rename 'register_types' to specifically 'apic_common_register_types'
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: ff6986ce618c69f988e4419efd67ea5cbf7792a5
https://github.com/qemu/qemu/commit/ff6986ce618c69f988e4419efd67ea5cbf7792a5
Author: xiaoqiang zhao <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/i386/kvm/apic.c
M hw/intc/apic.c
M hw/intc/apic_common.c
M hw/xen/xen_apic.c
M include/hw/i386/apic_internal.h
Log Message:
-----------
apic: QOM'ify APIC
Convert 'init' function to QOM's 'realize' for apic, kvm/apic and
xen/xen_apic.
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 494c271784a5e360523e874be9f67259932ea68c
https://github.com/qemu/qemu/commit/494c271784a5e360523e874be9f67259932ea68c
Author: xiaoqiang zhao <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/cpu/icc_bus.c
M hw/intc/apic_common.c
M include/hw/cpu/icc_bus.h
Log Message:
-----------
icc_bus: QOM'ify ICC
For consistency, QOM'ify APIC's parent bus.
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: f97718584baa6ef919d00067b9787ba7fc5f1a5b
https://github.com/qemu/qemu/commit/f97718584baa6ef919d00067b9787ba7fc5f1a5b
Author: xiaoqiang zhao <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/i386/kvm/ioapic.c
M hw/intc/ioapic.c
M hw/intc/ioapic_common.c
Log Message:
-----------
ioapic: Cleanup for QOM'ification
Some cleanups:
* ioapic_common.c: Rename 'register_types' to 'ioapic_common_register_types'
* Replace inline 'DEVICE(s)' with local 'DeviceState *dev' variable
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: db0f888848bc5cc578d005d04f4cf7a1105bb758
https://github.com/qemu/qemu/commit/db0f888848bc5cc578d005d04f4cf7a1105bb758
Author: xiaoqiang zhao <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M hw/i386/kvm/ioapic.c
M hw/intc/ioapic.c
M hw/intc/ioapic_common.c
M include/hw/i386/ioapic_internal.h
Log Message:
-----------
ioapic: QOM'ify ioapic
Convert 'init' function to QOM's 'realize' for ioapic and kvm-ioapic.
Change variable 'ioapic_no' from static to global. Then we can drop
the 'instance_no' function argument.
Signed-off-by: xiaoqiang zhao <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 11c308b17a34932033cceca4f88b5e67009e3ebd
https://github.com/qemu/qemu/commit/11c308b17a34932033cceca4f88b5e67009e3ebd
Author: Markus Armbruster <address@hidden>
Date: 2013-12-24 (Tue, 24 Dec 2013)
Changed paths:
M qdev-monitor.c
Log Message:
-----------
qdev-monitor: Improve error message for -device nonexistant
Once upon a time, the error message was:
qemu: -device nonexistant: Device "nonexistant" not found. Try -device '?'
for a list.
But progress marches on, and conversion to QError (commit 0204276)
changed it into:
Invalid parameter 'driver'
Try with argument '?' for a list.
Progress didn't stop there, of course. After a couple of iterations,
we arrived at the current message (commit 6acbe4c):
qemu: -device nonexistant: Parameter 'driver' expects device type
Mission accomplished: this is complete mush.
We've since abandoned our quest for "rich" error objects, fortunately
before it turned all error messages into mush. Time to undo the
damage to this one. Make it:
qemu: -device nonexistant: nonexistant is not a valid device model name
Signed-off-by: Markus Armbruster <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Commit: 08fb77ed391dcbb35ba98fd98d81635a9f6aeb12
https://github.com/qemu/qemu/commit/08fb77ed391dcbb35ba98fd98d81635a9f6aeb12
Author: Stefan Weil <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M configure
Log Message:
-----------
configure: Rewrite code for help message
In the new form most lines of the code now look like the final output:
there is no leading echo command and the lines are shorter.
The resulting output is nearly identical: the only difference is a blank
character which was deliberately removed:
@@ -8,7 +8,7 @@
--interp-prefix=PREFIX where to find shared libraries, etc.
use %M for cpu name [/usr/gnemul/qemu-%M]
--target-list=LIST set target list (default: build everything)
- Available targets: alpha-softmmu arm-softmmu
+ Available targets: alpha-softmmu arm-softmmu
cris-softmmu i386-softmmu lm32-softmmu m68k-softmmu
microblaze-softmmu microblazeel-softmmu mips-softmmu
mips64-softmmu mips64el-softmmu mipsel-softmmu
Signed-off-by: Stefan Weil <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: f6f0b7d90fe0c481d33165334b4a595fa514c202
https://github.com/qemu/qemu/commit/f6f0b7d90fe0c481d33165334b4a595fa514c202
Author: Stefan Weil <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M configure
Log Message:
-----------
configure: Python tests must be done before help message
The help message uses $python and displays its value, so that macro
should be tested and set early.
With this modification, configure --help displays the correct value
(usually python -B) and no longer creates several *.pyc files.
Signed-off-by: Stefan Weil <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 88e020e55e8fcfee0ca2428fb3654469abbd21ae
https://github.com/qemu/qemu/commit/88e020e55e8fcfee0ca2428fb3654469abbd21ae
Author: Ingo van Lil <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M qemu-options.hx
Log Message:
-----------
doc: Mention chardev:id in available devices for -serial
It is possible to pre-define a character device with the -chardev option
and reference its id as serial device. The man page does not mention this
feature.
Use case: Use stdio as serial, but do not terminate VM on Ctrl-C
-chardev stdio,id=mystdio,signal=off -serial chardev:mystdio
Signed-off-by: Ingo van Lil <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: f57d6693e1ad994374927d7ab7b151bb28f0cb37
https://github.com/qemu/qemu/commit/f57d6693e1ad994374927d7ab7b151bb28f0cb37
Author: Stefan Weil <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M include/hw/arm/pxa.h
Log Message:
-----------
pxa27x: Reduce size of keyboard matrix mapping
The row and column values use only a very limited range (-1 ... 7),
so a byte value is sufficient.
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 52975c313ee4b5ce2004c1ed3279272a55429ede
https://github.com/qemu/qemu/commit/52975c313ee4b5ce2004c1ed3279272a55429ede
Author: Stefan Weil <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M hw/arm/mainstone.c
M hw/arm/z2.c
M hw/input/pxa2xx_keypad.c
M include/hw/arm/pxa.h
Log Message:
-----------
pxa27x: Add 'const' attribute to keyboard maps
The mapping is a hardware feature, so it is relatively constant.
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 7dbc1158bc63fdbad849d21409eeeb53f5230445
https://github.com/qemu/qemu/commit/7dbc1158bc63fdbad849d21409eeeb53f5230445
Author: Stefan Weil <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M hw/arm/mainstone.c
Log Message:
-----------
mainstone: Fix duplicate array values for key 'space'
cgcc reported a duplicate initialisation. Mainstone includes a matrix
keyboard where two different positions map to 'space'.
QEMU uses the reversed mapping and does not map 'space' to two different
matrix positions.
Some other keys are either missing or might be mapped wrongly (cf. Linux
kernel code). Don't fix these until someone can test them with real
hardware, but add TODO comments.
Signed-off-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 5862ad0f55fa54f3ed05774b538a7e862a10941f
https://github.com/qemu/qemu/commit/5862ad0f55fa54f3ed05774b538a7e862a10941f
Author: Fam Zheng <address@hidden>
Date: 2014-01-01 (Wed, 01 Jan 2014)
Changed paths:
M tests/acpi-test.c
Log Message:
-----------
acpi unit-test: Remove temporary disk after test
Signed-off-by: Fam Zheng <address@hidden>
Signed-off-by: Michael Tokarev <address@hidden>
Commit: 6e6efd612f58726189893fd4d948b7fc10acd872
https://github.com/qemu/qemu/commit/6e6efd612f58726189893fd4d948b7fc10acd872
Author: Peter Maydell <address@hidden>
Date: 2014-01-04 (Sat, 04 Jan 2014)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Pull "add one cpreg to hashtable" into its own function
define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each of the possible
opc/crn/crm values allowed by wildcard specifications. We're about
to add an extra loop to this nesting, so pull the core of the loop
(which adds a single entry to the hashtable) out into its own
function for clarity.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: f5a0a5a5abe7b72ad14b8884681a25fcf3e91c16
https://github.com/qemu/qemu/commit/f5a0a5a5abe7b72ad14b8884681a25fcf3e91c16
Author: Peter Maydell <address@hidden>
Date: 2014-01-04 (Sat, 04 Jan 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/kvm-consts.h
Log Message:
-----------
target-arm: Update generic cpreg code for AArch64
Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash table with
AArch32-visible ones, with a bit in the hash key distinguishing
them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Commit: 60322b399dc62da7cc1ccd42fbd19b017f8a5e38
https://github.com/qemu/qemu/commit/60322b399dc62da7cc1ccd42fbd19b017f8a5e38
Author: Peter Maydell <address@hidden>
Date: 2014-01-07 (Tue, 07 Jan 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/translate-a64.c
M target-arm/translate.c
M target-arm/translate.h
Log Message:
-----------
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
This is problematic for the A64 decoder, which doesn't pass the
environment pointer around everywhere the way the 32 bit decoder
does. Adjust the parameters these functions take so that we can
copy only the relevant info from the CPUARMState into the
DisasContext and then use that.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: fea505221eaf87889000378d4d33ad0dfd5f4d9d
https://github.com/qemu/qemu/commit/fea505221eaf87889000378d4d33ad0dfd5f4d9d
Author: Peter Maydell <address@hidden>
Date: 2014-01-07 (Tue, 07 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Implement MRS/MSR/SYS/SYSL
The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/SYSL, which cover between them both true
system registers and the "operations with side effects"
such as cache maintenance which in AArch32 are mixed
in with other cp15 registers. Implement these instructions
to look in the cpregs hashtable for the register or
operation.
Since we don't yet populate the cpregs hashtable with
any registers with the "AA64" bit set, everything will
still UNDEF at this point.
MSR/MRS is the first user of is_jmp = DISAS_UPDATE, so
fix an infelicity in its handling where the main loop
was requiring the caller to do the update of PC rather
than just doing it itself.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: b0d2b7d0f084f6b33acf7c722790da683916fee3
https://github.com/qemu/qemu/commit/b0d2b7d0f084f6b33acf7c722790da683916fee3
Author: Peter Maydell <address@hidden>
Date: 2014-01-07 (Tue, 07 Jan 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Implement minimal set of EL0-visible sysregs
Implement an initial minimal set of EL0-visible system registers:
* NZCV
* FPCR
* FPSR
* CTR_EL0
* DCZID_EL0
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Commit: e4fe830b50b56561dae5b5c79c6eb63cc2e94a3d
https://github.com/qemu/qemu/commit/e4fe830b50b56561dae5b5c79c6eb63cc2e94a3d
Author: Peter Maydell <address@hidden>
Date: 2014-01-07 (Tue, 07 Jan 2014)
Changed paths:
M linux-user/aarch64/target_cpu.h
M linux-user/arm/target_cpu.h
M linux-user/main.c
M target-arm/cpu.h
M target-arm/helper.c
Log Message:
-----------
target-arm: Widen thread-local register state fields to 64 bits
The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a view of the
bottom 32 bits of the 64-bit AArch64 system register; writes in
AArch32 leave the top half unchanged. The most natural way to
model this is to have the state field in the CPU struct be a
64 bit value, and simply have the AArch32 TCG code operate on
a pointer to its lower half.
For aarch64-linux-user the only registers we need to share like
this are the thread-local-storage ones. Widen their fields to
64 bits and provide the 64 bit reginfo struct to make them
visible in AArch64 state. Note that minor cleanup of the AArch64
system register encoding space means We can share the TPIDR_EL1
reginfo but need split encodings for TPIDR_EL0 and TPIDRRO_EL0.
Since we're touching almost every line in QEMU that uses the
c13_tls* fields in this patch anyway, we take the opportunity
to rename them in line with the standard ARM architectural names
for these registers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 643dbb07d26d100487ea87153d5222674bf482d8
https://github.com/qemu/qemu/commit/643dbb07d26d100487ea87153d5222674bf482d8
Author: Claudio Fontana <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for add/sub with carry
This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 750813cfaa971bd8679d9f77b8bd21d316871f51
https://github.com/qemu/qemu/commit/750813cfaa971bd8679d9f77b8bd21d316871f51
Author: Claudio Fontana <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: add support for conditional compare insns
this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 32b64e860d6e0887b3d2ad36a940c362646146f4
https://github.com/qemu/qemu/commit/32b64e860d6e0887b3d2ad36a940c362646146f4
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: aarch64: add support for ld lit
Adds support for Load Register (literal), both normal
and SIMD/FP forms.
Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 03d05e2d0765512fb960192b6e9f9a41c47282bd
https://github.com/qemu/qemu/commit/03d05e2d0765512fb960192b6e9f9a41c47282bd
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M linux-user/main.c
M target-arm/cpu.h
M target-arm/machine.c
M target-arm/translate.c
Log Message:
-----------
target-arm: Widen exclusive-access support struct fields to 64 bits
In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct that deal with address and data values
for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
exclusive accesses will be generally separate there are some odd theoretical
corner cases (eg you should be able to do the exclusive load in AArch32, take
an exception to AArch64 and successfully do the store exclusive there), and it's
also easier to reason about.
The changes in semantics for the variables are:
exclusive_addr -> extended to 64 bits; -1ULL for "monitor lost",
otherwise always < 2^32 for AArch32
exclusive_val -> extended to 64 bits. 64 bit exclusives in AArch32 now
use the high half of exclusive_val instead of a separate exclusive_high
exclusive_high -> is no longer used in AArch32; extended to 64 bits as
it will be needed for AArch64's pair-of-64-bit-values exclusives.
exclusive_test -> extended to 64 bits, as it is an address. Since this is
a linux-user-only field, in arm-linux-user it will always have the top
32 bits zero.
exclusive_info -> stays 32 bits, as it is neither data nor address, but
simply holds register indexes etc. AArch64 will be able to fit all its
information into 32 bits as well.
Note that the refactoring of gen_store_exclusive() coincidentally fixes
a minor bug where ldrexd would incorrectly update the first CPU register
even if the load for the second register faulted.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: fa2ef212dff8556ea92c4aef54b57efec69ca6fe
https://github.com/qemu/qemu/commit/fa2ef212dff8556ea92c4aef54b57efec69ca6fe
Author: Michael Matz <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M linux-user/main.c
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: support for ld/st/cl exclusive
This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive load remembers the address
and loaded value. The exclusive store throws an an exception which uses
those values to check for equality in a proper exclusive region.
This is not actually the architecture mandated semantics (for either
AArch32 or AArch64) but it is close enough for typical guest code
sequences to work correctly, and saves us from having to monitor all
guest stores. It's fairly easy to come up with test cases where we
don't behave like hardware - we don't for example model cache line
behaviour. However in the common patterns this works, and the existing
32 bit ARM exclusive access implementation has the same limitations.
AArch64 also implements new acquire/release loads/stores (which may be
either exclusive or non-exclusive). These imposes extra ordering
constraints on memory operations (ie they act as if they have an implicit
barrier built into them). As TCG is single-threaded all our barriers
are no-ops, so these just behave like normal loads and stores.
Signed-off-by: Michael Matz <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 1b69f006bff89e5e4710dd04be85277aab8856bf
https://github.com/qemu/qemu/commit/1b69f006bff89e5e4710dd04be85277aab8856bf
Author: Claudio Fontana <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M linux-user/aarch64/syscall.h
Log Message:
-----------
linux-user: AArch64: define TARGET_CLONE_BACKWARDS
The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling of the clone()
syscall argument order, so we failed to notice that AArch64 also needs
TARGET_CLONE_BACKWARDS to be defined. Add this define so that clone
and fork syscalls work correctly.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: e0ee138bf241ca493afe1419d578584b8be05c29
https://github.com/qemu/qemu/commit/e0ee138bf241ca493afe1419d578584b8be05c29
Author: Will Newton <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M linux-user/signal.c
Log Message:
-----------
linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext
Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 08aef910d9398ba488455dbb553a8253dc24a333
https://github.com/qemu/qemu/commit/08aef910d9398ba488455dbb553a8253dc24a333
Author: Alex Bennée <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M .travis.yml
Log Message:
-----------
.travis.yml: Add aarch64-* targets
Now the AArch64 targets are in mainline we can include them in our
Travis test matrix.
Signed-off-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 13a7f79dfea84ddb9ff1132bf87583bdda93182d
https://github.com/qemu/qemu/commit/13a7f79dfea84ddb9ff1132bf87583bdda93182d
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
A default-configs/aarch64-linux-user.mak
Log Message:
-----------
default-configs: Add config for aarch64-linux-user
Add a config for aarch64-linux-user, thereby enabling it as
a valid target.
Signed-off-by: Peter Maydell <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: f6d8a31440c523de15f88a186b9e6daacab17054
https://github.com/qemu/qemu/commit/f6d8a31440c523de15f88a186b9e6daacab17054
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add support for dumping AArch64 VFP register state
When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, rebased. Output all registers, two per-line.]
Signed-off-by: Will Newton <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: e2f90565e7b3e2824fffcfcbcecf86205a1f14e2
https://github.com/qemu/qemu/commit/e2f90565e7b3e2824fffcfcbcecf86205a1f14e2
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Fix vector register access on bigendian hosts
The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we're directly loading or storing a value of size less than
64 bits we must adjust the offset appropriately to account
for whether the host is bigendian or not. Provide utility
functions to abstract away the offsetof() calculations for
the FP registers.
For do_fp_st() we can sidestep most of the issues for 64 bit
and smaller reg-to-mem transfers by always doing a 64 bit
load from the register and writing just the piece we need
to memory.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: f71a2ae50e728f775446302d84e509bf0af43899
https://github.com/qemu/qemu/commit/f71a2ae50e728f775446302d84e509bf0af43899
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
M target-arm/helper.h
M target-arm/neon_helper.c
M target-arm/translate.c
Log Message:
-----------
target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
Use the VFP_BINOP macro to provide helpers for min, max, minnum
and maxnum, rather than hand-rolling them. (The float64 max
version is not used by A32 but will be needed for A64.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: ec73d2e096df1848cbd4255ed2b69954498085aa
https://github.com/qemu/qemu/commit/ec73d2e096df1848cbd4255ed2b69954498085aa
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, merge single and double precision patches. Rebase
and update to new infrastructure. Incorporate FMIN/FMAX support patch by
Michael Matz.]
Signed-off-by: Will Newton <address@hidden>
[PMM:
* added convenience accessors for FP s and d regs
* pulled the field decode and opcode validity check up a level]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 6a30667fb77601b47501172218c7eabd0086c375
https://github.com/qemu/qemu/commit/6a30667fb77601b47501172218c7eabd0086c375
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, merged single and double precision patches.
Implement using muladd as suggested by Richard Henderson.]
Signed-off-by: Will Newton <address@hidden>
[PMM: pull field decode up a level, use register accessors]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 6163f868c9284a204ea108238f1812ad50c6bf17
https://github.com/qemu/qemu/commit/6163f868c9284a204ea108238f1812ad50c6bf17
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add fmov (scalar, immediate) instruction
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: da7dafe7ee9372322f926834ca7c0532822ad415
https://github.com/qemu/qemu/commit/da7dafe7ee9372322f926834ca7c0532822ad415
Author: Claudio Fontana <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper-a64.c
M target-arm/helper-a64.h
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add support for floating point compare
Add decoding support for C3.6.22 Floating-point compare.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 513f1d762f12a4cfdb6cfd59db5f2fb434db60ec
https://github.com/qemu/qemu/commit/513f1d762f12a4cfdb6cfd59db5f2fb434db60ec
Author: Claudio Fontana <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add support for floating point conditional compare
This adds decoding support for C3.6.23 FP Conditional Compare.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 5640ff62c9668651beae0a438540040fd9ee05b5
https://github.com/qemu/qemu/commit/5640ff62c9668651beae0a438540040fd9ee05b5
Author: Claudio Fontana <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add support for floating point cond select
This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 4d3da0f3aa5a5d0cbdb17ad49f1baf3cf1bd95a1
https://github.com/qemu/qemu/commit/4d3da0f3aa5a5d0cbdb17ad49f1baf3cf1bd95a1
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/cpu.h
M target-arm/helper.c
Log Message:
-----------
target-arm: Give the FPSCR rounding modes names
When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.
With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names so we don't get confused by accident.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, use names from ARM ARM.]
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 059ca2bf0d882349aa002e10e3769d25cb923eb4
https://github.com/qemu/qemu/commit/059ca2bf0d882349aa002e10e3769d25cb923eb4
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Mark struct fields as public/private
As per current QOM conventions.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 589bfb6888385ae1767fe2f94528f2dacf59509a
https://github.com/qemu/qemu/commit/589bfb6888385ae1767fe2f94528f2dacf59509a
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Add missing uart_update_state
This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 823dd48761a668c8e787cb9cf07234b656a05926
https://github.com/qemu/qemu/commit/823dd48761a668c8e787cb9cf07234b656a05926
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Fix reset.
Don't reset the uart as an init step. Register the reset function as a
proper reset fn instead.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1e77c91e2422ffa366fa5a0a39a6e7cc24a102ca
https://github.com/qemu/qemu/commit/1e77c91e2422ffa366fa5a0a39a6e7cc24a102ca
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: s/r_fifo/rx_fifo
Rename this field to match the many other uses of "rx". Xilinx
docmentation (UG585) also refers to this as "RxFIFO".
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 676f4c095d53841626b1ee2cbc7a53b4f6239e4e
https://github.com/qemu/qemu/commit/676f4c095d53841626b1ee2cbc7a53b4f6239e4e
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Simplify status generation
The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 11a239a51ccbf27a22e2aa5f423ff1d6f5df65a7
https://github.com/qemu/qemu/commit/11a239a51ccbf27a22e2aa5f423ff1d6f5df65a7
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Define Missing SR/ISR fields
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2152e08ad12180f307bc5b838134ab745767d2e5
https://github.com/qemu/qemu/commit/2152e08ad12180f307bc5b838134ab745767d2e5
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Remove TX timer & add TX FIFO state
This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the TX-empty status
bit (and corresponding interrupt) the controller is still transmitting
characters instantaneously. There is also no sense of multiple character
delay.
The only side effect of this timer is assertion of tx-empty status. So
just remove the timer completely and hold tx-empty as permanently
asserted (its reset status). This matches the actual behaviour of
instantaneous transmission.
While we are VMSD version bumping, add the tx_fifo as device state to
prepare for upcomming TxFIFO flow control. Implement the interrupt
generation logic for the TxFIFO occupancy.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d0ac820fe4152ea3a57fc3fa9f732cc9524017a4
https://github.com/qemu/qemu/commit/d0ac820fe4152ea3a57fc3fa9f732cc9524017a4
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Fix can_receive logic
The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo and normal modes
however. Improve the logic to correctly return the true number of
receivable characters based on the current mode:
Normal mode: RxFIFO vacancy.
Remote loopback: TxFIFO vacancy.
Echo mode: The min of the TxFIFO and RxFIFO vacancies.
Local Loopback: Return non-zero (to implement droppage)
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 86baecc3e43510c3bef03a0d7e947221823864d3
https://github.com/qemu/qemu/commit/86baecc3e43510c3bef03a0d7e947221823864d3
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Use the TX fifo for transmission
Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 1e5d8cacb7fe509aa793ad844105fbc4fe02e015
https://github.com/qemu/qemu/commit/1e5d8cacb7fe509aa793ad844105fbc4fe02e015
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Delete redundant rx rst logic
uart_rx_reset() called immediately above already does this. Remove.
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 38acd64b1cc8b9589e155d16ba4a0ccf9dc95ae4
https://github.com/qemu/qemu/commit/38acd64b1cc8b9589e155d16ba4a0ccf9dc95ae4
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/char/cadence_uart.c
Log Message:
-----------
char/cadence_uart: Implement Tx flow control
If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a4f0cec6c9da10c5998fdd53845baf2ce6105830
https://github.com/qemu/qemu/commit/a4f0cec6c9da10c5998fdd53845baf2ce6105830
Author: Sergey Fedorov <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: use c13_context field for CONTEXTIDR
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: afb2530fe328079b3e4355fda9751a1dd9ef6ffb
https://github.com/qemu/qemu/commit/afb2530fe328079b3e4355fda9751a1dd9ef6ffb
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: remove raw_read|write duplication
There is an inline duplication of the raw_read and raw_write function
bodies. Fix by just calling raw_read/raw_write instead.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7fcd57e80d134deb925aa47934040a39fd5fa1e0
https://github.com/qemu/qemu/commit/7fcd57e80d134deb925aa47934040a39fd5fa1e0
Author: Peter Crosthwaite <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
arm/xilinx_zynq: Always instantiate the GEMs
Don't conditionalise GEM instantiation on networking attachments. The
device should always be present even if not attached to a network.
This allows for probing of the device by expectant guests (such as
OS's). This is needed because sysbus (or AXI in Xilinx's real hw case)
is not self identifying so the guest has no dynamic way of detecting
device absence.
Also allows for testing of the GEM in loopback mode with -net none.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7b1aa025bdd8a62b203eb0a936e20af424fa2870
https://github.com/qemu/qemu/commit/7b1aa025bdd8a62b203eb0a936e20af424fa2870
Author: Michael S. Tsirkin <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/cpu64.c
Log Message:
-----------
target-arm: fix build with gcc 4.8.2
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CC aarch64-softmmu/target-arm/cpu64.o
/scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’:
/scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned
expression < 0 is always false [-Werror=type-limits]
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) {
^
cc1: all warnings being treated as errors
This is the result of ARRAY_SIZE being an unsigned type,
causing "i" to be promoted to unsigned int as well.
As zero size arrays are a gcc extension, it seems
cleanest to add a dummy element with NULL name,
and test for it during registration.
We'll be able to drop this when we add more CPUs.
Cc: Alexander Graf <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Richard Henderson <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Stefan Weil <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 04050c5c6aa6f9c086a63a30b182b996fb2d3d02
https://github.com/qemu/qemu/commit/04050c5c6aa6f9c086a63a30b182b996fb2d3d02
Author: Christoffer Dall <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/gic_internal.h
M include/hw/intc/arm_gic_common.h
Log Message:
-----------
arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to
make the code comprehensible without looking up the data structure.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9df90ad078ec782d1339bd6879b6ea117f9759f7
https://github.com/qemu/qemu/commit/9df90ad078ec782d1339bd6879b6ea117f9759f7
Author: Christoffer Dall <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M hw/intc/arm_gic.c
M hw/intc/gic_internal.h
Log Message:
-----------
hw: arm_gic: Introduce gic_set_priority function
To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this function to set the priority of
interrupts.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 38970efafdfa8a992c177563c4f0d77062b88fd9
https://github.com/qemu/qemu/commit/38970efafdfa8a992c177563c4f0d77062b88fd9
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix exception flag handling for float32_to_float16()
Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the right set of exception
flags. Fix this, mostly by rearranging the code to more closely
resemble RoundAndPackFloat*, and in particular:
* non-IEEE halfprec always raises Invalid for input NaNs
* we need to check for the overflow case before underflow
* we weren't getting the tininess-detected-after-rounding
case correct (somewhat academic since only ARM uses halfprec
and it is always tininess-detected-before-rounding)
* non-IEEE halfprec overflow raises only Invalid, not
Invalid + Inexact
* we weren't setting Inexact when we should
Also add some clarifying comments about what the code is doing.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: f581bf5474d2319ca37484eb63208017ac96ce0a
https://github.com/qemu/qemu/commit/f581bf5474d2319ca37484eb63208017ac96ce0a
Author: Will Newton <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float to 16bit integer conversions.
ARMv8 requires support for converting 32 and 64bit floating point
values to signed and unsigned 16bit integers.
Signed-off-by: Will Newton <address@hidden>
[PMM: updated not to incorrectly set Inexact for Invalid inputs]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 8afbdabac2a1bdc137691c46965ef8c490cb5e44
https://github.com/qemu/qemu/commit/8afbdabac2a1bdc137691c46965ef8c490cb5e44
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add 16 bit integer to float conversions
Add the float to 16 bit integer conversion routines. These can be
trivially implemented in terms of the int32_to_float* routines, but
providing them makes our API more symmetrical and can simplify callers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: c4850f9e1b9cef2ac35cd6e6f3d8d2147787740c
https://github.com/qemu/qemu/commit/c4850f9e1b9cef2ac35cd6e6f3d8d2147787740c
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Make the int-to-float functions take exact-width types
Currently the int-to-float functions take types which are specified
as "at least X bits wide", rather than "exactly X bits wide". This is
confusing and unhelpful since it means that the callers have to include
an explicit cast to [u]intXX_t to ensure the correct behaviour. Fix
them all to take the exactly-X-bits-wide types instead.
Note that this doesn't change behaviour at all since at the moment
we happen to define the 'int32' and 'uint32' types as exactly 32 bits
wide, and the 'int64' and 'uint64' types as exactly 64 bits wide.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: fb3ea83aa53cead46465c74ddd1872babe9f4a3e
https://github.com/qemu/qemu/commit/fb3ea83aa53cead46465c74ddd1872babe9f4a3e
Author: Tom Musta <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix float64_to_uint64
The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed, the case.
This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 34e1c27bc3094ffe484d9855e07ad104bddf579f
https://github.com/qemu/qemu/commit/34e1c27bc3094ffe484d9855e07ad104bddf579f
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Only raise Invalid when conversions to int are out of range
We implement a number of float-to-integer conversions using conversion
to an integer type with a wider range and then a check against the
narrower range we are actually converting to. If we find the result to
be out of range we correctly raise the Invalid exception, but we must
also suppress other exceptions which might have been raised by the
conversion function we called.
This won't throw away exceptions we should have preserved, because for
the 'core' exception flags the IEEE spec mandates that the only valid
combinations of exception that can be raised by a single operation are
Inexact + Overflow and Inexact + Underflow. For the non-IEEE softfloat
flag for input denormals, we can guarantee that that flag won't have
been set for out of range float-to-int conversions because a squashed
denormal by definition goes to plus or minus zero, which is always in
range after conversion to integer zero.
This bug has been fixed for some of the float-to-int conversion routines
by previous patches; fix it for the remaining functions as well, so
that they all restore the pre-conversion status flags prior to raising
Invalid.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 3c85c37f254bdfaea4e105b5014a287b5cf9514b
https://github.com/qemu/qemu/commit/3c85c37f254bdfaea4e105b5014a287b5cf9514b
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix factor 2 error for scalbn on denormal inputs
If the input to float*_scalbn() is denormal then it represents
a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual
exponent field is all zeroes). This means that when we convert
it to our unpacked encoding the unpacked exponent must be one
greater than for a normal number, which represents
1.[mantissabits] * 2^(e-exponentbias) for an exponent field e.
This meant we were giving answers too small by a factor of 2 for
all denormal inputs.
Note that the float-to-int routines also have this behaviour
of not adjusting the exponent for denormals; however there it is
harmless because denormals will all convert to integer zero anyway.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 2f18bbf9844ad110e0e69ad22708f37cab1557f6
https://github.com/qemu/qemu/commit/2f18bbf9844ad110e0e69ad22708f37cab1557f6
Author: Tom Musta <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float32_to_uint64()
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
[PMM: removed harmless but silly int64_t casts]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 0a87a3107dad97abff5b06558b0cce6832229086
https://github.com/qemu/qemu/commit/0a87a3107dad97abff5b06558b0cce6832229086
Author: Tom Musta <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix float64_to_uint64_round_to_zero
The float64_to_uint64_round_to_zero routine is incorrect.
For example, the following test pattern:
46697351FF4AEC29 / 0x1.97351ff4aec29p+103
currently produces 8000000000000000 instead of FFFFFFFFFFFFFFFF.
This patch re-implements the routine to temporarily force the
rounding mode and use the float64_to_uint64 routine.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 5e7f654fa152de246f2254707bacac31ba50c660
https://github.com/qemu/qemu/commit/5e7f654fa152de246f2254707bacac31ba50c660
Author: Tom Musta <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix float64_to_uint32
The float64_to_uint32 has several flaws:
- for numbers between 2**32 and 2**64, the inexact exception flag
may get incorrectly set. In this case, only the invalid flag
should be set.
test pattern: 425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
- for numbers between 2**63 and 2**64, incorrect results may
be produced:
test pattern: 43EAAF73F1F0B8BD / 0x1.aaf73f1f0b8bdp+63
This patch re-implements float64_to_uint32 to re-use the
float64_to_uint64 routine (instead of float64_to_int64). For the
saturation case, we ignore any flags which the conversion routine
has set and raise only the invalid flag.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: fd728f2f949273563f799640b863b4b94dc4c6da
https://github.com/qemu/qemu/commit/fd728f2f949273563f799640b863b4b94dc4c6da
Author: Tom Musta <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Fix float64_to_uint32_round_to_zero
The float64_to_uint32_round_to_zero routine is incorrect.
For example, the following test pattern:
425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
will erroneously set the inexact flag.
This patch re-implements the routine to use the float64_to_uint64_round_to_zero
routine. If saturation occurs we ignore any flags set by the
conversion function and raise only Invalid.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 879d096b37b1233fec334bc2c2f569ac3b8fec9a
https://github.com/qemu/qemu/commit/879d096b37b1233fec334bc2c2f569ac3b8fec9a
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Provide complete set of accessors for fp state
Tidy up the get/set accessors for the fp state to add missing ones
and make them all inline in softfloat.h rather than some inline and
some not.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: c4a1c5e7e2fae28ef3fde2aadf7ec6fed0a5a967
https://github.com/qemu/qemu/commit/c4a1c5e7e2fae28ef3fde2aadf7ec6fed0a5a967
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float16<=>float32
conversion functions into functions RoundAndPackFloat16 and
NormalizeFloat16Subnormal along the lines of the existing versions
for the other float types.
Note that we change the handling of zExp from the inline code
to match the API of the other RoundAndPackFloat functions; however
we leave the positioning of the binary point between bits 22 and 23
rather than shifting it up to the high end of the word.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 14c9a07eb9cae3d3bc1d39cc8815dd88337ce07a
https://github.com/qemu/qemu/commit/14c9a07eb9cae3d3bc1d39cc8815dd88337ce07a
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add float16 <=> float64 conversion functions
Add the conversion functions float16_to_float64() and
float64_to_float16(), which will be needed for the ARM
A64 instruction set.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: dc355b764de890e1b5872d0b402dccfd9a9b5286
https://github.com/qemu/qemu/commit/dc355b764de890e1b5872d0b402dccfd9a9b5286
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
softfloat: Refactor code handling various rounding modes
Refactor the code in various functions which calculates rounding
increments given the current rounding mode, so that instead of a
set of nested if statements we have a simple switch statement.
This will give us a clean place to add the case for the new
tiesAway rounding mode.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: f9288a76f1819c2dbf8d2873aebab6aec0f461f5
https://github.com/qemu/qemu/commit/f9288a76f1819c2dbf8d2873aebab6aec0f461f5
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add support for ties-away rounding
IEEE754-2008 specifies a new rounding mode:
"roundTiesToAway: the floating-point number nearest to the infinitely
precise result shall be delivered; if the two nearest floating-point
numbers bracketing an unrepresentable infinitely precise result are
equally near, the one with larger magnitude shall be delivered."
Implement this new mode (it is needed for ARM). The general principle
is that the required code is exactly like the ties-to-even code,
except that we do not need to do the "in case of exact tie clear LSB
to round-to-even", because the rounding operation naturally causes
the exact tie to round up in magnitude.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 8ed697e88b7ead01edca6bf762921b962c265c82
https://github.com/qemu/qemu/commit/8ed697e88b7ead01edca6bf762921b962c265c82
Author: Will Newton <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
* use the correct softfloat conversion function based on itype
rather than always the int32 one; this is possible now that
softfloat provides int16 versions and necessary for the
future conversion-to-int64 A64 variants. This also allows
us to drop the awkward 'sign' macro argument.
* split the 'fsz' argument which currently controls both
width of the input float type and width of the output
integer type into two; this will allow us to specify the
A64 64-bit-int-to-single conversion function, where the
two widths are different.
We can also drop the (itype##_t) cast now that softfloat
guarantees that all the itype##_to_float* functions take
an integer argument of exactly the correct type.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 16d5b3caca11360fd1d706403221c7bef40aa6f6
https://github.com/qemu/qemu/commit/16d5b3caca11360fd1d706403221c7bef40aa6f6
Author: Will Newton <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
M target-arm/helper.h
M target-arm/translate.c
Log Message:
-----------
target-arm: Rename A32 VFP conversion helpers
The VFP conversion helpers for A32 round to zero as this is the only
rounding mode supported. Rename these helpers to make it clear that
they round to zero and are not suitable for use in the AArch64 code.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: abe66f702cac88fd6b1ccdca5d6f0c57f814ab0f
https://github.com/qemu/qemu/commit/abe66f702cac88fd6b1ccdca5d6f0c57f814ab0f
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
Log Message:
-----------
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
The VFP fixed point conversion helpers first call float_scalbn and
then convert the result to an integer. This scalbn operation may
set floating point exception flags for:
* overflow & inexact (if it overflows to infinity)
* input denormal squashed to zero
* output denormal squashed to zero
Of these, we only care about the input-denormal flag, since
the output of the whole scale-and-convert operation will be
an integer (so squashed-output-denormal and overflow don't
apply). Suppress the others by saving the pre-scalb exception
flags and only copying across a potential input-denormal flag.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 3c6a074a08ed3797624d4fb667564b9f3487eeaa
https://github.com/qemu/qemu/commit/3c6a074a08ed3797624d4fb667564b9f3487eeaa
Author: Will Newton <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
M target-arm/helper.h
Log Message:
-----------
target-arm: A64: Add extra VFP fixed point conversion helpers
Define the full set of floating point to fixed point conversion
helpers required to support AArch64.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 52a1f6a3abb88ab875d5a70cec1048bb05e47263
https://github.com/qemu/qemu/commit/52a1f6a3abb88ab875d5a70cec1048bb05e47263
Author: Alexander Graf <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
M target-arm/helper.h
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add floating-point<->fixed-point instructions
This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, rebased, updated to new infrastructure.
Applied bug fixes from Michael Matz and Janne Grunau.]
Signed-off-by: Will Newton <address@hidden>
[PMM: significant cleanup]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: c436d40614ccfa756bbf3d7448356889ede825fb
https://github.com/qemu/qemu/commit/c436d40614ccfa756bbf3d7448356889ede825fb
Author: Will Newton <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add floating-point<->integer conversion instructions
Add support for the AArch64 floating-point <-> integer conversion
instructions to disas_fpintconv. In the process we can rearrange
and simplify the detection of unallocated encodings a little.
We also correct a typo in the instruction encoding diagram for this
instruction group: bit 21 is 1, not 0.
Signed-off-by: Will Newton <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: d9b0848d944aab124f03cedc8f54c3940450f3b0
https://github.com/qemu/qemu/commit/d9b0848d944aab124f03cedc8f54c3940450f3b0
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
M target-arm/helper.h
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
This patch adds support for those instructions in the "Floating-point
data-processing (1 source)" group which are simple 32-bit-to-32-bit
or 64-bit-to-64-bit operations (ie everything except FCVT between
single/double/half precision).
We put the new round-to-int helpers in helper.c because they will
also be used by the new ARMv8 A32/T32 rounding instructions.
Signed-off-by: Alexander Graf <address@hidden>
[WN: Commit message tweak, merged single and double precision patches,
updated to new infrastructure.]
Signed-off-by: Will Newton <address@hidden>
[PMM: reworked decode, split FCVT out into their own patch]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: 8900aad218f8f2348bcd688eacf06d6c1f66bc69
https://github.com/qemu/qemu/commit/8900aad218f8f2348bcd688eacf06d6c1f66bc69
Author: Peter Maydell <address@hidden>
Date: 2014-01-08 (Wed, 08 Jan 2014)
Changed paths:
M target-arm/helper.c
M target-arm/helper.h
M target-arm/translate-a64.c
Log Message:
-----------
target-arm: A64: Add support for FCVT between half, single and double
Add support for FCVT between half, single and double precision.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Commit: b61740dbef8d1c8fda8a0f46ecb617e6e865e9e2
https://github.com/qemu/qemu/commit/b61740dbef8d1c8fda8a0f46ecb617e6e865e9e2
Author: Anthony Liguori <address@hidden>
Date: 2014-01-09 (Thu, 09 Jan 2014)
Changed paths:
M .travis.yml
A default-configs/aarch64-linux-user.mak
M fpu/softfloat.c
M hw/arm/xilinx_zynq.c
M hw/char/cadence_uart.c
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/gic_internal.h
M include/fpu/softfloat.h
M include/hw/intc/arm_gic_common.h
M linux-user/aarch64/syscall.h
M linux-user/aarch64/target_cpu.h
M linux-user/arm/target_cpu.h
M linux-user/main.c
M linux-user/signal.c
M target-arm/cpu.h
M target-arm/cpu64.c
M target-arm/helper-a64.c
M target-arm/helper-a64.h
M target-arm/helper.c
M target-arm/helper.h
M target-arm/kvm-consts.h
M target-arm/machine.c
M target-arm/neon_helper.c
M target-arm/translate-a64.c
M target-arm/translate.c
M target-arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140108' into
staging
target-arm queue:
* further A64 decoder patches, including enabling the aarch64-linux-user
target; this includes full floating point support. Neon is not yet
supported.
* cadence UART model fixes.
* some minor bug fixes and cleanups.
* all the softfloat fixes required by the new A64 instructions;
several of these will also be used by PPC.
# gpg: Signature made Wed 08 Jan 2014 11:25:12 AM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
* pmaydell/tags/pull-target-arm-20140108: (76 commits)
target-arm: A64: Add support for FCVT between half, single and double
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
target-arm: A64: Add floating-point<->integer conversion instructions
target-arm: A64: Add floating-point<->fixed-point instructions
target-arm: A64: Add extra VFP fixed point conversion helpers
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
target-arm: Rename A32 VFP conversion helpers
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
softfloat: Add support for ties-away rounding
softfloat: Refactor code handling various rounding modes
softfloat: Add float16 <=> float64 conversion functions
softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
softfloat: Provide complete set of accessors for fp state
softfloat: Fix float64_to_uint32_round_to_zero
softfloat: Fix float64_to_uint32
softfloat: Fix float64_to_uint64_round_to_zero
softfloat: Add float32_to_uint64()
softfloat: Fix factor 2 error for scalbn on denormal inputs
softfloat: Only raise Invalid when conversions to int are out of range
softfloat: Fix float64_to_uint64
...
Message-id: address@hidden
Signed-off-by: Anthony Liguori <address@hidden>
Commit: 666eb032d34961a06713049c56361179903527e4
https://github.com/qemu/qemu/commit/666eb032d34961a06713049c56361179903527e4
Author: Anthony Liguori <address@hidden>
Date: 2014-01-09 (Thu, 09 Jan 2014)
Changed paths:
M configure
M hw/arm/highbank.c
M hw/arm/mainstone.c
M hw/arm/z2.c
M hw/audio/intel-hda.c
M hw/char/exynos4210_uart.c
M hw/input/pxa2xx_keypad.c
M hw/misc/exynos4210_pmu.c
M include/hw/arm/pxa.h
M linux-user/signal.c
M net/net.c
M qemu-char.c
M qemu-options.hx
M target-i386/helper.c
M target-openrisc/translate.c
M tests/acpi-test.c
M ui/cocoa.m
M vl.c
Log Message:
-----------
Merge remote-tracking branch 'mjt/trivial-patches' into staging
* mjt/trivial-patches:
acpi unit-test: Remove temporary disk after test
mainstone: Fix duplicate array values for key 'space'
pxa27x: Add 'const' attribute to keyboard maps
pxa27x: Reduce size of keyboard matrix mapping
doc: Mention chardev:id in available devices for -serial
configure: Python tests must be done before help message
configure: Rewrite code for help message
fix -boot strict regressed in commit 6ef4716
vl: make boot_strict variable static (not used outside vl.c)
x86: only allow real mode to access 32bit without LMA
linux-user: Use macro TARGET_NSIG_WORDS where possible
exynos4210: Use macro ARRAY_SIZE where possible
ui/cocoa: Use macro ARRAY_SIZE where possible
misc: Use macro ARRAY_SIZE where possible
openrisc: Fix spelling in comment (transaltion -> translation)
hw/arm/highbank: Simplify code (memory region in device state)
Message-id: address@hidden
Signed-off-by: Anthony Liguori <address@hidden>
Commit: c06f13c6da306180e9531114570d7800357f7446
https://github.com/qemu/qemu/commit/c06f13c6da306180e9531114570d7800357f7446
Author: Anthony Liguori <address@hidden>
Date: 2014-01-09 (Thu, 09 Jan 2014)
Changed paths:
M hw/acpi/piix4.c
M hw/alpha/typhoon.c
M hw/arm/versatilepb.c
M hw/audio/marvell_88w8618.c
M hw/audio/pcspk.c
M hw/audio/pl041.c
M hw/block/fdc.c
M hw/core/qdev.c
M hw/core/sysbus.c
M hw/cpu/icc_bus.c
M hw/display/pl110.c
M hw/dma/pl080.c
M hw/dma/sparc32_dma.c
M hw/gpio/omap_gpio.c
M hw/i2c/omap_i2c.c
M hw/i2c/smbus_eeprom.c
M hw/i2c/smbus_ich9.c
M hw/i386/kvm/apic.c
M hw/i386/kvm/clock.c
M hw/i386/kvm/ioapic.c
M hw/i386/kvmvapic.c
M hw/i386/pc.c
M hw/ide/piix.c
M hw/ide/via.c
M hw/input/pckbd.c
M hw/input/vmmouse.c
M hw/intc/apic.c
M hw/intc/apic_common.c
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M hw/intc/arm_gic_kvm.c
M hw/intc/etraxfs_pic.c
M hw/intc/grlib_irqmp.c
M hw/intc/i8259_common.c
M hw/intc/ioapic.c
M hw/intc/ioapic_common.c
M hw/intc/omap_intc.c
M hw/intc/pl190.c
M hw/isa/isa-bus.c
M hw/isa/lpc_ich9.c
M hw/isa/piix4.c
M hw/isa/vt82c686.c
M hw/mips/gt64xxx_pci.c
M hw/misc/arm_l2x0.c
M hw/misc/vmport.c
M hw/net/etraxfs_eth.c
M hw/net/lance.c
M hw/nvram/fw_cfg.c
M hw/pci-bridge/dec.c
M hw/pci-host/apb.c
M hw/pci-host/bonito.c
M hw/pci-host/grackle.c
M hw/pci-host/piix.c
M hw/pci-host/ppce500.c
M hw/pci-host/prep.c
M hw/pci-host/q35.c
M hw/pci-host/uninorth.c
M hw/pci-host/versatile.c
M hw/pci/pci_bridge.c
M hw/ppc/ppc4xx_pci.c
M hw/ppc/spapr_vio.c
M hw/s390x/ipl.c
M hw/s390x/s390-virtio-bus.c
M hw/s390x/virtio-ccw.c
M hw/sd/pl181.c
M hw/sh4/sh_pci.c
M hw/timer/arm_mptimer.c
M hw/timer/hpet.c
M hw/timer/i8254_common.c
M hw/timer/m48t59.c
M hw/timer/mc146818rtc.c
M hw/timer/pl031.c
M hw/xen/xen_apic.c
M include/hw/cpu/icc_bus.h
M include/hw/i386/apic_internal.h
M include/hw/i386/ioapic_internal.h
M include/hw/qdev-core.h
M include/hw/qdev-properties.h
M include/qom/object.h
M qdev-monitor.c
M qom/cpu.c
M qom/object.c
M tests/Makefile
A tests/check-qom-interface.c
Log Message:
-----------
Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into
staging
QOM infrastructure fixes and device conversions
* QOM interface fixes and unit test
* Device no_user sanitization and documentation
* Device error reporting improvement
* Conversion of APIC, ICC, IOAPIC to QOM realization model
# gpg: Signature made Tue 24 Dec 2013 09:04:05 AM PST using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <address@hidden>"
# gpg: aka "Andreas Färber <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F
* afaerber/tags/qom-devices-for-anthony: (24 commits)
qdev-monitor: Improve error message for -device nonexistant
ioapic: QOM'ify ioapic
ioapic: Cleanup for QOM'ification
icc_bus: QOM'ify ICC
apic: QOM'ify APIC
apic: Cleanup for QOM'ification
qdev: Drop misleading qbus_free() function
qom: Detect bad reentrance during object_class_foreach()
tests: Test QOM interface casting
qom: Do not register interface "types" in the type table and fix names
qom: Split out object and class caches
qdev: Document that pointer properties kill device_add
hw: cannot_instantiate_with_device_add_yet due to pointer props
qdev-monitor: Avoid device_add crashing on non-device driver name
qdev: Do not let the user try to device_add when it cannot work
isa: Clean up use of cannot_instantiate_with_device_add_yet
vt82c686: Clean up use of cannot_instantiate_with_device_add_yet
piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet
ich9: Document why cannot_instantiate_with_device_add_yet
pci-host: Consistently set cannot_instantiate_with_device_add_yet
...
Compare: https://github.com/qemu/qemu/compare/f976b09ea249...c06f13c6da30
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] efec3d: qdev: Replace no_user by cannot_instantiate_with_d...,
GitHub <=