[Qemu-commits] [qemu/qemu] c65f9a: target-ppc: add stubs for KVM breakpo

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[Qemu-commits] [qemu/qemu] c65f9a: target-ppc: add stubs for KVM breakpo

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] c65f9a: target-ppc: add stubs for KVM breakpoints
Date:	Thu, 19 Dec 2013 17:30:11 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c65f9a07a78afa3c98712f6192962ffd6babe339
      
https://github.com/qemu/qemu/commit/c65f9a07a78afa3c98712f6192962ffd6babe339
  Author: Greg Kurz <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/kvm.c

  Log Message:
  -----------
  target-ppc: add stubs for KVM breakpoints

The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:

kvm-all.o: In function `kvm_update_guest_debug':
kvm-all.c:1910: undefined reference to `kvm_arch_update_guest_debug'
kvm-all.o: In function `kvm_insert_breakpoint':
kvm-all.c:1937: undefined reference to `kvm_arch_insert_sw_breakpoint'
kvm-all.c:1945: undefined reference to `kvm_arch_insert_hw_breakpoint'
kvm-all.o: In function `kvm_remove_breakpoint':
kvm-all.c:1977: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:1985: undefined reference to `kvm_arch_remove_hw_breakpoint'
kvm-all.o: In function `kvm_remove_all_breakpoints':
kvm-all.c:2009: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2006: undefined reference to `kvm_arch_remove_sw_breakpoint'
kvm-all.c:2017: undefined reference to `kvm_arch_remove_all_hw_breakpoints'

We need stubs until something gets implemented.

Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Alexander Graf <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3bc9ccc054574820190f0e6bbfd299bc2d42323d
      
https://github.com/qemu/qemu/commit/3bc9ccc054574820190f0e6bbfd299bc2d42323d
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu-qom.h
    M target-ppc/kvm.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  powerpc: add PVR mask support

IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of already supported
CPU won't break the existing code.

This adds PVR value/mask support for KVM, i.e. for -cpu host option.

As CPU family class name for POWER7 is "POWER7-family", there is no need
to touch aliases.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 74f239975501cf0ad886a5d40ce40aecbb9dc0b2
      
https://github.com/qemu/qemu/commit/74f239975501cf0ad886a5d40ce40aecbb9dc0b2
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Declare and Enable VSX

This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of supported features of
the Power7 and Power8 CPUs.  Additionally, the VSX instructions
are added to the list of TCG-enabled instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 1f29871cb7518692cf5c1fa8c19b117c789ff7f0
      
https://github.com/qemu/qemu/commit/1f29871cb7518692cf5c1fa8c19b117c789ff7f0
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Add MSR VSX and Associated Exception

This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.

The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f9fc6d810f6777a253337ba050639d266e9a3538
      
https://github.com/qemu/qemu/commit/f9fc6d810f6777a253337ba050639d266e9a3538
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add VSX Instruction Decoders

This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM.  The first four are split fields and a general helper for
these types of fields is also added.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 472b24ce2b4f22363ec9a556e479be6ad5180727
      
https://github.com/qemu/qemu/commit/472b24ce2b4f22363ec9a556e479be6ad5180727
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add VSR to Global Registers

This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices.  The upper halves of the first
32 VSRs are already defined via cpu_fpr[].  And the second 32 VSRs
are already defined via the cpu_avrh[] and cpu_avrl[] arrays.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 304af367427301697df32112c50448b7d55c7054
      
https://github.com/qemu/qemu/commit/304af367427301697df32112c50448b7d55c7054
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add lxvd2x

This patch adds the lxvd2x instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: fbed2478e9ba22f091e3842123252a902dc5b98d
      
https://github.com/qemu/qemu/commit/fbed2478e9ba22f091e3842123252a902dc5b98d
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add stxvd2x

This patch adds the stxvd2x instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: cd73f2c992765141b3497551ebdf841b26c238ca
      
https://github.com/qemu/qemu/commit/cd73f2c992765141b3497551ebdf841b26c238ca
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add xxpermdi

This patch adds the xxpermdi instruction.  The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
and BX).  This results in overloading of the opcode table
with aliases, which can be seen in the GEN_XX3FORM_DM
macro.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Anton Blanchard <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: fa1832d7e2fccfe3ea55d2885c023daa285342d4
      
https://github.com/qemu/qemu/commit/fa1832d7e2fccfe3ea55d2885c023daa285342d4
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add lxsdx

This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.

The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ca03b46765d4633f5746764696058b0cb33ac487
      
https://github.com/qemu/qemu/commit/ca03b46765d4633f5746764696058b0cb33ac487
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add lxvdsx

This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 897e61d13777a5995d3cd12fcaf44eb4bbb5439c
      
https://github.com/qemu/qemu/commit/897e61d13777a5995d3cd12fcaf44eb4bbb5439c
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add lxvw4x

This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.

V2: changed to use deposit_i64 per Richard Henderson's review.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 9231ba9ee9c7d68364a28657109d2f7c32e12971
      
https://github.com/qemu/qemu/commit/9231ba9ee9c7d68364a28657109d2f7c32e12971
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add stxsdx

This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 86e61ce3d0e4806519c79f2555f20b7b3283bdab
      
https://github.com/qemu/qemu/commit/86e61ce3d0e4806519c79f2555f20b7b3283bdab
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add stxvw4x

This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: b650d6a2fcb77e2e42872ebd102ba387d547ab77
      
https://github.com/qemu/qemu/commit/b650d6a2fcb77e2e42872ebd102ba387d547ab77
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/translate_init.c

  Log Message:
  -----------
  target-ppc: move POWER7+ to a separate family

So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR masks, it needs a separate
family class.

This adds a new family class, PVR base and mask values and moves
Power7+ v2.1 CPU to a new family. The class init function is copied
from the POWER7 family.

This defines a firmware name for the new family as "PowerPC,POWER7+"
instead of previously used "PowerPC,POWER7" from the POWER7 family.
The reason for that is that the Sapphire firmware (a h0st firmware)
uses "PowerPC,POWER7+" already and since no specification defines
exactly the CPU nodes naming in the device tree, we better stay
in sync with the host firmware.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: a64d325df1ce9b554e15d612b80775159cc4d7a6
      
https://github.com/qemu/qemu/commit/a64d325df1ce9b554e15d612b80775159cc4d7a6
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M hw/intc/xics.c
    M hw/nvram/spapr_nvram.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr-rtas: replace return code constants with macros

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3ada6b113726ae554154f6e5367bf4b4ed110bbe
      
https://github.com/qemu/qemu/commit/3ada6b113726ae554154f6e5367bf4b4ed110bbe
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M hw/ppc/spapr_rtas.c
    M include/hw/ppc/spapr.h

  Log Message:
  -----------
  spapr-rtas: add ibm, (get|set)-system-parameter

This adds very basic handlers for ibm,get-system-parameter and
ibm,set-system-parameter RTAS calls.

The only parameter handled at the moment is
"platform-processor-diagnostics-run-mode" which is always disabled and
does not support changing. This is expected to make
"ppc64_cpu --run-mode=1" happy.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
[agraf: s/papameter/parameter/g]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 8a0e11045d5f50d300e0ab1ba05f4c8217fb5dcb
      
https://github.com/qemu/qemu/commit/8a0e11045d5f50d300e0ab1ba05f4c8217fb5dcb
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M hw/pci-host/grackle.c
    M hw/pci-host/uninorth.c

  Log Message:
  -----------
  PPC: Use default pci bus name for grackle and heathrow

There's no good reason to call our bus "pci" rather than let the default
bus name take over ("pci.0").

The big downside to calling it different from anyone else is that tools
that pass -device get confused. They are looking for a bus "pci.0" rather
than "pci".

To make life easier for everyone, let's just drop the name override.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 3978b863a5d8ac1c02848bf57d0a7f7067826a8a
      
https://github.com/qemu/qemu/commit/3978b863a5d8ac1c02848bf57d0a7f7067826a8a
  Author: Paolo Bonzini <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: tie spapr-nvram to -pflash

spapr-nvram's drive property is currently connected to a non-existent
"-machine nvram=<drivename>" option.  Instead, tie it to -pflash like
other non-volatile RAM devices.  This provides the following possibilities
for adding a backend for the sPAPR non-volatile RAM:

* -pflash filename

* -drive if=pflash,file=filename,format=raw,...

* -drive if=none,file=filename,format=raw,id=foo,... -global 
spapr-nvram.drive=foo

Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 582b55a96ac4f66cea64d82e47651bd5ef38a8ec
      
https://github.com/qemu/qemu/commit/582b55a96ac4f66cea64d82e47651bd5ef38a8ec
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M exec.c
    M hw/core/loader.c
    M include/exec/cpu-common.h

  Log Message:
  -----------
  roms: Flush icache when writing roms to guest memory

We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.

That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to ensure that after reboot we
don't happen to execute stale bits from the instruction cache.

So we need to invalidate the icache every time we write a rom into guest
address space. We do not need to do this for every DMA since the guest
expects it has to flush the icache manually in that case.

This fixes random reboot issues on e5500 (booke ppc) for me.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: df020ce07045413ab3205916a3cde64bb150694c
      
https://github.com/qemu/qemu/commit/df020ce07045413ab3205916a3cde64bb150694c
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add VSX Scalar Move Instructions

This patch adds the VSX scalar move instructions:

  - xsabsdp (Scalar Absolute Value Double-Precision)
  - xsnabspd (Scalar Negative Absolute Value Double-Precision)
  - xsnegdp (Scalar Negate Double-Precision)
  - xscpsgndp (Scalar Copy Sign Double-Precision)

A common generator macro (VSX_SCALAR_MOVE) is added since these
instructions vary only slightly from each other.

Macros to support VSX XX2 and XX3 form opcodes are also added.
These macros handle the overloading of "opcode 2" space (instruction
bits 26:30) caused by AX and BX bits (29 and 30, respectively).

V3: Per feedback from Paolo Bonzini, moved the sign mask into a
temporary and used andc.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: be574920b1285c0505ad116795d3a646422a1b8e
      
https://github.com/qemu/qemu/commit/be574920b1285c0505ad116795d3a646422a1b8e
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add VSX Vector Move Instructions

This patch adds the vector move instructions:

  - xvabsdp - Vector Absolute Value Double-Precision
  - xvnabsdp - Vector Negative Absolute Value Double-Precision
  - xvnegdp - Vector Negate Double-Precision
  - xvcpsgndp - Vector Copy Sign Double-Precision
  - xvabssp - Vector Absolute Value Single-Precision
  - xvnabssp - Vector Negative Absolute Value Single-Precision
  - xvnegsp - Vector Negate Single-Precision
  - xvcpsgnsp - Vector Copy Sign Single-Precision

V3: Per Paolo Bonzini's suggestion, used a temporary for the
sign mask and andc.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 79ca8a6a76517edb4f54793c638259b9e6dfce66
      
https://github.com/qemu/qemu/commit/79ca8a6a76517edb4f54793c638259b9e6dfce66
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add Power7 VSX Logical Instructions

This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):

   - xxland
   - xxlandc
   - xxlor
   - xxlxor
   - xxlnor

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: ce577d2e48e756f17d4c4a6c6bdc96924a157ca0
      
https://github.com/qemu/qemu/commit/ce577d2e48e756f17d4c4a6c6bdc96924a157ca0
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add xxmrgh/xxmrgl

This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.

V2: Now implemented using deposit (per Richard Henderson's comment)

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 551e3ef72e59d3975073e2ea3aaf2f7508323063
      
https://github.com/qemu/qemu/commit/551e3ef72e59d3975073e2ea3aaf2f7508323063
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add xxsel

This patch adds the VSX Select (xxsel) instruction.

The xxsel instruction has four VSR operands.  Thus the xC
instruction decoder is added.

The xxsel instruction is massively overloaded in the opcode
table since only bits 26 and 27 are opcode bits.  This
overloading is done in matrix fashion with two macros
(GEN_XXSEL_ROW and GEN_XX_SEL).

V2: (1) eliminated unecessary XXSEL macro  (2) tighter implementation
using tcg_gen_andc_i64.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 76c15fe0bdaa5b0c4b458c2b291e27a24494a77f
      
https://github.com/qemu/qemu/commit/76c15fe0bdaa5b0c4b458c2b291e27a24494a77f
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add xxspltw

This patch adds the VSX Splat Word (xxsplatw) instruction.

This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.

V2: reworked implementation per Richard Henderson's comments.

Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: acc429682c71968b8aef37822879dda3b54dda96
      
https://github.com/qemu/qemu/commit/acc429682c71968b8aef37822879dda3b54dda96
  Author: Tom Musta <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/translate.c

  Log Message:
  -----------
  Add xxsldwi

This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.

Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c2b63f03977a84d0584d82be6981e4eb5f4faacd
      
https://github.com/qemu/qemu/commit/c2b63f03977a84d0584d82be6981e4eb5f4faacd
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M target-ppc/helper_regs.h

  Log Message:
  -----------
  PPC: Add VSX to hflags

We generate different code depending on whether MSR_VSX is set or
clear, so it needs to be part of our hflags too which indicate whether
we're still in the same translation block cache bucket.

Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5a4348d1114b7f3dccc578e39e33ef07a1cfabc7
      
https://github.com/qemu/qemu/commit/5a4348d1114b7f3dccc578e39e33ef07a1cfabc7
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M device_tree.c
    M hw/arm/boot.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/microblaze/boot.c
    M hw/ppc/e500.c
    M hw/ppc/e500plat.c
    M hw/ppc/mpc8544ds.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/virtex_ml507.c
    M include/sysemu/device_tree.h

  Log Message:
  -----------
  device_tree: s/qemu_devtree/qemu_fdt globally

The qemu_devtree API is a wrapper around the fdt_ set of APIs.
Rename accordingly.

Signed-off-by: Peter Crosthwaite <address@hidden>
[agraf: also convert hw/arm/virt.c]
Signed-off-by: Alexander Graf <address@hidden>


  Commit: be5907f2cc6d075b1d687e51a0e0d8ac074a7ac8
      
https://github.com/qemu/qemu/commit/be5907f2cc6d075b1d687e51a0e0d8ac074a7ac8
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M device_tree.c
    M include/sysemu/device_tree.h

  Log Message:
  -----------
  device_tree: qemu_fdt_setprop: Rename val_array arg

Looking at the implementation, this doesn't really have a lot to do
with arrays. Its just a pointer to a buffer and is passed through
to the wrapped fn (qemu_fdt_setprop) unchanged. So rename to make it
consistent with libfdt, which in the wrapped function just calls it
"val".

Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: c4177479069d6d643e0e0f90595795406db7efbf
      
https://github.com/qemu/qemu/commit/c4177479069d6d643e0e0f90595795406db7efbf
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: make sure RMA is in first mode of first memory node

The SPAPR specification says that the RMA starts at the LPAR's logical
address 0 and is the first logical memory block reported in
the LPAR’s device tree.

So SLOF only maps the first block and that block needs to span
the full RMA.

This makes sure that the RMA area is where SLOF expects it.

Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: 5fe269b16c6dc8f19da3e8c13d4c66958b00d2f0
      
https://github.com/qemu/qemu/commit/5fe269b16c6dc8f19da3e8c13d4c66958b00d2f0
  Author: Paul Mackerras <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: limit numa memory regions by ram size

This makes sure that all NUMA memory blocks reside within RAM or
have zero length.

Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>


  Commit: f8251db121c3f051b22a7536b97d160c30bcccd4
      
https://github.com/qemu/qemu/commit/f8251db121c3f051b22a7536b97d160c30bcccd4
  Author: Anthony Liguori <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M device_tree.c
    M exec.c
    M hw/arm/boot.c
    M hw/arm/vexpress.c
    M hw/arm/virt.c
    M hw/core/loader.c
    M hw/intc/xics.c
    M hw/microblaze/boot.c
    M hw/nvram/spapr_nvram.c
    M hw/pci-host/grackle.c
    M hw/pci-host/uninorth.c
    M hw/ppc/e500.c
    M hw/ppc/e500plat.c
    M hw/ppc/mpc8544ds.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_events.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_rtas.c
    M hw/ppc/spapr_vio.c
    M hw/ppc/virtex_ml507.c
    M include/exec/cpu-common.h
    M include/hw/ppc/spapr.h
    M include/sysemu/device_tree.h
    M target-ppc/cpu-models.c
    M target-ppc/cpu-models.h
    M target-ppc/cpu-qom.h
    M target-ppc/cpu.h
    M target-ppc/excp_helper.c
    M target-ppc/helper_regs.h
    M target-ppc/kvm.c
    M target-ppc/translate.c
    M target-ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into staging

Patch queue for ppc - 2013-12-20

Alexander Graf (3):
      PPC: Use default pci bus name for grackle and heathrow
      roms: Flush icache when writing roms to guest memory
      PPC: Add VSX to hflags

Alexey Kardashevskiy (5):
      powerpc: add PVR mask support
      target-ppc: move POWER7+ to a separate family
      spapr-rtas: replace return code constants with macros
      spapr-rtas: add ibm, (get|set)-system-parameter
      spapr: make sure RMA is in first mode of first memory node

Greg Kurz (1):
      target-ppc: add stubs for KVM breakpoints

Paolo Bonzini (1):
      spapr: tie spapr-nvram to -pflash

Paul Mackerras (1):
      spapr: limit numa memory regions by ram size

Peter Crosthwaite (2):
      device_tree: s/qemu_devtree/qemu_fdt globally
      device_tree: qemu_fdt_setprop: Rename val_array arg

Tom Musta (19):
      Declare and Enable VSX
      Add MSR VSX and Associated Exception
      Add VSX Instruction Decoders
      Add VSR to Global Registers
      Add lxvd2x
      Add stxvd2x
      Add xxpermdi
      Add lxsdx
      Add lxvdsx
      Add lxvw4x
      Add stxsdx
      Add stxvw4x
      Add VSX Scalar Move Instructions
      Add VSX Vector Move Instructions
      Add Power7 VSX Logical Instructions
      Add xxmrgh/xxmrgl
      Add xxsel
      Add xxspltw
      Add xxsldwi

* agraf/tags/signed-ppc-for-upstream: (32 commits)
  spapr: limit numa memory regions by ram size
  spapr: make sure RMA is in first mode of first memory node
  device_tree: qemu_fdt_setprop: Rename val_array arg
  device_tree: s/qemu_devtree/qemu_fdt globally
  PPC: Add VSX to hflags
  Add xxsldwi
  Add xxspltw
  Add xxsel
  Add xxmrgh/xxmrgl
  Add Power7 VSX Logical Instructions
  Add VSX Vector Move Instructions
  Add VSX Scalar Move Instructions
  roms: Flush icache when writing roms to guest memory
  spapr: tie spapr-nvram to -pflash
  PPC: Use default pci bus name for grackle and heathrow
  spapr-rtas: add ibm, (get|set)-system-parameter
  spapr-rtas: replace return code constants with macros
  target-ppc: move POWER7+ to a separate family
  Add stxvw4x
  Add stxsdx
  ...


Compare: https://github.com/qemu/qemu/compare/3dc7e2a3feda...f8251db121c3
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