[Qemu-commits] [qemu/qemu] 9d9355: target-arm: add support for v8 AES in

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[Qemu-commits] [qemu/qemu] 9d9355: target-arm: add support for v8 AES in

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 9d9355: target-arm: add support for v8 AES instructions
Date:	Thu, 19 Dec 2013 17:00:07 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 9d935509fdb48e47cc46e81d2b9d466b18b546ba
      
https://github.com/qemu/qemu/commit/9d935509fdb48e47cc46e81d2b9d466b18b546ba
  Author: Ard Biesheuvel <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/Makefile.objs
    M target-arm/cpu.c
    M target-arm/cpu.h
    A target-arm/crypto_helper.c
    M target-arm/helper.h
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: add support for v8 AES instructions

This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.

Signed-off-by: Ard Biesheuvel <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4b6fedcac0f51157ef042cde80d5dc5d0c9ef8a4
      
https://github.com/qemu/qemu/commit/4b6fedcac0f51157ef042cde80d5dc5d0c9ef8a4
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  rename pflash_t member width to bank_width

Rename the 'width' member of the pflash_t structure
in preparation for adding a bank_width member.

Signed-off-by: Roy Franz <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1997b48527c38fe8cdbbb3df82ed79aa3ee88b83
      
https://github.com/qemu/qemu/commit/1997b48527c38fe8cdbbb3df82ed79aa3ee88b83
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  Add device-width property to pflash_cfi01

The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
write length for buffered writes.  This length will be presented
to each device on the interface by the program writing the flash,
and the flash emulation code needs to be able to determine
the length of the write as recieved by each flash device.
The device-width defaults to the bank width which should
maintain existing behavior for platforms that don't need
this change.
This change is required to support buffered writes on the
vexpress platform that has a 32 bit flash interface with 2
16 bit devices on it.

Signed-off-by: Roy Franz <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2003889f67755d47ab355c7813c587adb204eeea
      
https://github.com/qemu/qemu/commit/2003889f67755d47ab355c7813c587adb204eeea
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  return status for each NOR flash device

Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank.  Leave existing code
that treats 32 bit wide banks as composed of two 16 bit devices as otherwise
we may break configurations that do not set the device_width propery.

Signed-off-by: Roy Franz <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8433303fbc5a4a694adb0f0aff5059442ae63e3
      
https://github.com/qemu/qemu/commit/b8433303fbc5a4a694adb0f0aff5059442ae63e3
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/vexpress.c

  Log Message:
  -----------
  Set proper device-width for vexpress flash

Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes) for the NOR flash on the
vexpress platform.  This change is required for
buffered flash writes to work properly.

Signed-off-by: Roy Franz <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fa21a7b13e97120c789eda1dbae87a9bcb1efe09
      
https://github.com/qemu/qemu/commit/fa21a7b13e97120c789eda1dbae87a9bcb1efe09
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  Add max device width parameter for NOR devices

For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width.  The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for.  The most common
case is x16 parts that also support x8 mode.  When configured for x8
operation these devices respond to CFI and device ID requests differently
than native x8 NOR parts.

Signed-off-by: Roy Franz <address@hidden>
Message-id: address@hidden
[PMM: Added comment explaining the semantics of width vs device-width
 vs max-device-width]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4433e660e3ff19747d9ca7fd3873407ecfb276bf
      
https://github.com/qemu/qemu/commit/4433e660e3ff19747d9ca7fd3873407ecfb276bf
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  Fix CFI query responses for NOR flash

This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width.  Support is also
added for multi-width devices in a x8 configuration.  This is
typically x8/x16 devices, but the CFI specification mentions
x8/x32 devices so those should be supported as well if they
exist.
The query response data is now replicated per-device in the bank,
and is adjusted for x16 or x32 parts configured in x8 mode.

The existing code is left in place for boards that have not
been updated to specify an explicit device_width.  The VExpress
board has been updated in an earlier patch in this series so
this is the only board currently affected.

Signed-off-by: Roy Franz <address@hidden>
Message-id: address@hidden
[PMM: fixed a few formatting nits]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0163a2dc80b52553a478fa6e60f09cef4b338d42
      
https://github.com/qemu/qemu/commit/0163a2dc80b52553a478fa6e60f09cef4b338d42
  Author: Roy Franz <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/vexpress.c
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  Fix NOR flash device ID reading

Fix NOR flash manufacturer and device ID reading.  This now
properly takes into account device widths and device max widths
as required.  The reading of these IDs uses the same max_width
dependent addressing as CFI queries.

The old code remains for chips that don't specify a device width,
as the new code relies on a device width being set in order to
properly operate.  The existing code seems very broken.

Only ident0 and ident1 are used in the new code, as other fields
relate to the lock state of blocks in flash.

The VExpress flash configuration has been updated to match
the new code, as the existing definition was 'wrong' in order
to return the expected results with the broken device ID code.

Signed-off-by: Roy Franz <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3671cd879a2666ca1d6e8820a319924be25d6746
      
https://github.com/qemu/qemu/commit/3671cd879a2666ca1d6e8820a319924be25d6746
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm/helper.c: Allow cp15.c15 dummy override

The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d8ba780b6a17020aadea479ad96ed9fe3bb10661
      
https://github.com/qemu/qemu/commit/d8ba780b6a17020aadea479ad96ed9fe3bb10661
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Define and use ARM_FEATURE_CBAR

Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation).

This patch prepares support for converting CBAR reset value to
a CPU property by moving the CP registration out of the CPU
init fn, as registration will need to happen at realize time
to pick up any property updates. The easiest way to do this
is via definition of a new ARM_FEATURE to flag the existence
of the register.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 07a5b0d21e450842e3474546366593a5893e8c61
      
https://github.com/qemu/qemu/commit/07a5b0d21e450842e3474546366593a5893e8c61
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  target-arm/cpu: Convert reset CBAR to a property

The reset value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f282f29626b6ce65641fb5f8cb631aaade0e51c5
      
https://github.com/qemu/qemu/commit/f282f29626b6ce65641fb5f8cb631aaade0e51c5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  arm/highbank: Use object_new() rather than cpu_arm_init()

To allow the machine model to set device properties before CPU
realization.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c0f1ead985e024dd8d01bba650bc753083a2cc2a
      
https://github.com/qemu/qemu/commit/c0f1ead985e024dd8d01bba650bc753083a2cc2a
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  arm/highbank: Fix CBAR initialisation

Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the intended value is now
actually used.

So I have kind of tested this. I booted an ARM kernel on Highbank with
the stock Highbank DTB. It doesn't boot (and I will be doing something
wrong), but before this patch I got this:

------------[ cut here ]------------
WARNING: CPU: 0 PID: 0 at 
/workspaces/pcrost/public/linux2.git/arch/arm/mm/ioremap.c:301 
__arm_ioremap_pfn_caller+0x180/0x198()
CPU: 0 PID: 0 Comm: swapper/0 Tainted: G        W 
3.13.0-rc1-next-20131126-dirty #2
[<c0015164>] (unwind_backtrace) from [<c00118c0>] (show_stack+0x10/0x14)
[<c00118c0>] (show_stack) from [<c02bd5fc>] (dump_stack+0x78/0x90)
[<c02bd5fc>] (dump_stack) from [<c001f110>] (warn_slowpath_common+0x68/0x84)
[<c001f110>] (warn_slowpath_common) from [<c001f1f4>] 
(warn_slowpath_null+0x1c/0x24)
[<c001f1f4>] (warn_slowpath_null) from [<c0017c6c>] 
(__arm_ioremap_pfn_caller+0x180/0x198)
[<c0017c6c>] (__arm_ioremap_pfn_caller) from [<c0017cd8>] 
(__arm_ioremap_caller+0x54/0x5c)
[<c0017cd8>] (__arm_ioremap_caller) from [<c0017d10>] (__arm_ioremap+0x18/0x1c)
[<c0017d10>] (__arm_ioremap) from [<c03913c0>] (highbank_init_irq+0x34/0x8c)
[<c03913c0>] (highbank_init_irq) from [<c038c228>] (init_IRQ+0x28/0x2c)
[<c038c228>] (init_IRQ) from [<c03899ec>] (start_kernel+0x234/0x398)
[<c03899ec>] (start_kernel) from [<00008074>] (0x8074)
---[ end trace 3406ff24bd97382f ]---

Which disappears with this patch.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d8bbdcf8d6cb71735014dbd22baf274aea46066f
      
https://github.com/qemu/qemu/commit/d8bbdcf8d6cb71735014dbd22baf274aea46066f
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()

To allow the machine model to set device properties before CPU
realization.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c25771281ea17c2a09c86ac6a74672f2ec297f8d
      
https://github.com/qemu/qemu/commit/c25771281ea17c2a09c86ac6a74672f2ec297f8d
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  arm/xilinx_zynq: Implement CBAR initialisation

Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the SCU base address.

Needed to boot Linux on the xilinx_zynq machine model.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e2cddeeb97a47cd58384cfd86ae79c9bbe829255
      
https://github.com/qemu/qemu/commit/e2cddeeb97a47cd58384cfd86ae79c9bbe829255
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/highbank.c

  Log Message:
  -----------
  arm/highbank.c: Fix MPCore periphbase name

GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore. Rename to
MPCORE_PERIPHBASE accordingly.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 68e0a40a5342e798a76ff4c9bf33837e30099ef7
      
https://github.com/qemu/qemu/commit/68e0a40a5342e798a76ff4c9bf33837e30099ef7
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/cpu-qom.h
    M target-arm/cpu.c

  Log Message:
  -----------
  ARM: cpu: add "reset_hivecs" property

Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.

The existence of the property is conditional on the ARM CPU not being M
class.

Signed-off-by: Antony Pavlov <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[ PC Changes:
 * Elaborated commit message
 * refactored to use qdev_property_add_static
]
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 387f980676aedcc67baddbf5fd1c9169f331f30b
      
https://github.com/qemu/qemu/commit/387f980676aedcc67baddbf5fd1c9169f331f30b
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/cpu.c

  Log Message:
  -----------
  ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc

If hivecs are being used on reset, the CPU should come out of reset at
the hivecs reset vector (0xFFFF0000)

Signed-off-by: Antony Pavlov <address@hidden>
Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
[ PC Changes:
 * Fixed Grammar error in commit message
 * Elaborated commit message.
]
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b197ebd410f0298ec078c3048f9cfb9f6bfc3b3c
      
https://github.com/qemu/qemu/commit/b197ebd410f0298ec078c3048f9cfb9f6bfc3b3c
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/Makefile.objs
    M target-arm/kvm.c
    A target-arm/kvm32.c

  Log Message:
  -----------
  target-arm/kvm: Split 32 bit only code into its own file

Split ARM KVM support code which is 32 bit specific out into its
own file, which we only compile on 32 bit hosts. This will give
us a place to add the 64 bit support code without adding lots of
ifdefs to kvm.c.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Christoffer Dall <address@hidden>


  Commit: d356312fdc8640af929e0dbab61c6e514d47feb8
      
https://github.com/qemu/qemu/commit/d356312fdc8640af929e0dbab61c6e514d47feb8
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M linux-user/signal.c
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/gdbstub64.c
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: Clean up handling of AArch64 PSTATE

The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However it's convenient
for QEMU to use it to hold the various PSTATE architectural bits
in the same format the architecture specifies for SPSR registers
(since this is the same format the kernel uses for signal handlers
and the KVM register). Add some structure to how we deal with it:
 * document what env->pstate is
 * add some #defines for various bits in it
 * add helpers for reading/writing it taking account of caching
   of NZCV, and use them where appropriate
 * reset it on startup

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Christoffer Dall <address@hidden>


  Commit: 26861c7ce06c055786323ff4c65af74d735d1c19
      
https://github.com/qemu/qemu/commit/26861c7ce06c055786323ff4c65af74d735d1c19
  Author: Mian M. Hamayun <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/Makefile.objs
    M target-arm/kvm.c
    A target-arm/kvm64.c

  Log Message:
  -----------
  target-arm: Add minimal KVM AArch64 support

Add the bare minimum set of functions needed for control of an
AArch64 KVM vcpu:
 * CPU initialization
 * minimal get/put register functions which only handle the
   basic state of the CPU

Signed-off-by: Mian M. Hamayun <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: significantly overhauled; most notably:
 * code lives in kvm64.c rather than using #ifdefs
 * support '-cpu host' rather than implicitly using whatever the
   host's CPU is regardless of what the user requests
 * fix bug attempting to get/set nonexistent X[31]
 * fix bug writing 64 bit kernel pstate into uint32_t env field
]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>


  Commit: 70a5f682f34c04d13164eb0d55241b7378f02030
      
https://github.com/qemu/qemu/commit/70a5f682f34c04d13164eb0d55241b7378f02030
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M configure

  Log Message:
  -----------
  configure: Enable KVM for aarch64 host/target combination

Enable KVM if the host and target CPU are both aarch64. Note
that host aarch64 + target arm is not valid for KVM acceleration:
the 64 bit kernel does not support the ioctl interface for
32 bit CPUs. 32 bit VMs on 64 bit hosts need to be created
using the 64 bit ioctl interface; when QEMU supports this it
will be on the arch64-softmmu target with a -cpu parameter for
a 32 bit CPU, which is still an aarch64/aarch64 combination
as far as configure is concerned.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Christoffer Dall <address@hidden>


  Commit: 47b1da8134610c10a672b249808dbc763308668e
      
https://github.com/qemu/qemu/commit/47b1da8134610c10a672b249808dbc763308668e
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: Allow easier swapping in of different loader code

For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However currently
we hardcode the offsets into the loader code where we must write
the entrypoint and other data into arm_load_kernel(). This makes it
hard to substitute a different loader fragment, so switch to a more
flexible scheme where instead of a raw array of instructions we use
an array of (instruction, fixup-type) pairs that indicate which
words need special action or data written into them.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Christoffer Dall <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 4d9ebf751a5a98e5dc2e26baf2344e744f4fa7b9
      
https://github.com/qemu/qemu/commit/4d9ebf751a5a98e5dc2e26baf2344e744f4fa7b9
  Author: Mian M. Hamayun <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: Add boot support for AArch64 processor

This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes placeholders for Board-ID
that are used to implement uniform indexing across different bootloaders.

Signed-off-by: Mian M. Hamayun <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM:
 * updated to use ARMInsnFixup style bootloader fragments
 * dropped virt.c additions
 * use runtime checks for "is this an AArch64 core" rather than ifdefs
 * drop some unnecessary setting of registers in reset hook
]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>


  Commit: 013424d436b83f7ba8366b1d40bf82c4f6716f5e
      
https://github.com/qemu/qemu/commit/013424d436b83f7ba8366b1d40bf82c4f6716f5e
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    A default-configs/aarch64-softmmu.mak

  Log Message:
  -----------
  default-configs: Add config for aarch64-softmmu

Add a config for aarch64-softmmu; this enables building of this target.
The resulting executable doesn't know about any 64 bit CPUs, but all
the 32 bit CPUs and board models work.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Crosthwaite <address@hidden>


  Commit: 40f860cd6c1aa0d3399e3f8158f20bdc5b2bfbfe
      
https://github.com/qemu/qemu/commit/40f860cd6c1aa0d3399e3f8158f20bdc5b2bfbfe
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()

The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
 * conditionally executed instructions
 * Thumb IT blocks
 * kernel helper page
 * M profile exception-exit special casing

None of these apply to A64, so putting the "this is A64 so
call the A64 decoder" check in the middle of the A32/T32
loop is confusing and means the A64 decoder's handling of
things like conditional jump and singlestepping has to take
account of the conditional-execution jumps the main loop
might emit.

Refactor the code to give A64 its own gen_intermediate_code_internal
function instead.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
      
https://github.com/qemu/qemu/commit/5ce4f35781028ce1aee3341e6002f925fdc7aaf3
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/cpu64.c

  Log Message:
  -----------
  target-arm: A64: add set_pc cpu method

When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch64 CPUs.
This covers user-mode, but for system mode emulation we will
need to check if the CPU is in an AArch32 execution state.

Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: f903fa22f4d7f3a20c4d0f42e7585ed80a3ec051
      
https://github.com/qemu/qemu/commit/f903fa22f4d7f3a20c4d0f42e7585ed80a3ec051
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/cpu.h

  Log Message:
  -----------
  target-arm: A64: provide functions for accessing FPCR and FPSR

The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and FPCR.
Since they are carefully arranged to use non-overlapping bits,
we leave the underlying state in the same place, and provide
accessor functions which just update the appropriate bits
via vfp_get_fpscr() and vfp_set_fpscr().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 6a66942735569ec7f8b761c1205e6f4c50962fe4
      
https://github.com/qemu/qemu/commit/6a66942735569ec7f8b761c1205e6f4c50962fe4
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M configure
    A gdb-xml/aarch64-fpu.xml
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Support fp registers in gdb stub

Register the aarch64-fpu XML and implement the necessary
read/write handlers so we can support reading and writing
of FP registers in the gdb stub.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: d3e35a1fe4562ee3f9f1af91ab02d62cf31b9488
      
https://github.com/qemu/qemu/commit/d3e35a1fe4562ee3f9f1af91ab02d62cf31b9488
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/Makefile.objs
    A target-arm/helper-a64.c
    A target-arm/helper-a64.h
    M target-arm/helper.h

  Log Message:
  -----------
  target-arm: A64: add stubs for a64 specific helpers

We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.

Signed-off-by: Alexander Graf <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: ad7ee8a290d08a2fe9d408af2461d1f583d96f7d
      
https://github.com/qemu/qemu/commit/ad7ee8a290d08a2fe9d408af2461d1f583d96f7d
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: provide skeleton for a64 insn decoding

Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined by the
ARM Architecture Reference Manual(DDI0487A_a) section C3.

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 87462e0f41fccc353f9c902caed563ab7cbdd8ed
      
https://github.com/qemu/qemu/commit/87462e0f41fccc353f9c902caed563ab7cbdd8ed
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: expand decoding skeleton for system instructions

Decode the various kinds of system instructions:
 hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
 sync instructions, which include CLREX, DSB, DMB, ISB
 msr_i, which move immediate to processor state field
 sys, which include all SYS and SYSL instructions
 msr, which move from a gp register to a system register
 mrs, which move from a system register to a gp register

Provide implementations where they are trivial nops.

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 11e169de9940b9dc057e534ecf864c542fafb425
      
https://github.com/qemu/qemu/commit/11e169de9940b9dc057e534ecf864c542fafb425
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: A64: add support for B and BL insns

Implement the B and BL instructions (PC relative branches and calls).

For convenience in managing TCG temporaries which might be generated
if a source register is the zero-register XZR, we provide a simple
mechanism for creating a new temp which is automatically freed at the
end of decode of the instruction.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: renamed functions, adapted to new decoder layout]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: b001c8c3d6855b0b52fc0fdd63b5a93fd326bf0c
      
https://github.com/qemu/qemu/commit/b001c8c3d6855b0b52fc0fdd63b5a93fd326bf0c
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for BR, BLR and RET insns

Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
and DPRS (which are system mode only).

Signed-off-by: Alexander Graf <address@hidden>
[claudio: reimplemented on top of new decoder structure]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 39fb730aed8c5f7b0058845cb9feac0d4b177985
      
https://github.com/qemu/qemu/commit/39fb730aed8c5f7b0058845cb9feac0d4b177985
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h

  Log Message:
  -----------
  target-arm: A64: add support for conditional branches

This patch adds emulation for the conditional branch (b.cond) instruction.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder structure,
    reused arm infrastructure for checking the flags]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: db0f79589c16fe7f697716f4cadc903a2575ef55
      
https://github.com/qemu/qemu/commit/db0f79589c16fe7f697716f4cadc903a2575ef55
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 'test and branch' imm

This patch adds emulation for the test and branch insns,
TBZ and TBNZ.

Signed-off-by: Alexander Graf <address@hidden>
[claudio:
  adapted for new decoder
  always compare with 0
  remove a TCG temporary
]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 60e5338831e35e7b407b1670f5fe936859ea5490
      
https://github.com/qemu/qemu/commit/60e5338831e35e7b407b1670f5fe936859ea5490
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for compare and branch imm

This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder,
    compare with immediate 0,
          introduce read_cpu_reg to get the 0 extension on (!sf)]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e952d8c77a59dd31b5a4332f19e19f43dc90bd68
      
https://github.com/qemu/qemu/commit/e952d8c77a59dd31b5a4332f19e19f43dc90bd68
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for conditional select

This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.

Signed-off-by: Claudio Fontana <address@hidden>
[PMM: Improved code generated in the nomatch case as per RTH suggestions]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 832ffa1ce073f010fd1c766361b2e35ce3f105d3
      
https://github.com/qemu/qemu/commit/832ffa1ce073f010fd1c766361b2e35ce3f105d3
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for logical (shifted register)

Add support for the instructions described in "C3.5.10 Logical
(shifted register)".

We store the flags in the same locations as the 32 bit decoder.
This is slightly awkward when calculating 64 bit results, but seems
a better tradeoff than having to rework the whole 32 bit decoder
and also make 32 bit result calculation in A64 awkward.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: some refactoring to avoid hidden allocation of temps,
          rework flags, use enums for shift types,
          renaming of functions]
Signed-off-by: Claudio Fontana <address@hidden>
[PMM: Use TCG's andc/orc/eqv ops rather than manually inverting]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 15bfe8b650a0fd40940cb8f4bfc8c57d6940173e
      
https://github.com/qemu/qemu/commit/15bfe8b650a0fd40940cb8f4bfc8c57d6940173e
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for ADR and ADRP

Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder structure]
Signed-off-by: Claudio Fontana <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e801de93d0155c0c14d6b4dea1b3577ca36e214b
      
https://github.com/qemu/qemu/commit/e801de93d0155c0c14d6b4dea1b3577ca36e214b
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for EXTR

This patch adds emulation support for the EXTR instruction.

Signed-off-by: Alexander Graf <address@hidden>

[claudio: adapted for new decoder, removed a few temporaries,
    fixed the 32bit bug, added checks for more
    unallocated cases]

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 8220e911c240df5b4b2a1473f0ba9feddc154c45
      
https://github.com/qemu/qemu/commit/8220e911c240df5b4b2a1473f0ba9feddc154c45
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 2-src data processing and DIV

This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder adding the 2-src decoding level,
    always zero-extend result in 32bit mode]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 6c1adc919b6a81e008b919c53902b4877ef4d737
      
https://github.com/qemu/qemu/commit/6c1adc919b6a81e008b919c53902b4877ef4d737
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 2-src shift reg insns

This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 680ead216e666e5cc192fe86adf30563999a5dd8
      
https://github.com/qemu/qemu/commit/680ead216e666e5cc192fe86adf30563999a5dd8
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 1-src data processing and CLZ

This patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ (count leading zeroes).

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 82e14b02a2bd822af6db2ef728a1698b9a24e50c
      
https://github.com/qemu/qemu/commit/82e14b02a2bd822af6db2ef728a1698b9a24e50c
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 1-src RBIT insn

This adds support for the C5.6.147 RBIT instruction.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder, use bswap64,
    make RBIT part standalone from the rest of the patch,
          splitting REV into a separate patch]
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 453232096c4e93ec871f7ff97abfc0bf54258c95
      
https://github.com/qemu/qemu/commit/453232096c4e93ec871f7ff97abfc0bf54258c95
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 1-src REV insns

This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 880777423525685ccaf1bf6967b27cc8a38e5f96
      
https://github.com/qemu/qemu/commit/880777423525685ccaf1bf6967b27cc8a38e5f96
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for bitfield insns

This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: afd3fe4ce56e6fb0d0384ddb8e3c4fac01935c37
      
https://github.com/qemu/qemu/commit/afd3fe4ce56e6fb0d0384ddb8e3c4fac01935c37
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M include/qemu/host-utils.h

  Log Message:
  -----------
  host-utils: add clrsb32/64 - count leading redundant sign bits

this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: e80c502023d332fb60866eb378e715ab3f158b72
      
https://github.com/qemu/qemu/commit/e80c502023d332fb60866eb378e715ab3f158b72
  Author: Claudio Fontana <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/helper-a64.c
    M target-arm/helper-a64.h
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for 1-src CLS insn

this patch adds support for the CLS instruction.

Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 71b46089303beb7d52a0b9397f5c286a7e66275f
      
https://github.com/qemu/qemu/commit/71b46089303beb7d52a0b9397f5c286a7e66275f
  Author: Alexander Graf <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M target-arm/translate-a64.c

  Log Message:
  -----------
  target-arm: A64: add support for logical (immediate) insns

This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.

Signed-off-by: Alexander Graf <address@hidden>
[claudio: adapted to new decoder, function renaming,
    removed a TCG temp variable]
Signed-off-by: Claudio Fontana <address@hidden>
[PMM: cleaned up some unnecessary code in logic_imm_decode_wmask
and added clarifying commentary on what it's actually doing.
Dropped an ext32u that's not needed if we've just done an AND.]
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: c6f09eb4a0ea14b68f2745e87641c79a51057959
      
https://github.com/qemu/qemu/commit/c6f09eb4a0ea14b68f2745e87641c79a51057959
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/digic.c
    A include/hw/arm/digic.h

  Log Message:
  -----------
  hw/arm: add very initial support for Canon DIGIC SoC

DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.

There is no publicly available specification for
DIGIC chips. All information about DIGIC chip
internals is based on reverse engineering efforts
made by CHDK (http://chdk.wikia.com) and
Magic Lantern (http://www.magiclantern.fm) projects
contributors.

Signed-off-by: Antony Pavlov <address@hidden>
Reviewed-by: Andreas Färber <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d91fd756fb2af16584d338c4ef715f40ea49924c
      
https://github.com/qemu/qemu/commit/d91fd756fb2af16584d338c4ef715f40ea49924c
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/digic_boards.c
    M tests/qom-test.c

  Log Message:
  -----------
  hw/arm/digic: prepare DIGIC-based boards support

Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.

Signed-off-by: Antony Pavlov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 576e99cb951e9c1a289555a31cfd5b9040e80037
      
https://github.com/qemu/qemu/commit/576e99cb951e9c1a289555a31cfd5b9040e80037
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/digic.c
    M hw/timer/Makefile.objs
    A hw/timer/digic-timer.c
    M include/hw/arm/digic.h
    A include/hw/timer/digic-timer.h

  Log Message:
  -----------
  hw/arm/digic: add timer support

Signed-off-by: Antony Pavlov <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 142593c9d700e02b316443bcaa99226720242625
      
https://github.com/qemu/qemu/commit/142593c9d700e02b316443bcaa99226720242625
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/digic.c
    M hw/char/Makefile.objs
    A hw/char/digic-uart.c
    M include/hw/arm/digic.h
    A include/hw/char/digic-uart.h

  Log Message:
  -----------
  hw/arm/digic: add UART support

Signed-off-by: Antony Pavlov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 04234a37b1a89f3f119ef59c143a7b2e0a1ab40e
      
https://github.com/qemu/qemu/commit/04234a37b1a89f3f119ef59c143a7b2e0a1ab40e
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/digic_boards.c

  Log Message:
  -----------
  hw/arm/digic: add NOR ROM support

Signed-off-by: Antony Pavlov <address@hidden>
Message-id: address@hidden
[PMM: don't try to load ROM blob if qtest_enabled()]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9082f12173d407290bcec9f4ae84242972b2480c
      
https://github.com/qemu/qemu/commit/9082f12173d407290bcec9f4ae84242972b2480c
  Author: Antony Pavlov <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Document 'Canon DIGIC' machine

Signed-off-by: Antony Pavlov <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1f05e79f2c207bded5efc23e8c6b1ca58161a8e
      
https://github.com/qemu/qemu/commit/a1f05e79f2c207bded5efc23e8c6b1ca58161a8e
  Author: Peter Maydell <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M include/hw/ptimer.h
    M include/migration/vmstate.h

  Log Message:
  -----------
  vmstate: Add support for an array of ptimer_state *

Add support for defining a vmstate field which is an array
of pointers to structures, and use this to define a
VMSTATE_PTIMER_ARRAY() which allows an array of ptimer_state*
to be used by devices.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: 3589de8c971df29562fcaf2d9b04f0886aff4866
      
https://github.com/qemu/qemu/commit/3589de8c971df29562fcaf2d9b04f0886aff4866
  Author: liguang <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/timer/Makefile.objs
    A hw/timer/allwinner-a10-pit.c
    A include/hw/timer/allwinner-a10-pit.h

  Log Message:
  -----------
  hw/timer: add allwinner a10 timer

Signed-off-by: liguang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c3931ee8b42def4089831b4d79e93c5b05667ff6
      
https://github.com/qemu/qemu/commit/c3931ee8b42def4089831b4d79e93c5b05667ff6
  Author: liguang <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/intc/Makefile.objs
    A hw/intc/allwinner-a10-pic.c
    A include/hw/intc/allwinner-a10-pic.h

  Log Message:
  -----------
  hw/intc: add allwinner A10 interrupt controller

Signed-off-by: liguang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9158fa5451b5929f1d882ef08c30b4f4aadd6945
      
https://github.com/qemu/qemu/commit/9158fa5451b5929f1d882ef08c30b4f4aadd6945
  Author: liguang <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/allwinner-a10.c
    A include/hw/arm/allwinner-a10.h

  Log Message:
  -----------
  hw/arm: add allwinner a10 SoC support

Signed-off-by: liguang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a01c005327007562f3313f3efe235f77309db809
      
https://github.com/qemu/qemu/commit/a01c005327007562f3313f3efe235f77309db809
  Author: liguang <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/cubieboard.c
    M tests/qom-test.c

  Log Message:
  -----------
  hw/arm: add cubieboard support

Signed-off-by: liguang <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 84291fe7a34f8c2d595bcdb77ff506d1d60fcd7c
      
https://github.com/qemu/qemu/commit/84291fe7a34f8c2d595bcdb77ff506d1d60fcd7c
  Author: liguang <address@hidden>
  Date:   2013-12-17 (Tue, 17 Dec 2013)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: add myself to maintain allwinner-a10

Signed-off-by: liguang <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3dc7e2a3fedafc2f951bd62300b342c84e3606f8
      
https://github.com/qemu/qemu/commit/3dc7e2a3fedafc2f951bd62300b342c84e3606f8
  Author: Anthony Liguori <address@hidden>
  Date:   2013-12-19 (Thu, 19 Dec 2013)

  Changed paths:
    M MAINTAINERS
    M configure
    A default-configs/aarch64-softmmu.mak
    M default-configs/arm-softmmu.mak
    A gdb-xml/aarch64-fpu.xml
    M hw/arm/Makefile.objs
    A hw/arm/allwinner-a10.c
    M hw/arm/boot.c
    A hw/arm/cubieboard.c
    A hw/arm/digic.c
    A hw/arm/digic_boards.c
    M hw/arm/highbank.c
    M hw/arm/vexpress.c
    M hw/arm/xilinx_zynq.c
    M hw/block/pflash_cfi01.c
    M hw/char/Makefile.objs
    A hw/char/digic-uart.c
    M hw/intc/Makefile.objs
    A hw/intc/allwinner-a10-pic.c
    M hw/timer/Makefile.objs
    A hw/timer/allwinner-a10-pit.c
    A hw/timer/digic-timer.c
    A include/hw/arm/allwinner-a10.h
    A include/hw/arm/digic.h
    A include/hw/char/digic-uart.h
    A include/hw/intc/allwinner-a10-pic.h
    M include/hw/ptimer.h
    A include/hw/timer/allwinner-a10-pit.h
    A include/hw/timer/digic-timer.h
    M include/migration/vmstate.h
    M include/qemu/host-utils.h
    M linux-user/signal.c
    M target-arm/Makefile.objs
    M target-arm/cpu-qom.h
    M target-arm/cpu.c
    M target-arm/cpu.h
    M target-arm/cpu64.c
    A target-arm/crypto_helper.c
    M target-arm/gdbstub64.c
    A target-arm/helper-a64.c
    A target-arm/helper-a64.h
    M target-arm/helper.c
    M target-arm/helper.h
    M target-arm/kvm.c
    A target-arm/kvm32.c
    A target-arm/kvm64.c
    M target-arm/translate-a64.c
    M target-arm/translate.c
    M target-arm/translate.h
    M tests/qom-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into 
staging

target-arm queue:
 * AES instruction support for 32 bit ARM
 * pflash01: much better emulation of 2x16bit and similar configs
   where multiple flash devices are banked together
 * fixed CBAR handling on Zynq, Highbank
 * initial AArch64 KVM control support
 * first two chunks of patches for A64 instruction emulation
 * new board: canon-a1100 (Canon DIGIC SoC)
 * new board: cubieboard (Allwinner A10 SoC)

# gpg: Signature made Tue 17 Dec 2013 12:18:39 PM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found

# By Alexander Graf (14) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20131217: (62 commits)
  MAINTAINERS: add myself to maintain allwinner-a10
  hw/arm: add cubieboard support
  hw/arm: add allwinner a10 SoC support
  hw/intc: add allwinner A10 interrupt controller
  hw/timer: add allwinner a10 timer
  vmstate: Add support for an array of ptimer_state *
  MAINTAINERS: Document 'Canon DIGIC' machine
  hw/arm/digic: add NOR ROM support
  hw/arm/digic: add UART support
  hw/arm/digic: add timer support
  hw/arm/digic: prepare DIGIC-based boards support
  hw/arm: add very initial support for Canon DIGIC SoC
  target-arm: A64: add support for logical (immediate) insns
  target-arm: A64: add support for 1-src CLS insn
  host-utils: add clrsb32/64 - count leading redundant sign bits
  target-arm: A64: add support for bitfield insns
  target-arm: A64: add support for 1-src REV insns
  target-arm: A64: add support for 1-src RBIT insn
  target-arm: A64: add support for 1-src data processing and CLZ
  target-arm: A64: add support for 2-src shift reg insns
  ...

Message-id: address@hidden
Signed-off-by: Anthony Liguori <address@hidden>


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