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[Qemu-commits] [qemu/qemu] 37a011: microblaze/petalogix_s3adsp1800_mmu:
From: |
GitHub |
Subject: |
[Qemu-commits] [qemu/qemu] 37a011: microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ |
Date: |
Tue, 18 Jun 2013 01:00:08 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 37a011e9bade7bcbdd41addffc7c94cbf628404c
https://github.com/qemu/qemu/commit/37a011e9bade7bcbdd41addffc7c94cbf628404c
Author: Peter Crosthwaite <address@hidden>
Date: 2013-06-18 (Tue, 18 Jun 2013)
Changed paths:
M hw/microblaze/petalogix_s3adsp1800_mmu.c
Log Message:
-----------
microblaze/petalogix_s3adsp1800_mmu: Fix UART IRQ
The UART IRQ is edge sensitive, whereas the machine was registering it
as level sensitive. Fix.
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Commit: 6327c221fff955ee979559ec85c148963e06d78f
https://github.com/qemu/qemu/commit/6327c221fff955ee979559ec85c148963e06d78f
Author: Peter Crosthwaite <address@hidden>
Date: 2013-06-18 (Tue, 18 Jun 2013)
Changed paths:
M hw/intc/xilinx_intc.c
Log Message:
-----------
intc/xilinx_intc: Don't clear level sens. IRQs without ACK
For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Commit: 45fdd3bf5a00466cb0f762c638291a5446773dc9
https://github.com/qemu/qemu/commit/45fdd3bf5a00466cb0f762c638291a5446773dc9
Author: Peter Crosthwaite <address@hidden>
Date: 2013-06-18 (Tue, 18 Jun 2013)
Changed paths:
M hw/intc/xilinx_intc.c
Log Message:
-----------
intc/xilinx_intc: Handle level interrupt retriggering
Acking a level sensitive interrupt should have no effect if the
interrupt pin is still asserted. The current implementation requires
and edge condition to occur for setting a level sensitive IRQ, which
means an ACK can clear a level sensitive interrupt, until the original
source strobes the interrupt again.
Fix by keeping track of the interrupt pin state and setting ISR based
on this every time update_irq() is called.
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Commit: fa96d6142f7f1947717c7c45c4d3141e5ab55167
https://github.com/qemu/qemu/commit/fa96d6142f7f1947717c7c45c4d3141e5ab55167
Author: Peter Crosthwaite <address@hidden>
Date: 2013-06-18 (Tue, 18 Jun 2013)
Changed paths:
M hw/intc/xilinx_intc.c
Log Message:
-----------
intc/xilinx_intc: Inhibit write to ISR when HIE
When the Hardware Interrupt Enable (HIE) bit is set, software cannot
change ISR. Add write guard accordingly.
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Commit: afd59989db90683fa127fec501d2633bcfbd6379
https://github.com/qemu/qemu/commit/afd59989db90683fa127fec501d2633bcfbd6379
Author: Peter Crosthwaite <address@hidden>
Date: 2013-06-18 (Tue, 18 Jun 2013)
Changed paths:
M hw/intc/xilinx_intc.c
Log Message:
-----------
intc/xilinx_intc: Dont lower IRQ when HIE cleared
This is a little strange. It is lowering the parent IRQ pin on input
when HIE is cleared. There is no such behaviour in the real hardware.
ISR changes based on interrupt pin state are already guarded on HIE
being set. So we can just delete this if in its entirety.
Signed-off-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Compare: https://github.com/qemu/qemu/compare/21a885a7e2a0...afd59989db90
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