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[Qemu-commits] [qemu/qemu] 6b91f0: xilinx_spips: seperate SPI and QSPI a


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 6b91f0: xilinx_spips: seperate SPI and QSPI as two classes
Date: Mon, 03 Jun 2013 12:30:15 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6b91f0155b9338b7fa53d1d64f4e40c43a5d3bba
      
https://github.com/qemu/qemu/commit/6b91f0155b9338b7fa53d1d64f4e40c43a5d3bba
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/arm/xilinx_zynq.c
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: seperate SPI and QSPI as two classes

Make SPI and QSPI different classes. QSPIPS is setup as a child of SPIPS.
Only QSPI has the LQSPI functionality, so move all that to the child class.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 87920b44a1e04a45bf74ee0a88a2dfa51c65acdb
      
https://github.com/qemu/qemu/commit/87920b44a1e04a45bf74ee0a88a2dfa51c65acdb
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Make interrupts clear on read

By default these interrupts are clear on read.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3ea728d0c87011845666caedc582eaa9629797db
      
https://github.com/qemu/qemu/commit/3ea728d0c87011845666caedc582eaa9629797db
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Inhibit interrupts in LQSPI mode

The real hardware does not produce interrupts in LQSPI mode. Inhibit
generation of interrupts when the LQ_MODE bit is set.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: abef5fa6438d654de59dfa083166f41a4067f6b7
      
https://github.com/qemu/qemu/commit/abef5fa6438d654de59dfa083166f41a4067f6b7
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Add verbose LQSPI debug output

You really need this is you want to track a guest banging on LQSPI.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 10e60b35d04359fba1d759925018204527a1b9f5
      
https://github.com/qemu/qemu/commit/10e60b35d04359fba1d759925018204527a1b9f5
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Fix QSPI FIFO size

QSPI has a bigger FIFO than the regular SPI controller. Differentiate
between the two with correct FIFO sizes for each.

This is the first piece of class data for SPIPS, so this patch sees
the creation of the XilinxSPIPSClass definition and assoicated QOM
constructs.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b5cd9143e78da8ea9e17fa523aacbedd267aae54
      
https://github.com/qemu/qemu/commit/b5cd9143e78da8ea9e17fa523aacbedd267aae54
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Trash LQ page cache on mode change

Invalidate the LQSPI cached page when transitioning into LQSPI mode.
Otherwise there is a possibility that the controller will return stale
data to the guest when transitioning back to LQ_MODE after a page
program.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e100f3be0cccc58692b3988ec2e35cd8b906ca05
      
https://github.com/qemu/qemu/commit/e100f3be0cccc58692b3988ec2e35cd8b906ca05
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Add automatic start support

SPI has a mode where it automatically starts based on tx fifo
occupancy. Implemented.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4f08ffe134810307cebd66f2cbcffe5cd707915
      
https://github.com/qemu/qemu/commit/c4f08ffe134810307cebd66f2cbcffe5cd707915
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Implement automatic CS

Implement the automatic CS control feature. If the MANUAL_CS bit is
cleared then the chip select stay de-asserted as long as the tx FIFO
is empty.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 15408b428f5b4db56da555fbda4f1aaf40d77f4b
      
https://github.com/qemu/qemu/commit/15408b428f5b4db56da555fbda4f1aaf40d77f4b
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: lqspi: Dont touch config register

The LQSPI mode is supposed to work via the automatic CS mode feature
rather than manipulate CS lines itself. Now that auto CS is implemented
remove LQSPIs CS mode override logic. There is still a need to
manipulate the U_PAGE bit in LQSPI config register to implement
dual-stack mode however.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2133a5f6b8f8941a6a3734c6c1990656553de76c
      
https://github.com/qemu/qemu/commit/2133a5f6b8f8941a6a3734c6c1990656553de76c
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Fix CTRL register RW bits

The CTRL register was RAZ/WI on some of the RW bits. Even though the
function behind these bits is invalid in QEMU, they should still be
guest accessible. Fix.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9151da25a71a171d19beec107a8ee2066cb65e7c
      
https://github.com/qemu/qemu/commit/9151da25a71a171d19beec107a8ee2066cb65e7c
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Fix striping behaviour

The QSPI controller was using byte-wide stripes when striping across
the two flashes in dual parallel mode. The real hardware however uses
individual bit striping. QEMU misbehaves in the (corner) case where
data is written/read in dual-parallel mode and read/written back in
single mode.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c37fc509d288ff693e42b2025451241fdd481948
      
https://github.com/qemu/qemu/commit/c37fc509d288ff693e42b2025451241fdd481948
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Debug msgs for Snoop state

This is worth keeping track of when debugging the device model.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4a5b6fa8d9bdeec71f4f92e8b7a31fc344ef512f
      
https://github.com/qemu/qemu/commit/4a5b6fa8d9bdeec71f4f92e8b7a31fc344ef512f
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Multiple debug verbosity levels

The debug printfs on every SPI operation is extremely verbose. Add
a second level of debug for this.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a66418f6f181ca6ee04e77896674253ff83db45e
      
https://github.com/qemu/qemu/commit/a66418f6f181ca6ee04e77896674253ff83db45e
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: lqspi: Push more data to tx-fifo

Do 16 words per fifo flush. Increases performance and decreases
debug verbosity. This data depth has no real hardware analogue,
so just go with something that has reasonable performance.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b0b7ae6259e96e775315357c813b74e85637bf32
      
https://github.com/qemu/qemu/commit/b0b7ae6259e96e775315357c813b74e85637bf32
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: lqspi: Fix byte/misaligned access

The LQSPI bus attachment supports byte/halfword and misaligned
accesses. Fixed. Refactored the LQSPI cache to be byte-wise
instead of word wise accordingly.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 656f416c65d8ddbfd17500676865f0ac8f960801
      
https://github.com/qemu/qemu/commit/656f416c65d8ddbfd17500676865f0ac8f960801
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sd/sdhci.c: Only reset data_count on new commands

The data_count variable was being reset on every transfer, including
DMA transfer resumptions. This is incorrect, it should only be set
on a new command.

Manifests as a bug when using ADMA and there is a timer delay between
ADMA frames where the fifo is left in a non empty state.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dcdb4cd8507d93ecad10ae54b28d9609453c0312
      
https://github.com/qemu/qemu/commit/dcdb4cd8507d93ecad10ae54b28d9609453c0312
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sd/sdhci: Fix Buffer Write Ready interrupt

This interrupt is not risen after the last block is written to sd. It
is mutually exclusive with the end of transfer conditions. Fix.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 677ff2ae660b3a55f936a8836513cbab185f6e4f
      
https://github.com/qemu/qemu/commit/677ff2ae660b3a55f936a8836513cbab185f6e4f
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sd/sdhci.c: Fix bdata_read DPRINT message

This message was printing out the data in decimal only, which is not
very friendly to the debugging developer. Add hex variant in
parenthesis to make it consistent with other similar messages in this
module.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1d32c26f28d6e25f447b8ba40440c7d228ed4006
      
https://github.com/qemu/qemu/commit/1d32c26f28d6e25f447b8ba40440c7d228ed4006
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/sd/sdhci.c

  Log Message:
  -----------
  sd/sdhci:ADMA: fix interrupt

The end of transfer check was occurring and potentially returning before
the interrupt flag was checked. This means the interrupt will be missed
if it occurs on the last packet. Fix by checking for the interrupt
before checking for the end of transfer.

Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37ab4a566816f518fb958ea49734d51d1ccbd227
      
https://github.com/qemu/qemu/commit/37ab4a566816f518fb958ea49734d51d1ccbd227
  Author: Peter Crosthwaite <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/sd/sd.c

  Log Message:
  -----------
  sd/sd.c: Fix "inquiry" ACMD41

QEMU models two (of the three) ACMD41 has two modes, "inquiry" and
"first". The selection logic for which of the two is incorrect - it
compares != 0 for the entire argument value rather than only bits 23:0
as per the spec. Fix.

Signed-off-by: Peter Crosthwaite <address@hidden>
Message-id: address@hidden
Reviewed-by: Igor Mitsyanko <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a50c0d6f72830ca3016e63ded6ccfd4e951c172f
      
https://github.com/qemu/qemu/commit/a50c0d6f72830ca3016e63ded6ccfd4e951c172f
  Author: Jean-Christophe DUBOIS <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/timer/Makefile.objs
    A hw/timer/imx_epit.c
    A hw/timer/imx_gpt.c
    R hw/timer/imx_timer.c

  Log Message:
  -----------
  i.MX: split GPT and EPIT timer implementation

There is no common code between these 2 timer implementation.
So it is better to split them.

Signed-off-by: Jean-Christophe DUBOIS <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 11a5e48249d8c34211065c25ddf222f031a0338e
      
https://github.com/qemu/qemu/commit/11a5e48249d8c34211065c25ddf222f031a0338e
  Author: Igor Mitsyanko <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/arm/exynos4210.c

  Log Message:
  -----------
  hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region

Exynos SoC was misusing memory_region_init_ram_ptr(): this interface can safely
be used only for memory regions which size is a multiple of target page size.
Change chipid_and_omr memory to an mmio region to fix this.

Signed-off-by: Igor Mitsyanko <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6539ed21b1d5c93e8add2f7b2bf9856889e6d1ac
      
https://github.com/qemu/qemu/commit/6539ed21b1d5c93e8add2f7b2bf9856889e6d1ac
  Author: Igor Mitsyanko <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/arm/exynos4210.c

  Log Message:
  -----------
  exynos4210.c: register rom_mem for memory migration

Even if we do not register newly created RAM MemoryRegion for migration with
vmstate_register_ram_global() function, ram_save_setup() still saves this region
to snapshot file with empty idstr=="". Consequently this results in error during
VM loading in ram_load().
Register rom_mem for migration.

Signed-off-by: Igor Mitsyanko <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 95669e69848eda87861e1ec3016562101542f543
      
https://github.com/qemu/qemu/commit/95669e69848eda87861e1ec3016562101542f543
  Author: Jean-Christophe DUBOIS <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/timer/imx_epit.c

  Log Message:
  -----------
  i.MX: Improve EPIT timer code.

* Unify function and type naming
* use dynamic cast whenever possible
* simplify Debug printf.
* use new style device intialization.

Signed-off-by: Jean-Christophe DUBOIS <address@hidden>
Reviewed-by: Peter Chubb <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0ded1fe5f36765b97b15a7afebb6d04ddcc4771c
      
https://github.com/qemu/qemu/commit/0ded1fe5f36765b97b15a7afebb6d04ddcc4771c
  Author: Anthony Liguori <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M hw/arm/exynos4210.c
    M hw/arm/xilinx_zynq.c
    M hw/sd/sd.c
    M hw/sd/sdhci.c
    M hw/ssi/xilinx_spips.c
    M hw/timer/Makefile.objs
    A hw/timer/imx_epit.c
    A hw/timer/imx_gpt.c
    R hw/timer/imx_timer.c

  Log Message:
  -----------
  Merge remote-tracking branch 'pmaydell/arm-devs.next' into staging

# By Peter Crosthwaite (20) and others
# Via Peter Maydell
* pmaydell/arm-devs.next: (24 commits)
  i.MX: Improve EPIT timer code.
  exynos4210.c: register rom_mem for memory migration
  hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region
  i.MX: split GPT and EPIT timer implementation
  sd/sd.c: Fix "inquiry" ACMD41
  sd/sdhci:ADMA: fix interrupt
  sd/sdhci.c: Fix bdata_read DPRINT message
  sd/sdhci: Fix Buffer Write Ready interrupt
  sd/sdhci.c: Only reset data_count on new commands
  xilinx_spips: lqspi: Fix byte/misaligned access
  xilinx_spips: lqspi: Push more data to tx-fifo
  xilinx_spips: Multiple debug verbosity levels
  xilinx_spips: Debug msgs for Snoop state
  xilinx_spips: Fix striping behaviour
  xilinx_spips: Fix CTRL register RW bits
  xilinx_spips: lqspi: Dont touch config register
  xilinx_spips: Implement automatic CS
  xilinx_spips: Add automatic start support
  xilinx_spips: Trash LQ page cache on mode change
  xilinx_spips: Fix QSPI FIFO size
  ...

Message-id: address@hidden
Signed-off-by: Anthony Liguori <address@hidden>


  Commit: 6e92f823b67d87aa96df01b0cb01f81ac71ec5e3
      
https://github.com/qemu/qemu/commit/6e92f823b67d87aa96df01b0cb01f81ac71ec5e3
  Author: Peter Maydell <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M configure

  Log Message:
  -----------
  configure: Autogenerate default target list

Autogenerate the default target list based on what files exist
in default-configs; this allows us to remove one of the places
that has to be kept up to date with a complete list of every
target we support.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Anthony Liguori <address@hidden>


  Commit: 25b483381adf4144bad3cf3f433b4658da5e15bb
      
https://github.com/qemu/qemu/commit/25b483381adf4144bad3cf3f433b4658da5e15bb
  Author: Peter Maydell <address@hidden>
  Date:   2013-06-03 (Mon, 03 Jun 2013)

  Changed paths:
    M configure

  Log Message:
  -----------
  configure: Report unknown target names more helpfully

If the user specifies a target list themselves, check each entry
to make sure it's a target we recognise. This allows us to print
a helpful error message, rather than falling through (where we
would probably eventually end up hitting the uninformative
"ERROR: Unsupported target CPU").

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Anthony Liguori <address@hidden>


Compare: https://github.com/qemu/qemu/compare/8b779b368b3b...25b483381adf

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