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[Qemu-commits] [qemu/qemu] d89928: target-mips: clean-up in BIT_INSV


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] d89928: target-mips: clean-up in BIT_INSV
Date: Mon, 20 May 2013 10:30:35 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d8992825aedbb83b7a0e98284e0527bc82a6f7df
      
https://github.com/qemu/qemu/commit/d8992825aedbb83b7a0e98284e0527bc82a6f7df
  Author: Petar Jovanovic <address@hidden>
  Date:   2013-05-20 (Mon, 20 May 2013)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips: clean-up in BIT_INSV

This is a small follow-up change to "fix incorrect behaviour for INSV".

It includes two minor modifications:

- sizefilter is constant so it can be moved inside of the block,
- several lines of the code are replaced with a call to deposit64.

No functional change.

Signed-off-by: Petar Jovanovic <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: ea3164aafccdfdd8a9543787cdfa25fac30a5def
      
https://github.com/qemu/qemu/commit/ea3164aafccdfdd8a9543787cdfa25fac30a5def
  Author: Kwok Cheung Yeung <address@hidden>
  Date:   2013-05-20 (Mon, 20 May 2013)

  Changed paths:
    M linux-user/signal.c

  Log Message:
  -----------
  linux-user: Fix MIPS ISA transitions during signal handling

Processors supporting the MIPS16 or microMIPS ISAs set bit 0 in target
addresses to indicate that the target is written using a compressed ISA.

During signal handling, when jumping to or returning from a signal
handler, bit 0 of the destination PC is inspected and MIPS_HFLAG_M16 in
hflags cleared or set accordingly.  Bit 0 of the PC is then cleared.

Signed-off-by: Kwok Cheung Yeung <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 1239b472bb0dba8060f1af29d40dafbc1b2860d4
      
https://github.com/qemu/qemu/commit/1239b472bb0dba8060f1af29d40dafbc1b2860d4
  Author: Kwok Cheung Yeung <address@hidden>
  Date:   2013-05-20 (Mon, 20 May 2013)

  Changed paths:
    M linux-user/signal.c
    M target-mips/cpu.h
    M target-mips/helper.c

  Log Message:
  -----------
  linux-user: Save the correct resume address for MIPS signal handling

The current ISA mode needs to be saved in bit 0 of the resume address.
If the current instruction happens to be in a branch delay slot, then
the address of the preceding jump instruction should be stored instead.
exception_resume_pc already does both of these tasks, so it is
made available and reused.

MIPS_HFLAG_BMASK in hflags is cleared, otherwise QEMU may treat the
first instruction of the signal handler as a delay slot instruction.

Signed-off-by: Kwok Cheung Yeung <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9ce0e9275434...1239b472bb0d

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