[Qemu-commits] [qemu/qemu] 0bc472: hw/nand.c: correct the sense of the BUSY/READY sta...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0bc472a9d6b80567c212023c5eae413f4dfb53ad
      
https://github.com/qemu/qemu/commit/0bc472a9d6b80567c212023c5eae413f4dfb53ad
  Author: Kuo-Jung Su <address@hidden>
  Date:   2013-03-07 (Thu, 07 Mar 2013)

  Changed paths:
    M hw/nand.c

  Log Message:
  -----------
  hw/nand.c: correct the sense of the BUSY/READY status bit

The BIT6 of Status Register(SR):

SR[6] behaves the same as R/B# pin
    SR[6] = 0 indicates the device is busy;
    SR[6] = 1 means the device is ready

Some NAND flash controller (i.e. ftnandc021) relies on the SR[6]
to determine if the NAND flash erase/program is success or error timeout.

P.S:
The exmaple NAND flash datasheet could be found at following link:
http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/8FEA549237D2F7674825795800104C26/$File/MX30LF1G08AA,%203V,%201Gb,%20v1.1.pdf

Signed-off-by: Kuo-Jung Su <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>