[Qemu-commits] [qemu/qemu] e4c1cf: target-arm: Fix TCG temp leaks for WI

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[Qemu-commits] [qemu/qemu] e4c1cf: target-arm: Fix TCG temp leaks for WI

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] e4c1cf: target-arm: Fix TCG temp leaks for WI and UNDEF VF...
Date:	Thu, 31 Jan 2013 15:00:12 -0800
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e4c1cfa5cb8f8bfbbfd949f2fabbe2be35e60c99
      
https://github.com/qemu/qemu/commit/e4c1cfa5cb8f8bfbbfd949f2fabbe2be35e60c99
  Author: Peter Maydell <address@hidden>
  Date:   2013-01-30 (Wed, 30 Jan 2013)

  Changed paths:
    M target-arm/translate.c

  Log Message:
  -----------
  target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes

Fix a leak of a TCG temporary in code paths for VFP system register
writes for cases which UNDEF or are write-ignored.

Signed-off-by: Peter Maydell <address@hidden>


  Commit: 51492fd1a99099308d8c20ab7134ffb54abbf374
      
https://github.com/qemu/qemu/commit/51492fd1a99099308d8c20ab7134ffb54abbf374
  Author: Andreas Färber <address@hidden>
  Date:   2013-01-30 (Wed, 30 Jan 2013)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/helper.c

  Log Message:
  -----------
  target-arm: Rename CPU types

In the initial conversion of CPU models to QOM types, model names were
mapped 1:1 to type names. As a side effect this gained us a type "any",
which is now a device.

To avoid "-device any" silliness and to pave the way for compiling
multiple targets into one executable, adopt a <name>-<arch>-cpu scheme.
This leads to names like arm926-arm-cpu but is easiest to handle.

No functional changes for -cpu arguments or -cpu ? output.

Suggested-by: Eduardo Habkost <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Signed-off-by: Andreas Färber <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f7d2072e25d3592acec4657dae8862facf298e9f
      
https://github.com/qemu/qemu/commit/f7d2072e25d3592acec4657dae8862facf298e9f
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: fix DSP loads with rd = 0

When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.

Reviewed-by: Eric Johnson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: d75c135e6b6255787dfc01ce997862d820ed1d36
      
https://github.com/qemu/qemu/commit/d75c135e6b6255787dfc01ce997862d820ed1d36
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: copy insn_flags in DisasContext

Copy insn_flags in DisasContext to avoid passing a CPUMIPSState pointer
to subroutines, as suggested by Richard Henderson. Change subroutines to
use this new field and remove the first argument.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: ad153f153da08f5e08bc8e433c0070af53e34e0a
      
https://github.com/qemu/qemu/commit/ad153f153da08f5e08bc8e433c0070af53e34e0a
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: generate a reserved instruction exception on CPU without DSP

On CPU without DSP ASE support, a reserved instruction exception (instead of
a DSP ASE sate disabled) should be generated.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 652613ab5ae4559b481c612010b407e1c2216f36
      
https://github.com/qemu/qemu/commit/652613ab5ae4559b481c612010b407e1c2216f36
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips: add unions to access DSP elements

Instead of playing with bit shifting, add two unions (one for 32-bit
values, one for 64-bit ones) to access all the DSP elements with the
correct type.

This make the code easier to read and less error prone, and allow GCC
to vectorize the code in some cases.

Reviewed-by: Eric Johnson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 6de0e6c13e275a59de7fcf5dee26c5a88e3a2ebe
      
https://github.com/qemu/qemu/commit/6de0e6c13e275a59de7fcf5dee26c5a88e3a2ebe
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips: use DSP unions for binary DSP operators

This allow to reduce the number of macros.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 75d012ac7f5c92ac5ee2c1dee8c7a7fbeb724e3c
      
https://github.com/qemu/qemu/commit/75d012ac7f5c92ac5ee2c1dee8c7a7fbeb724e3c
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips: use DSP unions for unary DSP operators

This allow to reduce the number of macros.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 0a16c79cc4087838ae5f2bc9554d91db2cbb2503
      
https://github.com/qemu/qemu/commit/0a16c79cc4087838ae5f2bc9554d91db2cbb2503
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/dsp_helper.c

  Log Message:
  -----------
  target-mips: use DSP unions for reduction add instructions

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: df6126a7f21a1a032e41b15899ca29777399d5a2
      
https://github.com/qemu/qemu/commit/df6126a7f21a1a032e41b15899ca29777399d5a2
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/dsp_helper.c
    M target-mips/helper.h
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: implement DSP (d)append sub-class with TCG

DSP instruction from the (d)append sub-class can be implemented with
TCG. Use a different function for these instructions are they are quite
different from compare-pick sub-class.

Fix BALIGN instruction for negative value, where the value should be
zero-extended before being shift to the right.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 810ded13792042d988c8dbdea3b97eedbd949b40
      
https://github.com/qemu/qemu/commit/810ded13792042d988c8dbdea3b97eedbd949b40
  Author: Aurelien Jarno <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-arm/cpu.c
    M target-arm/helper.c
    M target-arm/translate.c

  Log Message:
  -----------
  Merge branch 'target-arm.next' of 
git://git.linaro.org/people/pmaydell/qemu-arm

* 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-arm:
  target-arm: Rename CPU types
  target-arm: Fix TCG temp leaks for WI and UNDEF VFP sysreg writes


  Commit: 17e8fef1af2db3a13613a311db2ec2f7a69645a1
      
https://github.com/qemu/qemu/commit/17e8fef1af2db3a13613a311db2ec2f7a69645a1
  Author: Richard Sandiford <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Fix signedness of loads in MIPS16 RESTOREs

Make RESTORE use sign-extending rather than zero-extending loads.

Signed-off-by: Richard Sandiford <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: c728154bbbc1a86465a0fd6bfc839bc9710ac374
      
https://github.com/qemu/qemu/commit/c728154bbbc1a86465a0fd6bfc839bc9710ac374
  Author: Richard Sandiford <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Sign-extend the result of LWR

Sign-extend the result of LWR, as is already done for LWL.  This is necessary
in the case where LWR loads the full word (i.e. the address is actually
aligned).  In the other cases, it is implementation defined whether the
upper 32 bits of the result are unchanged or a copy of bit 31.  The latter
seems easier to implement.

Previously the code used:

    (oldval & (0xfffffffe << (31 - bitshift))) | (newval >> bitshift)

which zeroed the upper bits of the register, losing any previous sign
extension in the unaligned cases.

Signed-off-by: Richard Sandiford <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: f54c35d1ea287beb26f6e929e2362cbc9dcfec07
      
https://github.com/qemu/qemu/commit/f54c35d1ea287beb26f6e929e2362cbc9dcfec07
  Author: Richard Sandiford <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/op_helper.c

  Log Message:
  -----------
  target-mips: Unfuse {,N}M{ADD,SUB}.fmt

Turn MADD.fmt, MSUB.fmt, NMADD.fmt and NMSUB.fmt from fused to unfused
operations, so that they behave in the same way as a separate multiplication
and addition.  The instructions were only fused in early MIPS IV processors.

Signed-off-by: Richard Sandiford <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 6f0af30449b4780c65723d0d45d0f956af5e8c4e
      
https://github.com/qemu/qemu/commit/6f0af30449b4780c65723d0d45d0f956af5e8c4e
  Author: Petar Jovanovic <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: enable access to DSP ASE if implemented

compute_hflags() will reset DSP h-flags, so MX bit should be initially set
for usermode in cpu_state_reset() if DSP ASE is implemented.
This change will bring back user-mode support for DSP ASE, since one of the
recent changes broke it.

Signed-off-by: Petar Jovanovic <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: e62a214cd49f836339fe3fd8126fc81d66c3c917
      
https://github.com/qemu/qemu/commit/e62a214cd49f836339fe3fd8126fc81d66c3c917
  Author: Petar Jovanovic <address@hidden>
  Date:   2013-01-31 (Thu, 31 Jan 2013)

  Changed paths:
    M tests/tcg/mips/mips32-dsp/mthlip.c

  Log Message:
  -----------
  target-mips: fix incorrect test for MTHLIP

The pos field in the DSPControl register is not correctly initialized.
Per documentation, the result of MTHLIP is unpredictable if the value of the
pos field before the execution is greater than 32.

Signed-off-by: Petar Jovanovic <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/321f21170782...e62a214cd49f
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