[Qemu-commits] [qemu/qemu] d17bd1: tcg/arm: fix TLB access in qemu-ld/st ops

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d17bd1d8cc27f8c1a24c65f555a77a661c332b7f
      
https://github.com/qemu/qemu/commit/d17bd1d8cc27f8c1a24c65f555a77a661c332b7f
  Author: Aurelien Jarno <address@hidden>
  Date:   2012-11-24 (Sat, 24 Nov 2012)

  Changed paths:
    M tcg/arm/tcg-target.c

  Log Message:
  -----------
  tcg/arm: fix TLB access in qemu-ld/st ops

The TCG arm backend considers likely that the offset to the TLB
entries does not exceed 12 bits for mem_index = 0. In practice this is
not true for at least the MIPS target.

The current patch fixes that by loading the bits 23-12 with a separate
instruction, and using loads with address writeback, independently of
the value of mem_idx. In total this allow a 24-bit offset, which is a
lot more than needed.

Cc: Andrzej Zaborowski <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: address@hidden
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 7aab08aa786e3a8838beac758ee61c5000144937
      
https://github.com/qemu/qemu/commit/7aab08aa786e3a8838beac758ee61c5000144937
  Author: Aurelien Jarno <address@hidden>
  Date:   2012-11-24 (Sat, 24 Nov 2012)

  Changed paths:
    M tcg/arm/tcg-target.c

  Log Message:
  -----------
  tcg/arm: fix cross-endian qemu_st16

The bswap16 TCG opcode assumes that the high bytes of the temp equal
to 0 before calling it. The ARM backend implementation takes this
assumption to slightly optimize the generated code.

The same implementation is called for implementing the cross-endian
qemu_st16 opcode, where this assumption is not true anymore. One way to
fix that would be to zero the high bytes before calling it. Given the
store instruction just ignore them, it is possible to provide a slightly
more optimized version. With ARMv6+ the rev16 instruction does the work
correctly. For lower ARM versions the patch provides a version which
behaves correctly with non-zero high bytes, but fill them with junk.

Cc: Andrzej Zaborowski <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 44e04d3b945ba6f5cc87e65192081da4783f73fa
      
https://github.com/qemu/qemu/commit/44e04d3b945ba6f5cc87e65192081da4783f73fa
  Author: Aurelien Jarno <address@hidden>
  Date:   2012-11-24 (Sat, 24 Nov 2012)

  Changed paths:
    M target-openrisc/cpu.h

  Log Message:
  -----------
  target-openrisc: remove conflicting definitions from cpu.h

On an ARM host, the registers definitions from cpu.h clash
with /usr/include/sys/ucontext.h. As there are unused, just remove
them.

Cc: Jia Liu <address@hidden>
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: d132c79f6b68622e8a115327d1f60176e1816c7c
      
https://github.com/qemu/qemu/commit/d132c79f6b68622e8a115327d1f60176e1816c7c
  Author: 陳韋任 (Wei-Ren Chen) <address@hidden>
  Date:   2012-11-24 (Sat, 24 Nov 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Add comments on POOL32Axf encoding

  Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
and microMIPS32 DSP. Add comment here to help reading.

Signed-off-by: Chen Wei-Ren <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 211da99290c8d570eee78f3f534f7e7d9d8f9da8
      
https://github.com/qemu/qemu/commit/211da99290c8d570eee78f3f534f7e7d9d8f9da8
  Author: 陳韋任 (Wei-Ren Chen) <address@hidden>
  Date:   2012-11-24 (Sat, 24 Nov 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: Clean up microMIPS32 major opcode

  I check MIPS microMIPS manual [1], and found the major opcode might
be wrong. I add a comment to explicitly indicate what manual I am refering
to, and according that manual I remove microMIPS32 major opcodes 0x1f.
As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order
MIPS ISA level or new revision of this microMIPS architecture. Quote
from Johnson, they are belong MIPS64 [2].

[1] http://www.mips.com/products/architectures/micromips/#specifications

    MIPS Architecture for Programmers Volume II-B:
      The microMIPS32 Instruction Set (Revision 3.05)

    MD00582-2B-microMIPS-AFP-03.05.pdf

[2] http://www.mips.com/products/architectures/mips64/

    MIPS Architecture For Programmers
      Volume II-A: The MIPS64 Instruction Set

    MD00087-2B-MIPS64BIS-AFP-03.51.pdf

Signed-off-by: Chen Wei-Ren <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: e5138db510efb61523be92c225d8c65eb985fff0
      
https://github.com/qemu/qemu/commit/e5138db510efb61523be92c225d8c65eb985fff0
  Author: Aurelien Jarno <address@hidden>
  Date:   2012-11-24 (Sat, 24 Nov 2012)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: mark local temps as MEM in dead_temp()

In dead_temp, local temps should always be marked as back to memory,
even if they have not been allocated (i.e. they are discared before
cross a basic block).

It fixes the following assertion in target-xtensa:

    qemu-system-xtensa: tcg/tcg.c:1665: temp_save: Assertion 
`s->temps[temp].val_type == 2 || s->temps[temp].fixed_reg' failed.
    Aborted

Reported-by: Max Filippov <address@hidden>
Tested-by: Max Filippov <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1ccbc2851282...e5138db510ef