[Qemu-commits] [qemu/qemu] 68d001: mips/malta: fix CBUS UART interrupt pin

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 68d001928b151a0c50f367c0bdca645b3d5e9ed3
      
https://github.com/qemu/qemu/commit/68d001928b151a0c50f367c0bdca645b3d5e9ed3
  Author: Aurelien Jarno <address@hidden>
  Date:   2012-11-15 (Thu, 15 Nov 2012)

  Changed paths:
    M hw/mips_malta.c

  Log Message:
  -----------
  mips/malta: fix CBUS UART interrupt pin

According to the MIPS Malta Developement Platform User's Manual, the
i8259 interrupt controller is supposed to be connected to the hardware
IRQ0, and the CBUS UART to the hardware interrupt 2.

In QEMU they are both connected to hardware interrupt 0, the CBUS UART
interrupt being wrong. This patch fixes that. It should be noted that
the irq array in QEMU includes the software interrupts, hence
env->irq[2] is the first hardware interrupt.

Cc: Ralf Baechle <address@hidden>
Reviewed-by: Eric Johnson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


  Commit: 6801038bc52d61f81ac8a25fbe392f1bad982887
      
https://github.com/qemu/qemu/commit/6801038bc52d61f81ac8a25fbe392f1bad982887
  Author: 陳韋任 (Wei-Ren Chen) <address@hidden>
  Date:   2012-11-15 (Thu, 15 Nov 2012)

  Changed paths:
    M target-mips/translate.c

  Log Message:
  -----------
  target-mips: fix wrong microMIPS opcode encoding

While reading microMIPS decoding, I found a possible wrong opcode
encoding. According to [1] page 166, the bits 13..12 for MULTU is
0x01 rather than 0x00. Please review, thanks.

[1] MIPS Architecture for Programmers VolumeIV-e: The MIPS DSP
    Application-Specific Extension to the microMIPS32 Architecture

Signed-off-by: Chen Wei-Ren <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>


Compare: https://github.com/qemu/qemu/compare/ce34cf72fe50...6801038bc52d