[Qemu-commits] [COMMIT 930f3fe] Add some chipset doc links

[Anthony Liguori]

From: Blue Swirl <address@hidden>

Signed-off-by: Blue Swirl <address@hidden>

diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 72f15af..43be7ce 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -39,6 +39,15 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
 #define APB_DPRINTF(fmt, ...)
 #endif
 
+/*
+ * Chipset docs:
+ * PBM: "UltraSPARC IIi User's Manual",
+ * http://www.sun.com/processors/manuals/805-0087.pdf
+ *
+ * APB: "Advanced PCI Bridge (APB) User's Manual",
+ * http://www.sun.com/processors/manuals/805-1251.pdf
+ */
+
 typedef target_phys_addr_t pci_addr_t;
 #include "pci_host.h"
 
diff --git a/hw/m48t59.c b/hw/m48t59.c
index 0f45071..d5a91aa 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -41,6 +41,14 @@
  * alarm and a watchdog timer and related control registers. In the
  * PPC platform there is also a nvram lock function.
  */
+
+/*
+ * Chipset docs:
+ * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
+ * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
+ * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
+ */
+
 struct m48t59_t {
     /* Model parameters */
     uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59