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[Qemu-commits] [COMMIT d60efc6] Make CPURead/WriteFunc structure 'const'
|
From: |
Anthony Liguori |
|
Subject: |
[Qemu-commits] [COMMIT d60efc6] Make CPURead/WriteFunc structure 'const' |
|
Date: |
Thu, 27 Aug 2009 22:04:03 -0000 |
From: Blue Swirl <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>
diff --git a/cpu-common.h b/cpu-common.h
index d094194..6302372 100644
--- a/cpu-common.h
+++ b/cpu-common.h
@@ -36,8 +36,8 @@ void *qemu_get_ram_ptr(ram_addr_t addr);
/* This should not be used by devices. */
ram_addr_t qemu_ram_addr_from_host(void *ptr);
-int cpu_register_io_memory(CPUReadMemoryFunc **mem_read,
- CPUWriteMemoryFunc **mem_write,
+int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
+ CPUWriteMemoryFunc * const *mem_write,
void *opaque);
void cpu_unregister_io_memory(int table_address);
diff --git a/exec.c b/exec.c
index 131e2af..59e2a1f 100644
--- a/exec.c
+++ b/exec.c
@@ -205,8 +205,8 @@ static int tb_phys_invalidate_count;
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
target_phys_addr_t base;
- CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
- CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
+ CPUReadMemoryFunc * const *mem_read[TARGET_PAGE_SIZE][4];
+ CPUWriteMemoryFunc * const *mem_write[TARGET_PAGE_SIZE][4];
void *opaque[TARGET_PAGE_SIZE][2][4];
ram_addr_t region_offset[TARGET_PAGE_SIZE][2][4];
} subpage_t;
@@ -2550,13 +2550,13 @@ static void unassigned_mem_writel(void *opaque,
target_phys_addr_t addr, uint32_
#endif
}
-static CPUReadMemoryFunc *unassigned_mem_read[3] = {
+static CPUReadMemoryFunc * const unassigned_mem_read[3] = {
unassigned_mem_readb,
unassigned_mem_readw,
unassigned_mem_readl,
};
-static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
+static CPUWriteMemoryFunc * const unassigned_mem_write[3] = {
unassigned_mem_writeb,
unassigned_mem_writew,
unassigned_mem_writel,
@@ -2622,13 +2622,13 @@ static void notdirty_mem_writel(void *opaque,
target_phys_addr_t ram_addr,
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
-static CPUReadMemoryFunc *error_mem_read[3] = {
+static CPUReadMemoryFunc * const error_mem_read[3] = {
NULL, /* never used */
NULL, /* never used */
NULL, /* never used */
};
-static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
+static CPUWriteMemoryFunc * const notdirty_mem_write[3] = {
notdirty_mem_writeb,
notdirty_mem_writew,
notdirty_mem_writel,
@@ -2721,13 +2721,13 @@ static void watch_mem_writel(void *opaque,
target_phys_addr_t addr,
stl_phys(addr, val);
}
-static CPUReadMemoryFunc *watch_mem_read[3] = {
+static CPUReadMemoryFunc * const watch_mem_read[3] = {
watch_mem_readb,
watch_mem_readw,
watch_mem_readl,
};
-static CPUWriteMemoryFunc *watch_mem_write[3] = {
+static CPUWriteMemoryFunc * const watch_mem_write[3] = {
watch_mem_writeb,
watch_mem_writew,
watch_mem_writel,
@@ -2819,13 +2819,13 @@ static void subpage_writel (void *opaque,
subpage_writelen(opaque, addr, value, 2);
}
-static CPUReadMemoryFunc *subpage_read[] = {
+static CPUReadMemoryFunc * const subpage_read[] = {
&subpage_readb,
&subpage_readw,
&subpage_readl,
};
-static CPUWriteMemoryFunc *subpage_write[] = {
+static CPUWriteMemoryFunc * const subpage_write[] = {
&subpage_writeb,
&subpage_writew,
&subpage_writel,
@@ -2906,8 +2906,8 @@ static int get_free_io_mem_idx(void)
value can be used with cpu_register_physical_memory(). (-1) is
returned if error. */
static int cpu_register_io_memory_fixed(int io_index,
- CPUReadMemoryFunc **mem_read,
- CPUWriteMemoryFunc **mem_write,
+ CPUReadMemoryFunc * const *mem_read,
+ CPUWriteMemoryFunc * const *mem_write,
void *opaque)
{
int i, subwidth = 0;
@@ -2932,8 +2932,8 @@ static int cpu_register_io_memory_fixed(int io_index,
return (io_index << IO_MEM_SHIFT) | subwidth;
}
-int cpu_register_io_memory(CPUReadMemoryFunc **mem_read,
- CPUWriteMemoryFunc **mem_write,
+int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
+ CPUWriteMemoryFunc * const *mem_write,
void *opaque)
{
return cpu_register_io_memory_fixed(0, mem_read, mem_write, opaque);
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 8b42fa8..13284c6 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -75,13 +75,13 @@ static uint32_t pci_apb_config_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc *pci_apb_config_write[] = {
+static CPUWriteMemoryFunc * const pci_apb_config_write[] = {
&pci_apb_config_writel,
&pci_apb_config_writel,
&pci_apb_config_writel,
};
-static CPUReadMemoryFunc *pci_apb_config_read[] = {
+static CPUReadMemoryFunc * const pci_apb_config_read[] = {
&pci_apb_config_readl,
&pci_apb_config_readl,
&pci_apb_config_readl,
@@ -124,25 +124,25 @@ static uint32_t apb_config_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc *apb_config_write[] = {
+static CPUWriteMemoryFunc * const apb_config_write[] = {
&apb_config_writel,
&apb_config_writel,
&apb_config_writel,
};
-static CPUReadMemoryFunc *apb_config_read[] = {
+static CPUReadMemoryFunc * const apb_config_read[] = {
&apb_config_readl,
&apb_config_readl,
&apb_config_readl,
};
-static CPUWriteMemoryFunc *pci_apb_write[] = {
+static CPUWriteMemoryFunc * const pci_apb_write[] = {
&pci_host_data_writeb,
&pci_host_data_writew,
&pci_host_data_writel,
};
-static CPUReadMemoryFunc *pci_apb_read[] = {
+static CPUReadMemoryFunc * const pci_apb_read[] = {
&pci_host_data_readb,
&pci_host_data_readw,
&pci_host_data_readl,
@@ -190,13 +190,13 @@ static uint32_t pci_apb_ioreadl (void *opaque,
target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
+static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
&pci_apb_iowriteb,
&pci_apb_iowritew,
&pci_apb_iowritel,
};
-static CPUReadMemoryFunc *pci_apb_ioread[] = {
+static CPUReadMemoryFunc * const pci_apb_ioread[] = {
&pci_apb_ioreadb,
&pci_apb_ioreadw,
&pci_apb_ioreadl,
diff --git a/hw/apic.c b/hw/apic.c
index 1927811..5bcf75d 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -957,13 +957,13 @@ static void apic_reset(void *opaque)
cpu_synchronize_state(s->cpu_env, 1);
}
-static CPUReadMemoryFunc *apic_mem_read[3] = {
+static CPUReadMemoryFunc * const apic_mem_read[3] = {
apic_mem_readb,
apic_mem_readw,
apic_mem_readl,
};
-static CPUWriteMemoryFunc *apic_mem_write[3] = {
+static CPUWriteMemoryFunc * const apic_mem_write[3] = {
apic_mem_writeb,
apic_mem_writew,
apic_mem_writel,
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 563397d..12f5109 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -558,13 +558,13 @@ static void gic_dist_writel(void *opaque,
target_phys_addr_t offset,
gic_dist_writew(opaque, offset + 2, value >> 16);
}
-static CPUReadMemoryFunc *gic_dist_readfn[] = {
+static CPUReadMemoryFunc * const gic_dist_readfn[] = {
gic_dist_readb,
gic_dist_readw,
gic_dist_readl
};
-static CPUWriteMemoryFunc *gic_dist_writefn[] = {
+static CPUWriteMemoryFunc * const gic_dist_writefn[] = {
gic_dist_writeb,
gic_dist_writew,
gic_dist_writel
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index 11b3787..2b494e4 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -177,13 +177,13 @@ static void arm_sysctl_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *arm_sysctl_readfn[] = {
+static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
arm_sysctl_read,
arm_sysctl_read,
arm_sysctl_read
};
-static CPUWriteMemoryFunc *arm_sysctl_writefn[] = {
+static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
arm_sysctl_write,
arm_sysctl_write,
arm_sysctl_write
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 572804f..25cbf66 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -223,13 +223,13 @@ static void sp804_write(void *opaque, target_phys_addr_t
offset,
}
}
-static CPUReadMemoryFunc *sp804_readfn[] = {
+static CPUReadMemoryFunc * const sp804_readfn[] = {
sp804_read,
sp804_read,
sp804_read
};
-static CPUWriteMemoryFunc *sp804_writefn[] = {
+static CPUWriteMemoryFunc * const sp804_writefn[] = {
sp804_write,
sp804_write,
sp804_write
@@ -311,13 +311,13 @@ static void icp_pit_write(void *opaque,
target_phys_addr_t offset,
}
-static CPUReadMemoryFunc *icp_pit_readfn[] = {
+static CPUReadMemoryFunc * const icp_pit_readfn[] = {
icp_pit_read,
icp_pit_read,
icp_pit_read
};
-static CPUWriteMemoryFunc *icp_pit_writefn[] = {
+static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
icp_pit_write,
icp_pit_write,
icp_pit_write
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 2e4f0ed..bf91331 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -105,13 +105,13 @@ static void bitband_writel(void *opaque,
target_phys_addr_t offset,
cpu_physical_memory_write(addr, (uint8_t *)&v, 4);
}
-static CPUReadMemoryFunc *bitband_readfn[] = {
+static CPUReadMemoryFunc * const bitband_readfn[] = {
bitband_readb,
bitband_readw,
bitband_readl
};
-static CPUWriteMemoryFunc *bitband_writefn[] = {
+static CPUWriteMemoryFunc * const bitband_writefn[] = {
bitband_writeb,
bitband_writew,
bitband_writel
diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c
index f93f431..b5163b6 100644
--- a/hw/axis_dev88.c
+++ b/hw/axis_dev88.c
@@ -69,13 +69,13 @@ nand_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
s->rdy = rdy;
}
-static CPUReadMemoryFunc *nand_read[] = {
+static CPUReadMemoryFunc * const nand_read[] = {
&nand_readl,
&nand_readl,
&nand_readl,
};
-static CPUWriteMemoryFunc *nand_write[] = {
+static CPUWriteMemoryFunc * const nand_write[] = {
&nand_writel,
&nand_writel,
&nand_writel,
@@ -226,12 +226,12 @@ static void gpio_writel (void *opaque, target_phys_addr_t
addr, uint32_t value)
}
}
-static CPUReadMemoryFunc *gpio_read[] = {
+static CPUReadMemoryFunc * const gpio_read[] = {
NULL, NULL,
&gpio_readl,
};
-static CPUWriteMemoryFunc *gpio_write[] = {
+static CPUWriteMemoryFunc * const gpio_write[] = {
NULL, NULL,
&gpio_writel,
};
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index 95d822a..64ff524 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2156,13 +2156,13 @@ static void cirrus_vga_mem_writel(void *opaque,
target_phys_addr_t addr, uint32_
#endif
}
-static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
+static CPUReadMemoryFunc * const cirrus_vga_mem_read[3] = {
cirrus_vga_mem_readb,
cirrus_vga_mem_readw,
cirrus_vga_mem_readl,
};
-static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
+static CPUWriteMemoryFunc * const cirrus_vga_mem_write[3] = {
cirrus_vga_mem_writeb,
cirrus_vga_mem_writew,
cirrus_vga_mem_writel,
@@ -2472,13 +2472,13 @@ static void cirrus_linear_writel(void *opaque,
target_phys_addr_t addr,
}
-static CPUReadMemoryFunc *cirrus_linear_read[3] = {
+static CPUReadMemoryFunc * const cirrus_linear_read[3] = {
cirrus_linear_readb,
cirrus_linear_readw,
cirrus_linear_readl,
};
-static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
+static CPUWriteMemoryFunc * const cirrus_linear_write[3] = {
cirrus_linear_writeb,
cirrus_linear_writew,
cirrus_linear_writel,
@@ -2573,13 +2573,13 @@ static void cirrus_linear_bitblt_writel(void *opaque,
target_phys_addr_t addr,
}
-static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
+static CPUReadMemoryFunc * const cirrus_linear_bitblt_read[3] = {
cirrus_linear_bitblt_readb,
cirrus_linear_bitblt_readw,
cirrus_linear_bitblt_readl,
};
-static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
+static CPUWriteMemoryFunc * const cirrus_linear_bitblt_write[3] = {
cirrus_linear_bitblt_writeb,
cirrus_linear_bitblt_writew,
cirrus_linear_bitblt_writel,
@@ -3003,13 +3003,13 @@ static void cirrus_mmio_writel(void *opaque,
target_phys_addr_t addr,
}
-static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
+static CPUReadMemoryFunc * const cirrus_mmio_read[3] = {
cirrus_mmio_readb,
cirrus_mmio_readw,
cirrus_mmio_readl,
};
-static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
+static CPUWriteMemoryFunc * const cirrus_mmio_write[3] = {
cirrus_mmio_writeb,
cirrus_mmio_writew,
cirrus_mmio_writel,
diff --git a/hw/cs4231.c b/hw/cs4231.c
index f13815b..82e2f52 100644
--- a/hw/cs4231.c
+++ b/hw/cs4231.c
@@ -129,13 +129,13 @@ static void cs_mem_writel(void *opaque,
target_phys_addr_t addr, uint32_t val)
}
}
-static CPUReadMemoryFunc *cs_mem_read[3] = {
+static CPUReadMemoryFunc * const cs_mem_read[3] = {
cs_mem_readl,
cs_mem_readl,
cs_mem_readl,
};
-static CPUWriteMemoryFunc *cs_mem_write[3] = {
+static CPUWriteMemoryFunc * const cs_mem_write[3] = {
cs_mem_writel,
cs_mem_writel,
cs_mem_writel,
diff --git a/hw/cuda.c b/hw/cuda.c
index a948ec0..3acd881 100644
--- a/hw/cuda.c
+++ b/hw/cuda.c
@@ -630,13 +630,13 @@ static uint32_t cuda_readl (void *opaque,
target_phys_addr_t addr)
return 0;
}
-static CPUWriteMemoryFunc *cuda_write[] = {
+static CPUWriteMemoryFunc * const cuda_write[] = {
&cuda_writeb,
&cuda_writew,
&cuda_writel,
};
-static CPUReadMemoryFunc *cuda_read[] = {
+static CPUReadMemoryFunc * const cuda_read[] = {
&cuda_readb,
&cuda_readw,
&cuda_readl,
diff --git a/hw/dp8393x.c b/hw/dp8393x.c
index b700d7e..fcf0398 100644
--- a/hw/dp8393x.c
+++ b/hw/dp8393x.c
@@ -663,13 +663,13 @@ static void dp8393x_writel(void *opaque,
target_phys_addr_t addr, uint32_t val)
dp8393x_writew(opaque, addr + 2, (val >> 16) & 0xffff);
}
-static CPUReadMemoryFunc *dp8393x_read[3] = {
+static CPUReadMemoryFunc * const dp8393x_read[3] = {
dp8393x_readb,
dp8393x_readw,
dp8393x_readl,
};
-static CPUWriteMemoryFunc *dp8393x_write[3] = {
+static CPUWriteMemoryFunc * const dp8393x_write[3] = {
dp8393x_writeb,
dp8393x_writew,
dp8393x_writel,
diff --git a/hw/ds1225y.c b/hw/ds1225y.c
index 4475717..009d127 100644
--- a/hw/ds1225y.c
+++ b/hw/ds1225y.c
@@ -126,19 +126,19 @@ static void nvram_writel_protected (void *opaque,
target_phys_addr_t addr, uint3
nvram_writeb_protected(opaque, addr + 3, (val >> 24) & 0xff);
}
-static CPUReadMemoryFunc *nvram_read[] = {
+static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
&nvram_readl,
};
-static CPUWriteMemoryFunc *nvram_write[] = {
+static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writeb,
&nvram_writew,
&nvram_writel,
};
-static CPUWriteMemoryFunc *nvram_write_protected[] = {
+static CPUWriteMemoryFunc * const nvram_write_protected[] = {
&nvram_writeb_protected,
&nvram_writew_protected,
&nvram_writel_protected,
diff --git a/hw/e1000.c b/hw/e1000.c
index b0542d7..d95a6c8 100644
--- a/hw/e1000.c
+++ b/hw/e1000.c
@@ -1020,11 +1020,11 @@ static const uint32_t mac_reg_init[] = {
/* PCI interface */
-static CPUWriteMemoryFunc *e1000_mmio_write[] = {
+static CPUWriteMemoryFunc * const e1000_mmio_write[] = {
e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel
};
-static CPUReadMemoryFunc *e1000_mmio_read[] = {
+static CPUReadMemoryFunc * const e1000_mmio_read[] = {
e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl
};
diff --git a/hw/eccmemctl.c b/hw/eccmemctl.c
index a19a112..c8eac38 100644
--- a/hw/eccmemctl.c
+++ b/hw/eccmemctl.c
@@ -221,13 +221,13 @@ static uint32_t ecc_mem_readl(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *ecc_mem_read[3] = {
+static CPUReadMemoryFunc * const ecc_mem_read[3] = {
NULL,
NULL,
ecc_mem_readl,
};
-static CPUWriteMemoryFunc *ecc_mem_write[3] = {
+static CPUWriteMemoryFunc * const ecc_mem_write[3] = {
NULL,
NULL,
ecc_mem_writel,
@@ -251,13 +251,13 @@ static uint32_t ecc_diag_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *ecc_diag_mem_read[3] = {
+static CPUReadMemoryFunc * const ecc_diag_mem_read[3] = {
ecc_diag_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *ecc_diag_mem_write[3] = {
+static CPUWriteMemoryFunc * const ecc_diag_mem_write[3] = {
ecc_diag_mem_writeb,
NULL,
NULL,
diff --git a/hw/eepro100.c b/hw/eepro100.c
index ec31a6a..8988b3f 100644
--- a/hw/eepro100.c
+++ b/hw/eepro100.c
@@ -1405,13 +1405,13 @@ static uint32_t pci_mmio_readl(void *opaque,
target_phys_addr_t addr)
return eepro100_read4(s, addr);
}
-static CPUWriteMemoryFunc *pci_mmio_write[] = {
+static CPUWriteMemoryFunc * const pci_mmio_write[] = {
pci_mmio_writeb,
pci_mmio_writew,
pci_mmio_writel
};
-static CPUReadMemoryFunc *pci_mmio_read[] = {
+static CPUReadMemoryFunc * const pci_mmio_read[] = {
pci_mmio_readb,
pci_mmio_readw,
pci_mmio_readl
diff --git a/hw/escc.c b/hw/escc.c
index 031dae3..ae3b802 100644
--- a/hw/escc.c
+++ b/hw/escc.c
@@ -654,13 +654,13 @@ static void serial_event(void *opaque, int event)
serial_receive_break(s);
}
-static CPUReadMemoryFunc *escc_mem_read[3] = {
+static CPUReadMemoryFunc * const escc_mem_read[3] = {
escc_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *escc_mem_write[3] = {
+static CPUWriteMemoryFunc * const escc_mem_write[3] = {
escc_mem_writeb,
NULL,
NULL,
diff --git a/hw/esp.c b/hw/esp.c
index 5331022..ed3cb58 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -579,13 +579,13 @@ static void esp_mem_writeb(void *opaque,
target_phys_addr_t addr, uint32_t val)
s->wregs[saddr] = val;
}
-static CPUReadMemoryFunc *esp_mem_read[3] = {
+static CPUReadMemoryFunc * const esp_mem_read[3] = {
esp_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *esp_mem_write[3] = {
+static CPUWriteMemoryFunc * const esp_mem_write[3] = {
esp_mem_writeb,
NULL,
esp_mem_writeb,
diff --git a/hw/etraxfs_dma.c b/hw/etraxfs_dma.c
index 4117535..15c8ad3 100644
--- a/hw/etraxfs_dma.c
+++ b/hw/etraxfs_dma.c
@@ -668,13 +668,13 @@ dma_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
}
}
-static CPUReadMemoryFunc *dma_read[] = {
+static CPUReadMemoryFunc * const dma_read[] = {
&dma_rinvalid,
&dma_rinvalid,
&dma_readl,
};
-static CPUWriteMemoryFunc *dma_write[] = {
+static CPUWriteMemoryFunc * const dma_write[] = {
&dma_winvalid,
&dma_winvalid,
&dma_writel,
diff --git a/hw/etraxfs_eth.c b/hw/etraxfs_eth.c
index e1e5d8c..54786c5 100644
--- a/hw/etraxfs_eth.c
+++ b/hw/etraxfs_eth.c
@@ -544,12 +544,12 @@ static void eth_set_link(VLANClientState *vc)
eth->phy.link = !vc->link_down;
}
-static CPUReadMemoryFunc *eth_read[] = {
+static CPUReadMemoryFunc * const eth_read[] = {
NULL, NULL,
ð_readl,
};
-static CPUWriteMemoryFunc *eth_write[] = {
+static CPUWriteMemoryFunc * const eth_write[] = {
NULL, NULL,
ð_writel,
};
diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
index 4527d98..6e063c8 100644
--- a/hw/etraxfs_pic.c
+++ b/hw/etraxfs_pic.c
@@ -99,12 +99,12 @@ pic_writel (void *opaque, target_phys_addr_t addr, uint32_t
value)
}
}
-static CPUReadMemoryFunc *pic_read[] = {
+static CPUReadMemoryFunc * const pic_read[] = {
NULL, NULL,
&pic_readl,
};
-static CPUWriteMemoryFunc *pic_write[] = {
+static CPUWriteMemoryFunc * const pic_write[] = {
NULL, NULL,
&pic_writel,
};
diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
index 7cb5e71..5b5b6c0 100644
--- a/hw/etraxfs_ser.c
+++ b/hw/etraxfs_ser.c
@@ -122,12 +122,12 @@ ser_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
ser_update_irq(s);
}
-static CPUReadMemoryFunc *ser_read[] = {
+static CPUReadMemoryFunc * const ser_read[] = {
NULL, NULL,
&ser_readl,
};
-static CPUWriteMemoryFunc *ser_write[] = {
+static CPUWriteMemoryFunc * const ser_write[] = {
NULL, NULL,
&ser_writel,
};
diff --git a/hw/etraxfs_timer.c b/hw/etraxfs_timer.c
index 450e7d1..c2b2b10 100644
--- a/hw/etraxfs_timer.c
+++ b/hw/etraxfs_timer.c
@@ -285,12 +285,12 @@ timer_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
}
}
-static CPUReadMemoryFunc *timer_read[] = {
+static CPUReadMemoryFunc * const timer_read[] = {
NULL, NULL,
&timer_readl,
};
-static CPUWriteMemoryFunc *timer_write[] = {
+static CPUWriteMemoryFunc * const timer_write[] = {
NULL, NULL,
&timer_writel,
};
diff --git a/hw/fdc.c b/hw/fdc.c
index c55560f..dabbf3a 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -603,25 +603,25 @@ static void fdctrl_write_mem (void *opaque,
fdctrl_write(opaque, (uint32_t)reg, value);
}
-static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
+static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
fdctrl_read_mem,
fdctrl_read_mem,
fdctrl_read_mem,
};
-static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
+static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
fdctrl_write_mem,
fdctrl_write_mem,
fdctrl_write_mem,
};
-static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
+static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
fdctrl_read_mem,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
+static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
fdctrl_write_mem,
NULL,
NULL,
diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index 518f280..85f433a 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -133,25 +133,25 @@ static void fw_cfg_mem_writew(void *opaque,
target_phys_addr_t addr,
fw_cfg_select(opaque, (uint16_t)value);
}
-static CPUReadMemoryFunc *fw_cfg_ctl_mem_read[3] = {
+static CPUReadMemoryFunc * const fw_cfg_ctl_mem_read[3] = {
NULL,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *fw_cfg_ctl_mem_write[3] = {
+static CPUWriteMemoryFunc * const fw_cfg_ctl_mem_write[3] = {
NULL,
fw_cfg_mem_writew,
NULL,
};
-static CPUReadMemoryFunc *fw_cfg_data_mem_read[3] = {
+static CPUReadMemoryFunc * const fw_cfg_data_mem_read[3] = {
fw_cfg_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *fw_cfg_data_mem_write[3] = {
+static CPUWriteMemoryFunc * const fw_cfg_data_mem_write[3] = {
fw_cfg_mem_writeb,
NULL,
NULL,
diff --git a/hw/g364fb.c b/hw/g364fb.c
index 6aaca7a..d44fcc2 100644
--- a/hw/g364fb.c
+++ b/hw/g364fb.c
@@ -522,13 +522,13 @@ static void g364fb_ctrl_writeb(void *opaque,
target_phys_addr_t addr, uint32_t v
g364fb_ctrl_writel(opaque, addr & ~0x3, val);
}
-static CPUReadMemoryFunc *g364fb_ctrl_read[3] = {
+static CPUReadMemoryFunc * const g364fb_ctrl_read[3] = {
g364fb_ctrl_readb,
g364fb_ctrl_readw,
g364fb_ctrl_readl,
};
-static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = {
+static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
g364fb_ctrl_writeb,
g364fb_ctrl_writew,
g364fb_ctrl_writel,
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index b893ebe..5b6778e 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -72,25 +72,25 @@ static uint32_t pci_grackle_config_readl (void *opaque,
target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
+static CPUWriteMemoryFunc * const pci_grackle_config_write[] = {
&pci_grackle_config_writel,
&pci_grackle_config_writel,
&pci_grackle_config_writel,
};
-static CPUReadMemoryFunc *pci_grackle_config_read[] = {
+static CPUReadMemoryFunc * const pci_grackle_config_read[] = {
&pci_grackle_config_readl,
&pci_grackle_config_readl,
&pci_grackle_config_readl,
};
-static CPUWriteMemoryFunc *pci_grackle_write[] = {
+static CPUWriteMemoryFunc * const pci_grackle_write[] = {
&pci_host_data_writeb,
&pci_host_data_writew,
&pci_host_data_writel,
};
-static CPUReadMemoryFunc *pci_grackle_read[] = {
+static CPUReadMemoryFunc * const pci_grackle_read[] = {
&pci_host_data_readb,
&pci_host_data_readw,
&pci_host_data_readl,
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 3b44fc9..2115130 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -854,13 +854,13 @@ static uint32_t gt64120_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc *gt64120_write[] = {
+static CPUWriteMemoryFunc * const gt64120_write[] = {
>64120_writel,
>64120_writel,
>64120_writel,
};
-static CPUReadMemoryFunc *gt64120_read[] = {
+static CPUReadMemoryFunc * const gt64120_read[] = {
>64120_readl,
>64120_readl,
>64120_readl,
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index cdb6644..500b9f1 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -126,13 +126,13 @@ static uint32_t pic_readl (void *opaque,
target_phys_addr_t addr)
return value;
}
-static CPUWriteMemoryFunc *pic_write[] = {
+static CPUWriteMemoryFunc * const pic_write[] = {
&pic_writel,
&pic_writel,
&pic_writel,
};
-static CPUReadMemoryFunc *pic_read[] = {
+static CPUReadMemoryFunc * const pic_read[] = {
&pic_readl,
&pic_readl,
&pic_readl,
diff --git a/hw/hpet.c b/hw/hpet.c
index 01b10aa..20df7ef 100644
--- a/hw/hpet.c
+++ b/hw/hpet.c
@@ -508,7 +508,7 @@ static void hpet_ram_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *hpet_ram_read[] = {
+static CPUReadMemoryFunc * const hpet_ram_read[] = {
#ifdef HPET_DEBUG
hpet_ram_readb,
hpet_ram_readw,
@@ -519,7 +519,7 @@ static CPUReadMemoryFunc *hpet_ram_read[] = {
hpet_ram_readl,
};
-static CPUWriteMemoryFunc *hpet_ram_write[] = {
+static CPUWriteMemoryFunc * const hpet_ram_write[] = {
#ifdef HPET_DEBUG
hpet_ram_writeb,
hpet_ram_writew,
diff --git a/hw/ide.c b/hw/ide.c
index 637b082..0bde632 100644
--- a/hw/ide.c
+++ b/hw/ide.c
@@ -3906,13 +3906,13 @@ static uint32_t pmac_ide_readl (void
*opaque,target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc *pmac_ide_write[] = {
+static CPUWriteMemoryFunc * const pmac_ide_write[] = {
pmac_ide_writeb,
pmac_ide_writew,
pmac_ide_writel,
};
-static CPUReadMemoryFunc *pmac_ide_read[] = {
+static CPUReadMemoryFunc * const pmac_ide_read[] = {
pmac_ide_readb,
pmac_ide_readw,
pmac_ide_readl,
@@ -4026,13 +4026,13 @@ static void mmio_ide_write (void *opaque,
target_phys_addr_t addr,
ide_data_writew(ide, 0, val);
}
-static CPUReadMemoryFunc *mmio_ide_reads[] = {
+static CPUReadMemoryFunc * const mmio_ide_reads[] = {
mmio_ide_read,
mmio_ide_read,
mmio_ide_read,
};
-static CPUWriteMemoryFunc *mmio_ide_writes[] = {
+static CPUWriteMemoryFunc * const mmio_ide_writes[] = {
mmio_ide_write,
mmio_ide_write,
mmio_ide_write,
@@ -4053,13 +4053,13 @@ static void mmio_ide_cmd_write (void *opaque,
target_phys_addr_t addr,
ide_cmd_write(ide, 0, val);
}
-static CPUReadMemoryFunc *mmio_ide_status[] = {
+static CPUReadMemoryFunc * const mmio_ide_status[] = {
mmio_ide_status_read,
mmio_ide_status_read,
mmio_ide_status_read,
};
-static CPUWriteMemoryFunc *mmio_ide_cmd[] = {
+static CPUWriteMemoryFunc * const mmio_ide_cmd[] = {
mmio_ide_cmd_write,
mmio_ide_cmd_write,
mmio_ide_cmd_write,
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index 2d83004..e8b5194 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -215,13 +215,13 @@ static void integratorcm_write(void *opaque,
target_phys_addr_t offset,
/* Integrator/CM control registers. */
-static CPUReadMemoryFunc *integratorcm_readfn[] = {
+static CPUReadMemoryFunc * const integratorcm_readfn[] = {
integratorcm_read,
integratorcm_read,
integratorcm_read
};
-static CPUWriteMemoryFunc *integratorcm_writefn[] = {
+static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
integratorcm_write,
integratorcm_write,
integratorcm_write
@@ -360,13 +360,13 @@ static void icp_pic_write(void *opaque,
target_phys_addr_t offset,
icp_pic_update(s);
}
-static CPUReadMemoryFunc *icp_pic_readfn[] = {
+static CPUReadMemoryFunc * const icp_pic_readfn[] = {
icp_pic_read,
icp_pic_read,
icp_pic_read
};
-static CPUWriteMemoryFunc *icp_pic_writefn[] = {
+static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
icp_pic_write,
icp_pic_write,
icp_pic_write
@@ -416,13 +416,13 @@ static void icp_control_write(void *opaque,
target_phys_addr_t offset,
hw_error("icp_control_write: Bad offset %x\n", (int)offset);
}
}
-static CPUReadMemoryFunc *icp_control_readfn[] = {
+static CPUReadMemoryFunc * const icp_control_readfn[] = {
icp_control_read,
icp_control_read,
icp_control_read
};
-static CPUWriteMemoryFunc *icp_control_writefn[] = {
+static CPUWriteMemoryFunc * const icp_control_writefn[] = {
icp_control_write,
icp_control_write,
icp_control_write
diff --git a/hw/ioapic.c b/hw/ioapic.c
index 998894d..b232527 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -229,13 +229,13 @@ static void ioapic_reset(void *opaque)
s->ioredtbl[i] = 1 << 16; /* mask LVT */
}
-static CPUReadMemoryFunc *ioapic_mem_read[3] = {
+static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
ioapic_mem_readl,
ioapic_mem_readl,
ioapic_mem_readl,
};
-static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
+static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
ioapic_mem_writel,
ioapic_mem_writel,
ioapic_mem_writel,
diff --git a/hw/iommu.c b/hw/iommu.c
index 52385f7..ff8b415 100644
--- a/hw/iommu.c
+++ b/hw/iommu.c
@@ -238,13 +238,13 @@ static void iommu_mem_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *iommu_mem_read[3] = {
+static CPUReadMemoryFunc * const iommu_mem_read[3] = {
NULL,
NULL,
iommu_mem_readl,
};
-static CPUWriteMemoryFunc *iommu_mem_write[3] = {
+static CPUWriteMemoryFunc * const iommu_mem_write[3] = {
NULL,
NULL,
iommu_mem_writel,
diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c
index 868c7b0..ec5da5f 100644
--- a/hw/isa_mmio.c
+++ b/hw/isa_mmio.c
@@ -79,13 +79,13 @@ static uint32_t isa_mmio_readl (void *opaque,
target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc *isa_mmio_write[] = {
+static CPUWriteMemoryFunc * const isa_mmio_write[] = {
&isa_mmio_writeb,
&isa_mmio_writew,
&isa_mmio_writel,
};
-static CPUReadMemoryFunc *isa_mmio_read[] = {
+static CPUReadMemoryFunc * const isa_mmio_read[] = {
&isa_mmio_readb,
&isa_mmio_readw,
&isa_mmio_readl,
diff --git a/hw/jazz_led.c b/hw/jazz_led.c
index 9fdaf8f..18780e9 100644
--- a/hw/jazz_led.c
+++ b/hw/jazz_led.c
@@ -131,13 +131,13 @@ static void led_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
#endif
}
-static CPUReadMemoryFunc *led_read[3] = {
+static CPUReadMemoryFunc * const led_read[3] = {
led_readb,
led_readw,
led_readl,
};
-static CPUWriteMemoryFunc *led_write[3] = {
+static CPUWriteMemoryFunc * const led_write[3] = {
led_writeb,
led_writew,
led_writel,
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index f749a45..d41b8ba 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -1779,13 +1779,13 @@ static uint32_t lsi_mmio_readl(void *opaque,
target_phys_addr_t addr)
return val;
}
-static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
+static CPUReadMemoryFunc * const lsi_mmio_readfn[3] = {
lsi_mmio_readb,
lsi_mmio_readw,
lsi_mmio_readl,
};
-static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
+static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
lsi_mmio_writeb,
lsi_mmio_writew,
lsi_mmio_writel,
@@ -1860,13 +1860,13 @@ static uint32_t lsi_ram_readl(void *opaque,
target_phys_addr_t addr)
return le32_to_cpu(s->script_ram[addr >> 2]);
}
-static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
+static CPUReadMemoryFunc * const lsi_ram_readfn[3] = {
lsi_ram_readb,
lsi_ram_readw,
lsi_ram_readl,
};
-static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
+static CPUWriteMemoryFunc * const lsi_ram_writefn[3] = {
lsi_ram_writeb,
lsi_ram_writew,
lsi_ram_writel,
diff --git a/hw/m48t59.c b/hw/m48t59.c
index 6541cbe..3f2e3e5 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -565,13 +565,13 @@ static uint32_t nvram_readl (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc *nvram_write[] = {
+static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writeb,
&nvram_writew,
&nvram_writel,
};
-static CPUReadMemoryFunc *nvram_read[] = {
+static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
&nvram_readl,
diff --git a/hw/mac_dbdma.c b/hw/mac_dbdma.c
index 85826d8..c88ba2b 100644
--- a/hw/mac_dbdma.c
+++ b/hw/mac_dbdma.c
@@ -785,13 +785,13 @@ static uint32_t dbdma_readl (void *opaque,
target_phys_addr_t addr)
return value;
}
-static CPUWriteMemoryFunc *dbdma_write[] = {
+static CPUWriteMemoryFunc * const dbdma_write[] = {
NULL,
NULL,
dbdma_writel,
};
-static CPUReadMemoryFunc *dbdma_read[] = {
+static CPUReadMemoryFunc * const dbdma_read[] = {
NULL,
NULL,
dbdma_readl,
diff --git a/hw/mac_nvram.c b/hw/mac_nvram.c
index 1c2121c..0c91b3f 100644
--- a/hw/mac_nvram.c
+++ b/hw/mac_nvram.c
@@ -93,13 +93,13 @@ static uint32_t macio_nvram_readb (void *opaque,
target_phys_addr_t addr)
return value;
}
-static CPUWriteMemoryFunc *nvram_write[] = {
+static CPUWriteMemoryFunc * const nvram_write[] = {
&macio_nvram_writeb,
&macio_nvram_writeb,
&macio_nvram_writeb,
};
-static CPUReadMemoryFunc *nvram_read[] = {
+static CPUReadMemoryFunc * const nvram_read[] = {
&macio_nvram_readb,
&macio_nvram_readb,
&macio_nvram_readb,
diff --git a/hw/marvell_88w8618_audio.c b/hw/marvell_88w8618_audio.c
index 5c6d3a5..d6be2e7 100644
--- a/hw/marvell_88w8618_audio.c
+++ b/hw/marvell_88w8618_audio.c
@@ -221,13 +221,13 @@ static void mv88w8618_audio_reset(void *opaque)
s->irq_enable = 0;
}
-static CPUReadMemoryFunc *mv88w8618_audio_readfn[] = {
+static CPUReadMemoryFunc * const mv88w8618_audio_readfn[] = {
mv88w8618_audio_read,
mv88w8618_audio_read,
mv88w8618_audio_read
};
-static CPUWriteMemoryFunc *mv88w8618_audio_writefn[] = {
+static CPUWriteMemoryFunc * const mv88w8618_audio_writefn[] = {
mv88w8618_audio_write,
mv88w8618_audio_write,
mv88w8618_audio_write
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index 2022548..5c8676e 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -696,13 +696,13 @@ static void cmos_mm_writel (void *opaque,
cmos_ioport_write(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc *rtc_mm_read[] = {
+static CPUReadMemoryFunc * const rtc_mm_read[] = {
&cmos_mm_readb,
&cmos_mm_readw,
&cmos_mm_readl,
};
-static CPUWriteMemoryFunc *rtc_mm_write[] = {
+static CPUWriteMemoryFunc * const rtc_mm_write[] = {
&cmos_mm_writeb,
&cmos_mm_writew,
&cmos_mm_writel,
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index 049099e..c107de8 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -505,13 +505,13 @@ static void m5206_mbar_writel(void *opaque,
target_phys_addr_t offset,
m5206_mbar_write(s, offset, value);
}
-static CPUReadMemoryFunc *m5206_mbar_readfn[] = {
+static CPUReadMemoryFunc * const m5206_mbar_readfn[] = {
m5206_mbar_readb,
m5206_mbar_readw,
m5206_mbar_readl
};
-static CPUWriteMemoryFunc *m5206_mbar_writefn[] = {
+static CPUWriteMemoryFunc * const m5206_mbar_writefn[] = {
m5206_mbar_writeb,
m5206_mbar_writew,
m5206_mbar_writel
diff --git a/hw/mcf5208.c b/hw/mcf5208.c
index 1ee9680..95a03fc 100644
--- a/hw/mcf5208.c
+++ b/hw/mcf5208.c
@@ -118,13 +118,13 @@ static uint32_t m5208_timer_read(void *opaque,
target_phys_addr_t addr)
}
}
-static CPUReadMemoryFunc *m5208_timer_readfn[] = {
+static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
m5208_timer_read,
m5208_timer_read,
m5208_timer_read
};
-static CPUWriteMemoryFunc *m5208_timer_writefn[] = {
+static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
m5208_timer_write,
m5208_timer_write,
m5208_timer_write
@@ -157,13 +157,13 @@ static void m5208_sys_write(void *opaque,
target_phys_addr_t addr,
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
-static CPUReadMemoryFunc *m5208_sys_readfn[] = {
+static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
m5208_sys_read,
m5208_sys_read,
m5208_sys_read
};
-static CPUWriteMemoryFunc *m5208_sys_writefn[] = {
+static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
m5208_sys_write,
m5208_sys_write,
m5208_sys_write
diff --git a/hw/mcf_fec.c b/hw/mcf_fec.c
index 27f27a6..f6d2bab 100644
--- a/hw/mcf_fec.c
+++ b/hw/mcf_fec.c
@@ -429,13 +429,13 @@ static ssize_t mcf_fec_receive(VLANClientState *vc, const
uint8_t *buf, size_t s
return size;
}
-static CPUReadMemoryFunc *mcf_fec_readfn[] = {
+static CPUReadMemoryFunc * const mcf_fec_readfn[] = {
mcf_fec_read,
mcf_fec_read,
mcf_fec_read
};
-static CPUWriteMemoryFunc *mcf_fec_writefn[] = {
+static CPUWriteMemoryFunc * const mcf_fec_writefn[] = {
mcf_fec_write,
mcf_fec_write,
mcf_fec_write
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index e291280..f01bd32 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -127,13 +127,13 @@ static void mcf_intc_reset(mcf_intc_state *s)
s->active_vector = 24;
}
-static CPUReadMemoryFunc *mcf_intc_readfn[] = {
+static CPUReadMemoryFunc * const mcf_intc_readfn[] = {
mcf_intc_read,
mcf_intc_read,
mcf_intc_read
};
-static CPUWriteMemoryFunc *mcf_intc_writefn[] = {
+static CPUWriteMemoryFunc * const mcf_intc_writefn[] = {
mcf_intc_write,
mcf_intc_write,
mcf_intc_write
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
index 8300fe8..d16bac7 100644
--- a/hw/mcf_uart.c
+++ b/hw/mcf_uart.c
@@ -284,13 +284,13 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
}
-static CPUReadMemoryFunc *mcf_uart_readfn[] = {
+static CPUReadMemoryFunc * const mcf_uart_readfn[] = {
mcf_uart_read,
mcf_uart_read,
mcf_uart_read
};
-static CPUWriteMemoryFunc *mcf_uart_writefn[] = {
+static CPUWriteMemoryFunc * const mcf_uart_writefn[] = {
mcf_uart_write,
mcf_uart_write,
mcf_uart_write
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index e09a6b2..9740d72 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -58,13 +58,13 @@ static void rtc_writeb(void *opaque, target_phys_addr_t
addr, uint32_t val)
cpu_outw(env, 0x71, val & 0xff);
}
-static CPUReadMemoryFunc *rtc_read[3] = {
+static CPUReadMemoryFunc * const rtc_read[3] = {
rtc_readb,
rtc_readb,
rtc_readb,
};
-static CPUWriteMemoryFunc *rtc_write[3] = {
+static CPUWriteMemoryFunc * const rtc_write[3] = {
rtc_writeb,
rtc_writeb,
rtc_writeb,
@@ -76,13 +76,13 @@ static void dma_dummy_writeb(void *opaque,
target_phys_addr_t addr, uint32_t val
* the current DMA acknowledge cycle is completed. */
}
-static CPUReadMemoryFunc *dma_dummy_read[3] = {
+static CPUReadMemoryFunc * const dma_dummy_read[3] = {
NULL,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *dma_dummy_write[3] = {
+static CPUWriteMemoryFunc * const dma_dummy_write[3] = {
dma_dummy_writeb,
dma_dummy_writeb,
dma_dummy_writeb,
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 4e51c8d..d8fa264 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -387,13 +387,13 @@ static void malta_fpga_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *malta_fpga_read[] = {
+static CPUReadMemoryFunc * const malta_fpga_read[] = {
malta_fpga_readl,
malta_fpga_readl,
malta_fpga_readl
};
-static CPUWriteMemoryFunc *malta_fpga_write[] = {
+static CPUWriteMemoryFunc * const malta_fpga_write[] = {
malta_fpga_writel,
malta_fpga_writel,
malta_fpga_writel
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index 476612c..d902591 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -56,13 +56,13 @@ static uint32_t mips_qemu_readl (void *opaque,
target_phys_addr_t addr)
return 0;
}
-static CPUWriteMemoryFunc *mips_qemu_write[] = {
+static CPUWriteMemoryFunc * const mips_qemu_write[] = {
&mips_qemu_writel,
&mips_qemu_writel,
&mips_qemu_writel,
};
-static CPUReadMemoryFunc *mips_qemu_read[] = {
+static CPUReadMemoryFunc * const mips_qemu_read[] = {
&mips_qemu_readl,
&mips_qemu_readl,
&mips_qemu_readl,
diff --git a/hw/mpcore.c b/hw/mpcore.c
index 907bd99..f286d5f 100644
--- a/hw/mpcore.c
+++ b/hw/mpcore.c
@@ -243,13 +243,13 @@ bad_reg:
hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
}
-static CPUReadMemoryFunc *mpcore_priv_readfn[] = {
+static CPUReadMemoryFunc * const mpcore_priv_readfn[] = {
mpcore_priv_read,
mpcore_priv_read,
mpcore_priv_read
};
-static CPUWriteMemoryFunc *mpcore_priv_writefn[] = {
+static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
mpcore_priv_write,
mpcore_priv_write,
mpcore_priv_write
diff --git a/hw/msix.c b/hw/msix.c
index c954d47..c07d7a1 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -194,11 +194,11 @@ static void msix_mmio_write_unallowed(void *opaque,
target_phys_addr_t addr,
fprintf(stderr, "MSI-X: only dword write is allowed!\n");
}
-static CPUWriteMemoryFunc *msix_mmio_write[] = {
+static CPUWriteMemoryFunc * const msix_mmio_write[] = {
msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
};
-static CPUReadMemoryFunc *msix_mmio_read[] = {
+static CPUReadMemoryFunc * const msix_mmio_read[] = {
msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
};
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index c77328f..1b6cb77 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -164,12 +164,12 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
}
}
-static CPUReadMemoryFunc *mst_fpga_readfn[] = {
+static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
mst_fpga_readb,
mst_fpga_readb,
mst_fpga_readb,
};
-static CPUWriteMemoryFunc *mst_fpga_writefn[] = {
+static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
mst_fpga_writeb,
mst_fpga_writeb,
mst_fpga_writeb,
diff --git a/hw/musicpal.c b/hw/musicpal.c
index 72d7264..097a1f7 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -344,13 +344,13 @@ static void mv88w8618_eth_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *mv88w8618_eth_readfn[] = {
+static CPUReadMemoryFunc * const mv88w8618_eth_readfn[] = {
mv88w8618_eth_read,
mv88w8618_eth_read,
mv88w8618_eth_read
};
-static CPUWriteMemoryFunc *mv88w8618_eth_writefn[] = {
+static CPUWriteMemoryFunc * const mv88w8618_eth_writefn[] = {
mv88w8618_eth_write,
mv88w8618_eth_write,
mv88w8618_eth_write
@@ -532,13 +532,13 @@ static void musicpal_lcd_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *musicpal_lcd_readfn[] = {
+static CPUReadMemoryFunc * const musicpal_lcd_readfn[] = {
musicpal_lcd_read,
musicpal_lcd_read,
musicpal_lcd_read
};
-static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
+static CPUWriteMemoryFunc * const musicpal_lcd_writefn[] = {
musicpal_lcd_write,
musicpal_lcd_write,
musicpal_lcd_write
@@ -630,13 +630,13 @@ static void mv88w8618_pic_reset(void *opaque)
s->enabled = 0;
}
-static CPUReadMemoryFunc *mv88w8618_pic_readfn[] = {
+static CPUReadMemoryFunc * const mv88w8618_pic_readfn[] = {
mv88w8618_pic_read,
mv88w8618_pic_read,
mv88w8618_pic_read
};
-static CPUWriteMemoryFunc *mv88w8618_pic_writefn[] = {
+static CPUWriteMemoryFunc * const mv88w8618_pic_writefn[] = {
mv88w8618_pic_write,
mv88w8618_pic_write,
mv88w8618_pic_write
@@ -749,13 +749,13 @@ static void mv88w8618_pit_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *mv88w8618_pit_readfn[] = {
+static CPUReadMemoryFunc * const mv88w8618_pit_readfn[] = {
mv88w8618_pit_read,
mv88w8618_pit_read,
mv88w8618_pit_read
};
-static CPUWriteMemoryFunc *mv88w8618_pit_writefn[] = {
+static CPUWriteMemoryFunc * const mv88w8618_pit_writefn[] = {
mv88w8618_pit_write,
mv88w8618_pit_write,
mv88w8618_pit_write
@@ -812,13 +812,13 @@ static void mv88w8618_flashcfg_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *mv88w8618_flashcfg_readfn[] = {
+static CPUReadMemoryFunc * const mv88w8618_flashcfg_readfn[] = {
mv88w8618_flashcfg_read,
mv88w8618_flashcfg_read,
mv88w8618_flashcfg_read
};
-static CPUWriteMemoryFunc *mv88w8618_flashcfg_writefn[] = {
+static CPUWriteMemoryFunc * const mv88w8618_flashcfg_writefn[] = {
mv88w8618_flashcfg_write,
mv88w8618_flashcfg_write,
mv88w8618_flashcfg_write
@@ -856,13 +856,13 @@ static void musicpal_misc_write(void *opaque,
target_phys_addr_t offset,
{
}
-static CPUReadMemoryFunc *musicpal_misc_readfn[] = {
+static CPUReadMemoryFunc * const musicpal_misc_readfn[] = {
musicpal_misc_read,
musicpal_misc_read,
musicpal_misc_read,
};
-static CPUWriteMemoryFunc *musicpal_misc_writefn[] = {
+static CPUWriteMemoryFunc * const musicpal_misc_writefn[] = {
musicpal_misc_write,
musicpal_misc_write,
musicpal_misc_write,
@@ -901,13 +901,13 @@ static void mv88w8618_wlan_write(void *opaque,
target_phys_addr_t offset,
{
}
-static CPUReadMemoryFunc *mv88w8618_wlan_readfn[] = {
+static CPUReadMemoryFunc * const mv88w8618_wlan_readfn[] = {
mv88w8618_wlan_read,
mv88w8618_wlan_read,
mv88w8618_wlan_read,
};
-static CPUWriteMemoryFunc *mv88w8618_wlan_writefn[] = {
+static CPUWriteMemoryFunc * const mv88w8618_wlan_writefn[] = {
mv88w8618_wlan_write,
mv88w8618_wlan_write,
mv88w8618_wlan_write,
@@ -1099,13 +1099,13 @@ static void musicpal_gpio_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *musicpal_gpio_readfn[] = {
+static CPUReadMemoryFunc * const musicpal_gpio_readfn[] = {
musicpal_gpio_read,
musicpal_gpio_read,
musicpal_gpio_read,
};
-static CPUWriteMemoryFunc *musicpal_gpio_writefn[] = {
+static CPUWriteMemoryFunc * const musicpal_gpio_writefn[] = {
musicpal_gpio_write,
musicpal_gpio_write,
musicpal_gpio_write,
diff --git a/hw/omap.h b/hw/omap.h
index a484c82..d305779 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -1039,8 +1039,8 @@ enum {
# ifdef MEM_VERBOSE
struct io_fn {
- CPUReadMemoryFunc **mem_read;
- CPUWriteMemoryFunc **mem_write;
+ CPUReadMemoryFunc * const *mem_read;
+ CPUWriteMemoryFunc * const *mem_write;
void *opaque;
int in;
};
@@ -1112,12 +1112,12 @@ static void io_writew(void *opaque, target_phys_addr_t
addr, uint32_t value)
s->in --;
}
-static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };
-static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };
+static CPUReadMemoryFunc * const io_readfn[] = { io_readb, io_readh, io_readw,
};
+static CPUWriteMemoryFunc * const io_writefn[] = { io_writeb, io_writeh,
io_writew, };
-inline static int debug_register_io_memory(
- CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,
- void *opaque)
+inline static int debug_register_io_memory(CPUReadMemoryFunc * const *mem_read,
+ CPUWriteMemoryFunc * const
*mem_write,
+ void *opaque)
{
struct io_fn *s = qemu_malloc(sizeof(struct io_fn));
@@ -1135,8 +1135,8 @@ inline static int debug_register_io_memory(
# ifdef L4_MUX_HACK
# undef l4_register_io_memory
-int l4_register_io_memory(CPUReadMemoryFunc **mem_read,
- CPUWriteMemoryFunc **mem_write, void *opaque);
+int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
+ CPUWriteMemoryFunc * const *mem_write, void *opaque);
# endif
#endif /* hw_omap_h */
diff --git a/hw/omap1.c b/hw/omap1.c
index 93515ee..e870d96 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -366,13 +366,13 @@ static void omap_inth_write(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc *omap_inth_readfn[] = {
+static CPUReadMemoryFunc * const omap_inth_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_inth_read,
};
-static CPUWriteMemoryFunc *omap_inth_writefn[] = {
+static CPUWriteMemoryFunc * const omap_inth_writefn[] = {
omap_inth_write,
omap_inth_write,
omap_inth_write,
@@ -612,13 +612,13 @@ static void omap2_inth_write(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc *omap2_inth_readfn[] = {
+static CPUReadMemoryFunc * const omap2_inth_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap2_inth_read,
};
-static CPUWriteMemoryFunc *omap2_inth_writefn[] = {
+static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
omap2_inth_write,
omap2_inth_write,
omap2_inth_write,
@@ -795,13 +795,13 @@ static void omap_mpu_timer_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
+static CPUReadMemoryFunc * const omap_mpu_timer_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_mpu_timer_read,
};
-static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mpu_timer_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mpu_timer_write,
@@ -913,13 +913,13 @@ static void omap_wd_timer_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
+static CPUReadMemoryFunc * const omap_wd_timer_readfn[] = {
omap_badwidth_read16,
omap_wd_timer_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
+static CPUWriteMemoryFunc * const omap_wd_timer_writefn[] = {
omap_badwidth_write16,
omap_wd_timer_write,
omap_badwidth_write16,
@@ -1021,13 +1021,13 @@ static void omap_os_timer_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
+static CPUReadMemoryFunc * const omap_os_timer_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_os_timer_read,
};
-static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
+static CPUWriteMemoryFunc * const omap_os_timer_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_os_timer_write,
@@ -1243,13 +1243,13 @@ static void omap_ulpd_pm_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
+static CPUReadMemoryFunc * const omap_ulpd_pm_readfn[] = {
omap_badwidth_read16,
omap_ulpd_pm_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
+static CPUWriteMemoryFunc * const omap_ulpd_pm_writefn[] = {
omap_badwidth_write16,
omap_ulpd_pm_write,
omap_badwidth_write16,
@@ -1469,13 +1469,13 @@ static void omap_pin_cfg_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
+static CPUReadMemoryFunc * const omap_pin_cfg_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_pin_cfg_read,
};
-static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
+static CPUWriteMemoryFunc * const omap_pin_cfg_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_pin_cfg_write,
@@ -1556,13 +1556,13 @@ static void omap_id_write(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc *omap_id_readfn[] = {
+static CPUReadMemoryFunc * const omap_id_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_id_read,
};
-static CPUWriteMemoryFunc *omap_id_writefn[] = {
+static CPUWriteMemoryFunc * const omap_id_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_id_write,
@@ -1633,13 +1633,13 @@ static void omap_mpui_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_mpui_readfn[] = {
+static CPUReadMemoryFunc * const omap_mpui_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_mpui_read,
};
-static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mpui_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mpui_write,
@@ -1732,13 +1732,13 @@ static void omap_tipb_bridge_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
+static CPUReadMemoryFunc * const omap_tipb_bridge_readfn[] = {
omap_badwidth_read16,
omap_tipb_bridge_read,
omap_tipb_bridge_read,
};
-static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
+static CPUWriteMemoryFunc * const omap_tipb_bridge_writefn[] = {
omap_badwidth_write16,
omap_tipb_bridge_write,
omap_tipb_bridge_write,
@@ -1834,13 +1834,13 @@ static void omap_tcmi_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
+static CPUReadMemoryFunc * const omap_tcmi_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_tcmi_read,
};
-static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
+static CPUWriteMemoryFunc * const omap_tcmi_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_tcmi_write,
@@ -1920,13 +1920,13 @@ static void omap_dpll_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_dpll_readfn[] = {
+static CPUReadMemoryFunc * const omap_dpll_readfn[] = {
omap_badwidth_read16,
omap_dpll_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
+static CPUWriteMemoryFunc * const omap_dpll_writefn[] = {
omap_badwidth_write16,
omap_dpll_write,
omap_badwidth_write16,
@@ -2069,13 +2069,13 @@ static void omap_uart_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_uart_readfn[] = {
+static CPUReadMemoryFunc * const omap_uart_readfn[] = {
omap_uart_read,
omap_uart_read,
omap_badwidth_read8,
};
-static CPUWriteMemoryFunc *omap_uart_writefn[] = {
+static CPUWriteMemoryFunc * const omap_uart_writefn[] = {
omap_uart_write,
omap_uart_write,
omap_badwidth_write8,
@@ -2381,13 +2381,13 @@ static void omap_clkm_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_clkm_readfn[] = {
+static CPUReadMemoryFunc * const omap_clkm_readfn[] = {
omap_badwidth_read16,
omap_clkm_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
+static CPUWriteMemoryFunc * const omap_clkm_writefn[] = {
omap_badwidth_write16,
omap_clkm_write,
omap_badwidth_write16,
@@ -2464,13 +2464,13 @@ static void omap_clkdsp_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
+static CPUReadMemoryFunc * const omap_clkdsp_readfn[] = {
omap_badwidth_read16,
omap_clkdsp_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
+static CPUWriteMemoryFunc * const omap_clkdsp_writefn[] = {
omap_badwidth_write16,
omap_clkdsp_write,
omap_badwidth_write16,
@@ -2706,13 +2706,13 @@ static void omap_mpuio_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_mpuio_readfn[] = {
+static CPUReadMemoryFunc * const omap_mpuio_readfn[] = {
omap_badwidth_read16,
omap_mpuio_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_mpuio_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mpuio_writefn[] = {
omap_badwidth_write16,
omap_mpuio_write,
omap_badwidth_write16,
@@ -2919,13 +2919,13 @@ static void omap_gpio_write(void *opaque,
target_phys_addr_t addr,
}
/* *Some* sources say the memory region is 32-bit. */
-static CPUReadMemoryFunc *omap_gpio_readfn[] = {
+static CPUReadMemoryFunc * const omap_gpio_readfn[] = {
omap_badwidth_read16,
omap_gpio_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_gpio_writefn[] = {
+static CPUWriteMemoryFunc * const omap_gpio_writefn[] = {
omap_badwidth_write16,
omap_gpio_write,
omap_badwidth_write16,
@@ -3089,13 +3089,13 @@ static void omap_uwire_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_uwire_readfn[] = {
+static CPUReadMemoryFunc * const omap_uwire_readfn[] = {
omap_badwidth_read16,
omap_uwire_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_uwire_writefn[] = {
+static CPUWriteMemoryFunc * const omap_uwire_writefn[] = {
omap_badwidth_write16,
omap_uwire_write,
omap_badwidth_write16,
@@ -3188,13 +3188,13 @@ static void omap_pwl_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_pwl_readfn[] = {
+static CPUReadMemoryFunc * const omap_pwl_readfn[] = {
omap_pwl_read,
omap_badwidth_read8,
omap_badwidth_read8,
};
-static CPUWriteMemoryFunc *omap_pwl_writefn[] = {
+static CPUWriteMemoryFunc * const omap_pwl_writefn[] = {
omap_pwl_write,
omap_badwidth_write8,
omap_badwidth_write8,
@@ -3292,13 +3292,13 @@ static void omap_pwt_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_pwt_readfn[] = {
+static CPUReadMemoryFunc * const omap_pwt_readfn[] = {
omap_pwt_read,
omap_badwidth_read8,
omap_badwidth_read8,
};
-static CPUWriteMemoryFunc *omap_pwt_writefn[] = {
+static CPUWriteMemoryFunc * const omap_pwt_writefn[] = {
omap_pwt_write,
omap_badwidth_write8,
omap_badwidth_write8,
@@ -3633,13 +3633,13 @@ static void omap_rtc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_rtc_readfn[] = {
+static CPUReadMemoryFunc * const omap_rtc_readfn[] = {
omap_rtc_read,
omap_badwidth_read8,
omap_badwidth_read8,
};
-static CPUWriteMemoryFunc *omap_rtc_writefn[] = {
+static CPUWriteMemoryFunc * const omap_rtc_writefn[] = {
omap_rtc_write,
omap_badwidth_write8,
omap_badwidth_write8,
@@ -4216,13 +4216,13 @@ static void omap_mcbsp_writew(void *opaque,
target_phys_addr_t addr,
omap_badwidth_write16(opaque, addr, value);
}
-static CPUReadMemoryFunc *omap_mcbsp_readfn[] = {
+static CPUReadMemoryFunc * const omap_mcbsp_readfn[] = {
omap_badwidth_read16,
omap_mcbsp_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mcbsp_writefn[] = {
omap_badwidth_write16,
omap_mcbsp_writeh,
omap_mcbsp_writew,
@@ -4404,13 +4404,13 @@ static void omap_lpg_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_lpg_readfn[] = {
+static CPUReadMemoryFunc * const omap_lpg_readfn[] = {
omap_lpg_read,
omap_badwidth_read8,
omap_badwidth_read8,
};
-static CPUWriteMemoryFunc *omap_lpg_writefn[] = {
+static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
omap_lpg_write,
omap_badwidth_write8,
omap_badwidth_write8,
@@ -4453,13 +4453,13 @@ static uint32_t omap_mpui_io_read(void *opaque,
target_phys_addr_t addr)
return 0;
}
-static CPUReadMemoryFunc *omap_mpui_io_readfn[] = {
+static CPUReadMemoryFunc * const omap_mpui_io_readfn[] = {
omap_badwidth_read16,
omap_mpui_io_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mpui_io_writefn[] = {
omap_badwidth_write16,
omap_badwidth_write16,
omap_badwidth_write16,
diff --git a/hw/omap2.c b/hw/omap2.c
index e43b4a8..6a681d6 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -343,7 +343,7 @@ static uint32_t omap_gp_timer_readh(void *opaque,
target_phys_addr_t addr)
}
}
-static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
+static CPUReadMemoryFunc * const omap_gp_timer_readfn[] = {
omap_badwidth_read32,
omap_gp_timer_readh,
omap_gp_timer_readw,
@@ -460,7 +460,7 @@ static void omap_gp_timer_writeh(void *opaque,
target_phys_addr_t addr,
s->writeh = (uint16_t) value;
}
-static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
+static CPUWriteMemoryFunc * const omap_gp_timer_writefn[] = {
omap_badwidth_write32,
omap_gp_timer_writeh,
omap_gp_timer_write,
@@ -529,7 +529,7 @@ static uint32_t omap_synctimer_readh(void *opaque,
target_phys_addr_t addr)
}
}
-static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
+static CPUReadMemoryFunc * const omap_synctimer_readfn[] = {
omap_badwidth_read32,
omap_synctimer_readh,
omap_synctimer_readw,
@@ -541,7 +541,7 @@ static void omap_synctimer_write(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
+static CPUWriteMemoryFunc * const omap_synctimer_writefn[] = {
omap_badwidth_write32,
omap_synctimer_write,
omap_synctimer_write,
@@ -927,13 +927,13 @@ static void omap_gpio_module_writep(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
+static CPUReadMemoryFunc * const omap_gpio_module_readfn[] = {
omap_gpio_module_readp,
omap_gpio_module_readp,
omap_gpio_module_read,
};
-static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
+static CPUWriteMemoryFunc * const omap_gpio_module_writefn[] = {
omap_gpio_module_writep,
omap_gpio_module_writep,
omap_gpio_module_write,
@@ -1032,13 +1032,13 @@ static void omap_gpif_top_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
+static CPUReadMemoryFunc * const omap_gpif_top_readfn[] = {
omap_gpif_top_read,
omap_gpif_top_read,
omap_gpif_top_read,
};
-static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
+static CPUWriteMemoryFunc * const omap_gpif_top_writefn[] = {
omap_gpif_top_write,
omap_gpif_top_write,
omap_gpif_top_write,
@@ -1356,13 +1356,13 @@ static void omap_mcspi_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
+static CPUReadMemoryFunc * const omap_mcspi_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_mcspi_read,
};
-static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_mcspi_write,
@@ -1947,13 +1947,13 @@ static void omap_eac_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_eac_readfn[] = {
+static CPUReadMemoryFunc * const omap_eac_readfn[] = {
omap_badwidth_read16,
omap_eac_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_eac_writefn[] = {
+static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
omap_badwidth_write16,
omap_eac_write,
omap_badwidth_write16,
@@ -2096,13 +2096,13 @@ static void omap_sti_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_sti_readfn[] = {
+static CPUReadMemoryFunc * const omap_sti_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_sti_read,
};
-static CPUWriteMemoryFunc *omap_sti_writefn[] = {
+static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_sti_write,
@@ -2134,13 +2134,13 @@ static void omap_sti_fifo_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
+static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
omap_sti_fifo_read,
omap_badwidth_read8,
omap_badwidth_read8,
};
-static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
+static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
omap_sti_fifo_write,
omap_badwidth_write8,
omap_badwidth_write8,
@@ -2191,20 +2191,20 @@ struct omap_l4_s {
static int omap_l4_io_entries;
static int omap_cpu_io_entry;
static struct omap_l4_entry {
- CPUReadMemoryFunc **mem_read;
- CPUWriteMemoryFunc **mem_write;
+ CPUReadMemoryFunc * const *mem_read;
+ CPUWriteMemoryFunc * const *mem_write;
void *opaque;
} *omap_l4_io_entry;
-static CPUReadMemoryFunc **omap_l4_io_readb_fn;
-static CPUReadMemoryFunc **omap_l4_io_readh_fn;
-static CPUReadMemoryFunc **omap_l4_io_readw_fn;
-static CPUWriteMemoryFunc **omap_l4_io_writeb_fn;
-static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
-static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
+static CPUReadMemoryFunc * const *omap_l4_io_readb_fn;
+static CPUReadMemoryFunc * const *omap_l4_io_readh_fn;
+static CPUReadMemoryFunc * const *omap_l4_io_readw_fn;
+static CPUWriteMemoryFunc * const *omap_l4_io_writeb_fn;
+static CPUWriteMemoryFunc * const *omap_l4_io_writeh_fn;
+static CPUWriteMemoryFunc * const *omap_l4_io_writew_fn;
static void **omap_l4_io_opaque;
-int l4_register_io_memory(CPUReadMemoryFunc **mem_read,
- CPUWriteMemoryFunc **mem_write, void *opaque)
+int l4_register_io_memory(CPUReadMemoryFunc * const *mem_read,
+ CPUWriteMemoryFunc * const *mem_write, void *opaque)
{
omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
@@ -2258,13 +2258,13 @@ static void omap_l4_io_writew(void *opaque,
target_phys_addr_t addr,
return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
}
-static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
+static CPUReadMemoryFunc * const omap_l4_io_readfn[] = {
omap_l4_io_readb,
omap_l4_io_readh,
omap_l4_io_readw,
};
-static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
+static CPUWriteMemoryFunc * const omap_l4_io_writefn[] = {
omap_l4_io_writeb,
omap_l4_io_writeh,
omap_l4_io_writew,
@@ -2340,13 +2340,13 @@ static void omap_l4ta_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
+static CPUReadMemoryFunc * const omap_l4ta_readfn[] = {
omap_badwidth_read16,
omap_l4ta_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
+static CPUWriteMemoryFunc * const omap_l4ta_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_l4ta_write,
@@ -2692,13 +2692,13 @@ static void omap_tap_write(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc *omap_tap_readfn[] = {
+static CPUReadMemoryFunc * const omap_tap_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_tap_read,
};
-static CPUWriteMemoryFunc *omap_tap_writefn[] = {
+static CPUWriteMemoryFunc * const omap_tap_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_tap_write,
@@ -3414,13 +3414,13 @@ static void omap_prcm_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_prcm_readfn[] = {
+static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_prcm_read,
};
-static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
+static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_prcm_write,
@@ -3784,13 +3784,13 @@ static void omap_sysctl_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
+static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
omap_sysctl_read8,
omap_badwidth_read32, /* TODO */
omap_sysctl_read,
};
-static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
+static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
omap_sysctl_write8,
omap_badwidth_write32, /* TODO */
omap_sysctl_write,
@@ -4014,13 +4014,13 @@ static void omap_sdrc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
+static CPUReadMemoryFunc * const omap_sdrc_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_sdrc_read,
};
-static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
+static CPUWriteMemoryFunc * const omap_sdrc_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_sdrc_write,
@@ -4388,13 +4388,13 @@ static void omap_gpmc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
+static CPUReadMemoryFunc * const omap_gpmc_readfn[] = {
omap_badwidth_read32, /* TODO */
omap_badwidth_read32, /* TODO */
omap_gpmc_read,
};
-static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
+static CPUWriteMemoryFunc * const omap_gpmc_writefn[] = {
omap_badwidth_write32, /* TODO */
omap_badwidth_write32, /* TODO */
omap_gpmc_write,
diff --git a/hw/omap_dma.c b/hw/omap_dma.c
index 3122f42..6f5eaca 100644
--- a/hw/omap_dma.c
+++ b/hw/omap_dma.c
@@ -1526,13 +1526,13 @@ static void omap_dma_write(void *opaque,
target_phys_addr_t addr,
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc *omap_dma_readfn[] = {
+static CPUReadMemoryFunc * const omap_dma_readfn[] = {
omap_badwidth_read16,
omap_dma_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_dma_writefn[] = {
+static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
omap_badwidth_write16,
omap_dma_write,
omap_badwidth_write16,
@@ -2017,13 +2017,13 @@ static void omap_dma4_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_dma4_readfn[] = {
+static CPUReadMemoryFunc * const omap_dma4_readfn[] = {
omap_badwidth_read16,
omap_dma4_read,
omap_dma4_read,
};
-static CPUWriteMemoryFunc *omap_dma4_writefn[] = {
+static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
omap_badwidth_write16,
omap_dma4_write,
omap_dma4_write,
diff --git a/hw/omap_dss.c b/hw/omap_dss.c
index b6aad4f..044f2d2 100644
--- a/hw/omap_dss.c
+++ b/hw/omap_dss.c
@@ -230,13 +230,13 @@ static void omap_diss_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_diss1_readfn[] = {
+static CPUReadMemoryFunc * const omap_diss1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_diss_read,
};
-static CPUWriteMemoryFunc *omap_diss1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_diss1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_diss_write,
@@ -569,13 +569,13 @@ static void omap_disc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_disc1_readfn[] = {
+static CPUReadMemoryFunc * const omap_disc1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_disc_read,
};
-static CPUWriteMemoryFunc *omap_disc1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_disc1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_disc_write,
@@ -841,13 +841,13 @@ static void omap_rfbi_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_rfbi1_readfn[] = {
+static CPUReadMemoryFunc * const omap_rfbi1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_rfbi_read,
};
-static CPUWriteMemoryFunc *omap_rfbi1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_rfbi1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_rfbi_write,
@@ -960,13 +960,13 @@ static void omap_venc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_venc1_readfn[] = {
+static CPUReadMemoryFunc * const omap_venc1_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_venc_read,
};
-static CPUWriteMemoryFunc *omap_venc1_writefn[] = {
+static CPUWriteMemoryFunc * const omap_venc1_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_venc_write,
@@ -1010,13 +1010,13 @@ static void omap_im3_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_im3_readfn[] = {
+static CPUReadMemoryFunc * const omap_im3_readfn[] = {
omap_badwidth_read32,
omap_badwidth_read32,
omap_im3_read,
};
-static CPUWriteMemoryFunc *omap_im3_writefn[] = {
+static CPUWriteMemoryFunc * const omap_im3_writefn[] = {
omap_badwidth_write32,
omap_badwidth_write32,
omap_im3_write,
diff --git a/hw/omap_i2c.c b/hw/omap_i2c.c
index 9e59005..d7c1888 100644
--- a/hw/omap_i2c.c
+++ b/hw/omap_i2c.c
@@ -408,13 +408,13 @@ static void omap_i2c_writeb(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_i2c_readfn[] = {
+static CPUReadMemoryFunc * const omap_i2c_readfn[] = {
omap_badwidth_read16,
omap_i2c_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
+static CPUWriteMemoryFunc * const omap_i2c_writefn[] = {
omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
omap_i2c_write,
omap_badwidth_write16,
diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c
index 2dfffad..c065193 100644
--- a/hw/omap_lcdc.c
+++ b/hw/omap_lcdc.c
@@ -401,13 +401,13 @@ static void omap_lcdc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *omap_lcdc_readfn[] = {
+static CPUReadMemoryFunc * const omap_lcdc_readfn[] = {
omap_lcdc_read,
omap_lcdc_read,
omap_lcdc_read,
};
-static CPUWriteMemoryFunc *omap_lcdc_writefn[] = {
+static CPUWriteMemoryFunc * const omap_lcdc_writefn[] = {
omap_lcdc_write,
omap_lcdc_write,
omap_lcdc_write,
diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c
index 9aadfc9..bbe3f28 100644
--- a/hw/omap_mmc.c
+++ b/hw/omap_mmc.c
@@ -540,13 +540,13 @@ static void omap_mmc_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *omap_mmc_readfn[] = {
+static CPUReadMemoryFunc * const omap_mmc_readfn[] = {
omap_badwidth_read16,
omap_mmc_read,
omap_badwidth_read16,
};
-static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
+static CPUWriteMemoryFunc * const omap_mmc_writefn[] = {
omap_badwidth_write16,
omap_mmc_write,
omap_badwidth_write16,
diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c
index 22f801b..255dcbd 100644
--- a/hw/omap_sx1.c
+++ b/hw/omap_sx1.c
@@ -88,13 +88,13 @@ static void static_write(void *opaque, target_phys_addr_t
offset,
#endif
}
-static CPUReadMemoryFunc *static_readfn[] = {
+static CPUReadMemoryFunc * const static_readfn[] = {
static_readb,
static_readh,
static_readw,
};
-static CPUWriteMemoryFunc *static_writefn[] = {
+static CPUWriteMemoryFunc * const static_writefn[] = {
static_write,
static_write,
static_write,
diff --git a/hw/onenand.c b/hw/onenand.c
index 84fdb21..59bc8ac 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -603,13 +603,13 @@ static void onenand_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *onenand_readfn[] = {
+static CPUReadMemoryFunc * const onenand_readfn[] = {
onenand_read, /* TODO */
onenand_read,
onenand_read,
};
-static CPUWriteMemoryFunc *onenand_writefn[] = {
+static CPUWriteMemoryFunc * const onenand_writefn[] = {
onenand_write, /* TODO */
onenand_write,
onenand_write,
diff --git a/hw/openpic.c b/hw/openpic.c
index f50031d..74dde6d 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -1013,13 +1013,13 @@ static uint32_t openpic_readl (void
*opaque,target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc *openpic_write[] = {
+static CPUWriteMemoryFunc * const openpic_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&openpic_writel,
};
-static CPUReadMemoryFunc *openpic_read[] = {
+static CPUReadMemoryFunc * const openpic_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_readl,
@@ -1574,84 +1574,84 @@ static uint32_t mpic_src_msi_read (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc *mpic_glb_write[] = {
+static CPUWriteMemoryFunc * const mpic_glb_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&openpic_gbl_write,
};
-static CPUReadMemoryFunc *mpic_glb_read[] = {
+static CPUReadMemoryFunc * const mpic_glb_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_gbl_read,
};
-static CPUWriteMemoryFunc *mpic_tmr_write[] = {
+static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_timer_write,
};
-static CPUReadMemoryFunc *mpic_tmr_read[] = {
+static CPUReadMemoryFunc * const mpic_tmr_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_timer_read,
};
-static CPUWriteMemoryFunc *mpic_cpu_write[] = {
+static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&openpic_cpu_write,
};
-static CPUReadMemoryFunc *mpic_cpu_read[] = {
+static CPUReadMemoryFunc * const mpic_cpu_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_cpu_read,
};
-static CPUWriteMemoryFunc *mpic_ext_write[] = {
+static CPUWriteMemoryFunc * const mpic_ext_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_ext_write,
};
-static CPUReadMemoryFunc *mpic_ext_read[] = {
+static CPUReadMemoryFunc * const mpic_ext_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_ext_read,
};
-static CPUWriteMemoryFunc *mpic_int_write[] = {
+static CPUWriteMemoryFunc * const mpic_int_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_int_write,
};
-static CPUReadMemoryFunc *mpic_int_read[] = {
+static CPUReadMemoryFunc * const mpic_int_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_int_read,
};
-static CPUWriteMemoryFunc *mpic_msg_write[] = {
+static CPUWriteMemoryFunc * const mpic_msg_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_msg_write,
};
-static CPUReadMemoryFunc *mpic_msg_read[] = {
+static CPUReadMemoryFunc * const mpic_msg_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_msg_read,
};
-static CPUWriteMemoryFunc *mpic_msi_write[] = {
+static CPUWriteMemoryFunc * const mpic_msi_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_msi_write,
};
-static CPUReadMemoryFunc *mpic_msi_read[] = {
+static CPUReadMemoryFunc * const mpic_msi_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_msi_read,
@@ -1663,8 +1663,8 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
openpic_t *mpp;
int i;
struct {
- CPUReadMemoryFunc **read;
- CPUWriteMemoryFunc **write;
+ CPUReadMemoryFunc * const *read;
+ CPUWriteMemoryFunc * const *write;
target_phys_addr_t start_addr;
ram_addr_t size;
} const list[] = {
diff --git a/hw/palm.c b/hw/palm.c
index 7c812a3..bba9722 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -52,13 +52,13 @@ static void static_write(void *opaque, target_phys_addr_t
offset,
#endif
}
-static CPUReadMemoryFunc *static_readfn[] = {
+static CPUReadMemoryFunc * const static_readfn[] = {
static_readb,
static_readh,
static_readw,
};
-static CPUWriteMemoryFunc *static_writefn[] = {
+static CPUWriteMemoryFunc * const static_writefn[] = {
static_write,
static_write,
static_write,
diff --git a/hw/parallel.c b/hw/parallel.c
index 66f18bb..faaaa0d 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -518,13 +518,13 @@ static void parallel_mm_writel (void *opaque,
parallel_ioport_write_sw(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc *parallel_mm_read_sw[] = {
+static CPUReadMemoryFunc * const parallel_mm_read_sw[] = {
¶llel_mm_readb,
¶llel_mm_readw,
¶llel_mm_readl,
};
-static CPUWriteMemoryFunc *parallel_mm_write_sw[] = {
+static CPUWriteMemoryFunc * const parallel_mm_write_sw[] = {
¶llel_mm_writeb,
¶llel_mm_writew,
¶llel_mm_writel,
diff --git a/hw/pckbd.c b/hw/pckbd.c
index bb4cc0e..6d97e33 100644
--- a/hw/pckbd.c
+++ b/hw/pckbd.c
@@ -405,13 +405,13 @@ static void kbd_mm_writeb (void *opaque,
target_phys_addr_t addr, uint32_t value
kbd_write_data(s, 0, value & 0xff);
}
-static CPUReadMemoryFunc *kbd_mm_read[] = {
+static CPUReadMemoryFunc * const kbd_mm_read[] = {
&kbd_mm_readb,
&kbd_mm_readb,
&kbd_mm_readb,
};
-static CPUWriteMemoryFunc *kbd_mm_write[] = {
+static CPUWriteMemoryFunc * const kbd_mm_write[] = {
&kbd_mm_writeb,
&kbd_mm_writeb,
&kbd_mm_writeb,
diff --git a/hw/pcnet.c b/hw/pcnet.c
index 637dcfb..827f6bd 100644
--- a/hw/pcnet.c
+++ b/hw/pcnet.c
@@ -1963,16 +1963,16 @@ static void pcnet_common_init(DeviceState *dev,
PCNetState *s,
/* PCI interface */
-static CPUWriteMemoryFunc *pcnet_mmio_write[] = {
- (CPUWriteMemoryFunc *)&pcnet_mmio_writeb,
- (CPUWriteMemoryFunc *)&pcnet_mmio_writew,
- (CPUWriteMemoryFunc *)&pcnet_mmio_writel
+static CPUWriteMemoryFunc * const pcnet_mmio_write[] = {
+ (CPUWriteMemoryFunc * const )&pcnet_mmio_writeb,
+ (CPUWriteMemoryFunc * const )&pcnet_mmio_writew,
+ (CPUWriteMemoryFunc * const )&pcnet_mmio_writel
};
-static CPUReadMemoryFunc *pcnet_mmio_read[] = {
- (CPUReadMemoryFunc *)&pcnet_mmio_readb,
- (CPUReadMemoryFunc *)&pcnet_mmio_readw,
- (CPUReadMemoryFunc *)&pcnet_mmio_readl
+static CPUReadMemoryFunc * const pcnet_mmio_read[] = {
+ (CPUReadMemoryFunc * const )&pcnet_mmio_readb,
+ (CPUReadMemoryFunc * const )&pcnet_mmio_readw,
+ (CPUReadMemoryFunc * const )&pcnet_mmio_readl
};
static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
@@ -2101,13 +2101,13 @@ static uint32_t lance_mem_readw(void *opaque,
target_phys_addr_t addr)
return val & 0xffff;
}
-static CPUReadMemoryFunc *lance_mem_read[3] = {
+static CPUReadMemoryFunc * const lance_mem_read[3] = {
NULL,
lance_mem_readw,
NULL,
};
-static CPUWriteMemoryFunc *lance_mem_write[3] = {
+static CPUWriteMemoryFunc * const lance_mem_write[3] = {
NULL,
lance_mem_writew,
NULL,
diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c
index bfa2bdd..6dd39a6 100644
--- a/hw/pflash_cfi01.c
+++ b/hw/pflash_cfi01.c
@@ -453,13 +453,13 @@ static void pflash_writel (void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4);
}
-static CPUWriteMemoryFunc *pflash_write_ops[] = {
+static CPUWriteMemoryFunc * const pflash_write_ops[] = {
&pflash_writeb,
&pflash_writew,
&pflash_writel,
};
-static CPUReadMemoryFunc *pflash_read_ops[] = {
+static CPUReadMemoryFunc * const pflash_read_ops[] = {
&pflash_readb,
&pflash_readw,
&pflash_readl,
diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c
index a62d609..a97b9e6 100644
--- a/hw/pflash_cfi02.c
+++ b/hw/pflash_cfi02.c
@@ -492,13 +492,13 @@ static void pflash_writel (void *opaque,
target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4);
}
-static CPUWriteMemoryFunc *pflash_write_ops[] = {
+static CPUWriteMemoryFunc * const pflash_write_ops[] = {
&pflash_writeb,
&pflash_writew,
&pflash_writel,
};
-static CPUReadMemoryFunc *pflash_read_ops[] = {
+static CPUReadMemoryFunc * const pflash_read_ops[] = {
&pflash_readb,
&pflash_readw,
&pflash_readl,
diff --git a/hw/pl011.c b/hw/pl011.c
index 0528bfe..08a55ac 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -223,13 +223,13 @@ static void pl011_event(void *opaque, int event)
pl011_put_fifo(opaque, 0x400);
}
-static CPUReadMemoryFunc *pl011_readfn[] = {
+static CPUReadMemoryFunc * const pl011_readfn[] = {
pl011_read,
pl011_read,
pl011_read
};
-static CPUWriteMemoryFunc *pl011_writefn[] = {
+static CPUWriteMemoryFunc * const pl011_writefn[] = {
pl011_write,
pl011_write,
pl011_write
diff --git a/hw/pl022.c b/hw/pl022.c
index 78076e0..62e22d0 100644
--- a/hw/pl022.c
+++ b/hw/pl022.c
@@ -227,13 +227,13 @@ static void pl022_reset(pl022_state *s)
s->sr = PL022_SR_TFE | PL022_SR_TNF;
}
-static CPUReadMemoryFunc *pl022_readfn[] = {
+static CPUReadMemoryFunc * const pl022_readfn[] = {
pl022_read,
pl022_read,
pl022_read
};
-static CPUWriteMemoryFunc *pl022_writefn[] = {
+static CPUWriteMemoryFunc * const pl022_writefn[] = {
pl022_write,
pl022_write,
pl022_write
diff --git a/hw/pl031.c b/hw/pl031.c
index 5c9992e..671491f 100644
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -171,13 +171,13 @@ static void pl031_write(void * opaque, target_phys_addr_t
offset,
}
}
-static CPUWriteMemoryFunc * pl031_writefn[] = {
+static CPUWriteMemoryFunc * const pl031_writefn[] = {
pl031_write,
pl031_write,
pl031_write
};
-static CPUReadMemoryFunc * pl031_readfn[] = {
+static CPUReadMemoryFunc * const pl031_readfn[] = {
pl031_read,
pl031_read,
pl031_read
diff --git a/hw/pl050.c b/hw/pl050.c
index c8818e0..011edf2 100644
--- a/hw/pl050.c
+++ b/hw/pl050.c
@@ -110,13 +110,13 @@ static void pl050_write(void *opaque, target_phys_addr_t
offset,
hw_error("pl050_write: Bad offset %x\n", (int)offset);
}
}
-static CPUReadMemoryFunc *pl050_readfn[] = {
+static CPUReadMemoryFunc * const pl050_readfn[] = {
pl050_read,
pl050_read,
pl050_read
};
-static CPUWriteMemoryFunc *pl050_writefn[] = {
+static CPUWriteMemoryFunc * const pl050_writefn[] = {
pl050_write,
pl050_write,
pl050_write
diff --git a/hw/pl061.c b/hw/pl061.c
index a003b97..2f31517 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -223,13 +223,13 @@ static void pl061_set_irq(void * opaque, int irq, int
level)
}
}
-static CPUReadMemoryFunc *pl061_readfn[] = {
+static CPUReadMemoryFunc * const pl061_readfn[] = {
pl061_read,
pl061_read,
pl061_read
};
-static CPUWriteMemoryFunc *pl061_writefn[] = {
+static CPUWriteMemoryFunc * const pl061_writefn[] = {
pl061_write,
pl061_write,
pl061_write
diff --git a/hw/pl080.c b/hw/pl080.c
index 9c17be6..a6ea8eb 100644
--- a/hw/pl080.c
+++ b/hw/pl080.c
@@ -307,13 +307,13 @@ static void pl080_write(void *opaque, target_phys_addr_t
offset,
pl080_update(s);
}
-static CPUReadMemoryFunc *pl080_readfn[] = {
+static CPUReadMemoryFunc * const pl080_readfn[] = {
pl080_read,
pl080_read,
pl080_read
};
-static CPUWriteMemoryFunc *pl080_writefn[] = {
+static CPUWriteMemoryFunc * const pl080_writefn[] = {
pl080_write,
pl080_write,
pl080_write
diff --git a/hw/pl110.c b/hw/pl110.c
index 2797f83..9b5724b 100644
--- a/hw/pl110.c
+++ b/hw/pl110.c
@@ -340,13 +340,13 @@ static void pl110_write(void *opaque, target_phys_addr_t
offset,
}
}
-static CPUReadMemoryFunc *pl110_readfn[] = {
+static CPUReadMemoryFunc * const pl110_readfn[] = {
pl110_read,
pl110_read,
pl110_read
};
-static CPUWriteMemoryFunc *pl110_writefn[] = {
+static CPUWriteMemoryFunc * const pl110_writefn[] = {
pl110_write,
pl110_write,
pl110_write
diff --git a/hw/pl181.c b/hw/pl181.c
index 3075c9e..955e5ec 100644
--- a/hw/pl181.c
+++ b/hw/pl181.c
@@ -409,13 +409,13 @@ static void pl181_write(void *opaque, target_phys_addr_t
offset,
pl181_update(s);
}
-static CPUReadMemoryFunc *pl181_readfn[] = {
+static CPUReadMemoryFunc * const pl181_readfn[] = {
pl181_read,
pl181_read,
pl181_read
};
-static CPUWriteMemoryFunc *pl181_writefn[] = {
+static CPUWriteMemoryFunc * const pl181_writefn[] = {
pl181_write,
pl181_write,
pl181_write
diff --git a/hw/pl190.c b/hw/pl190.c
index f68fb42..da5b4b3 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -200,13 +200,13 @@ static void pl190_write(void *opaque, target_phys_addr_t
offset, uint32_t val)
pl190_update(s);
}
-static CPUReadMemoryFunc *pl190_readfn[] = {
+static CPUReadMemoryFunc * const pl190_readfn[] = {
pl190_read,
pl190_read,
pl190_read
};
-static CPUWriteMemoryFunc *pl190_writefn[] = {
+static CPUWriteMemoryFunc * const pl190_writefn[] = {
pl190_write,
pl190_write,
pl190_write
diff --git a/hw/ppc.h b/hw/ppc.h
index efb09e8..4b481af 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -26,8 +26,8 @@ void ppc40x_chip_reset (CPUState *env);
void ppc40x_system_reset (CPUState *env);
void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
-extern CPUWriteMemoryFunc *PPC_io_write[];
-extern CPUReadMemoryFunc *PPC_io_read[];
+extern CPUWriteMemoryFunc * const PPC_io_write[];
+extern CPUReadMemoryFunc * const PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
void ppc40x_irq_init (CPUState *env);
diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index 0377d1c..0d7860e 100644
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -134,13 +134,13 @@ static void ref405ep_fpga_writel (void *opaque,
ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
}
-static CPUReadMemoryFunc *ref405ep_fpga_read[] = {
+static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
&ref405ep_fpga_readb,
&ref405ep_fpga_readw,
&ref405ep_fpga_readl,
};
-static CPUWriteMemoryFunc *ref405ep_fpga_write[] = {
+static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
&ref405ep_fpga_writeb,
&ref405ep_fpga_writew,
&ref405ep_fpga_writel,
@@ -458,13 +458,13 @@ static void taihu_cpld_writel (void *opaque,
taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
}
-static CPUReadMemoryFunc *taihu_cpld_read[] = {
+static CPUReadMemoryFunc * const taihu_cpld_read[] = {
&taihu_cpld_readb,
&taihu_cpld_readw,
&taihu_cpld_readl,
};
-static CPUWriteMemoryFunc *taihu_cpld_write[] = {
+static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
&taihu_cpld_writeb,
&taihu_cpld_writew,
&taihu_cpld_writel,
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index aa2f0db..65d70d3 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -355,13 +355,13 @@ static void opba_writel (void *opaque,
opba_writeb(opaque, addr + 1, value >> 16);
}
-static CPUReadMemoryFunc *opba_read[] = {
+static CPUReadMemoryFunc * const opba_read[] = {
&opba_readb,
&opba_readw,
&opba_readl,
};
-static CPUWriteMemoryFunc *opba_write[] = {
+static CPUWriteMemoryFunc * const opba_write[] = {
&opba_writeb,
&opba_writew,
&opba_writel,
@@ -813,13 +813,13 @@ static void ppc405_gpio_writel (void *opaque,
#endif
}
-static CPUReadMemoryFunc *ppc405_gpio_read[] = {
+static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
&ppc405_gpio_readb,
&ppc405_gpio_readw,
&ppc405_gpio_readl,
};
-static CPUWriteMemoryFunc *ppc405_gpio_write[] = {
+static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
&ppc405_gpio_writeb,
&ppc405_gpio_writew,
&ppc405_gpio_writel,
@@ -1214,13 +1214,13 @@ static void ppc4xx_i2c_writel (void *opaque,
ppc4xx_i2c_writeb(opaque, addr + 3, value);
}
-static CPUReadMemoryFunc *i2c_read[] = {
+static CPUReadMemoryFunc * const i2c_read[] = {
&ppc4xx_i2c_readb,
&ppc4xx_i2c_readw,
&ppc4xx_i2c_readl,
};
-static CPUWriteMemoryFunc *i2c_write[] = {
+static CPUWriteMemoryFunc * const i2c_write[] = {
&ppc4xx_i2c_writeb,
&ppc4xx_i2c_writew,
&ppc4xx_i2c_writel,
@@ -1482,13 +1482,13 @@ static void ppc4xx_gpt_writel (void *opaque,
}
}
-static CPUReadMemoryFunc *gpt_read[] = {
+static CPUReadMemoryFunc * const gpt_read[] = {
&ppc4xx_gpt_readb,
&ppc4xx_gpt_readw,
&ppc4xx_gpt_readl,
};
-static CPUWriteMemoryFunc *gpt_write[] = {
+static CPUWriteMemoryFunc * const gpt_write[] = {
&ppc4xx_gpt_writeb,
&ppc4xx_gpt_writew,
&ppc4xx_gpt_writel,
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index 077ae70..98877cf 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -93,7 +93,7 @@ static uint32_t pci4xx_cfgaddr_readl(void *opaque,
target_phys_addr_t addr)
return ppc4xx_pci->pci_state.config_reg;
}
-static CPUReadMemoryFunc *pci4xx_cfgaddr_read[] = {
+static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
&pci4xx_cfgaddr_readl,
&pci4xx_cfgaddr_readl,
&pci4xx_cfgaddr_readl,
@@ -111,19 +111,19 @@ static void pci4xx_cfgaddr_writel(void *opaque,
target_phys_addr_t addr,
ppc4xx_pci->pci_state.config_reg = value & ~0x3;
}
-static CPUWriteMemoryFunc *pci4xx_cfgaddr_write[] = {
+static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
&pci4xx_cfgaddr_writel,
&pci4xx_cfgaddr_writel,
&pci4xx_cfgaddr_writel,
};
-static CPUReadMemoryFunc *pci4xx_cfgdata_read[] = {
+static CPUReadMemoryFunc * const pci4xx_cfgdata_read[] = {
&pci_host_data_readb,
&pci_host_data_readw,
&pci_host_data_readl,
};
-static CPUWriteMemoryFunc *pci4xx_cfgdata_write[] = {
+static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = {
&pci_host_data_writeb,
&pci_host_data_writew,
&pci_host_data_writel,
@@ -272,13 +272,13 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque,
target_phys_addr_t offset)
return value;
}
-static CPUReadMemoryFunc *pci_reg_read[] = {
+static CPUReadMemoryFunc * const pci_reg_read[] = {
&ppc4xx_pci_reg_read4,
&ppc4xx_pci_reg_read4,
&ppc4xx_pci_reg_read4,
};
-static CPUWriteMemoryFunc *pci_reg_write[] = {
+static CPUWriteMemoryFunc * const pci_reg_write[] = {
&ppc4xx_pci_reg_write4,
&ppc4xx_pci_reg_write4,
&ppc4xx_pci_reg_write4,
diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c
index 784e527..35a9858 100644
--- a/hw/ppc_newworld.c
+++ b/hw/ppc_newworld.c
@@ -66,13 +66,13 @@ static uint32_t unin_readl (void *opaque,
target_phys_addr_t addr)
return value;
}
-static CPUWriteMemoryFunc *unin_write[] = {
+static CPUWriteMemoryFunc * const unin_write[] = {
&unin_writel,
&unin_writel,
&unin_writel,
};
-static CPUReadMemoryFunc *unin_read[] = {
+static CPUReadMemoryFunc * const unin_read[] = {
&unin_readl,
&unin_readl,
&unin_readl,
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index adfa44d..223ca61 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -155,13 +155,13 @@ static uint32_t PPC_intack_readl (void *opaque,
target_phys_addr_t addr)
#endif
}
-static CPUWriteMemoryFunc *PPC_intack_write[] = {
+static CPUWriteMemoryFunc * const PPC_intack_write[] = {
&_PPC_intack_write,
&_PPC_intack_write,
&_PPC_intack_write,
};
-static CPUReadMemoryFunc *PPC_intack_read[] = {
+static CPUReadMemoryFunc * const PPC_intack_read[] = {
&PPC_intack_readb,
&PPC_intack_readw,
&PPC_intack_readl,
@@ -257,13 +257,13 @@ static uint32_t PPC_XCSR_readl (void *opaque,
target_phys_addr_t addr)
return retval;
}
-static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
+static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
&PPC_XCSR_writeb,
&PPC_XCSR_writew,
&PPC_XCSR_writel,
};
-static CPUReadMemoryFunc *PPC_XCSR_read[] = {
+static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
&PPC_XCSR_readb,
&PPC_XCSR_readw,
&PPC_XCSR_readl,
@@ -528,13 +528,13 @@ static uint32_t PPC_prep_io_readl (void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUWriteMemoryFunc *PPC_prep_io_write[] = {
+static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
&PPC_prep_io_writeb,
&PPC_prep_io_writew,
&PPC_prep_io_writel,
};
-static CPUReadMemoryFunc *PPC_prep_io_read[] = {
+static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
&PPC_prep_io_readb,
&PPC_prep_io_readw,
&PPC_prep_io_readl,
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 5b4673a..6328f73 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -94,7 +94,7 @@ static uint32_t pcie500_cfgaddr_readl(void *opaque,
target_phys_addr_t addr)
return pci->pci_state.config_reg;
}
-static CPUReadMemoryFunc *pcie500_cfgaddr_read[] = {
+static CPUReadMemoryFunc * const pcie500_cfgaddr_read[] = {
&pcie500_cfgaddr_readl,
&pcie500_cfgaddr_readl,
&pcie500_cfgaddr_readl,
@@ -110,19 +110,19 @@ static void pcie500_cfgaddr_writel(void *opaque,
target_phys_addr_t addr,
controller->pci_state.config_reg = value & ~0x3;
}
-static CPUWriteMemoryFunc *pcie500_cfgaddr_write[] = {
+static CPUWriteMemoryFunc * const pcie500_cfgaddr_write[] = {
&pcie500_cfgaddr_writel,
&pcie500_cfgaddr_writel,
&pcie500_cfgaddr_writel,
};
-static CPUReadMemoryFunc *pcie500_cfgdata_read[] = {
+static CPUReadMemoryFunc * const pcie500_cfgdata_read[] = {
&pci_host_data_readb,
&pci_host_data_readw,
&pci_host_data_readl,
};
-static CPUWriteMemoryFunc *pcie500_cfgdata_write[] = {
+static CPUWriteMemoryFunc * const pcie500_cfgdata_write[] = {
&pci_host_data_writeb,
&pci_host_data_writew,
&pci_host_data_writel,
@@ -175,7 +175,7 @@ static uint32_t pci_reg_read4(void *opaque,
target_phys_addr_t addr)
return value;
}
-static CPUReadMemoryFunc *e500_pci_reg_read[] = {
+static CPUReadMemoryFunc * const e500_pci_reg_read[] = {
&pci_reg_read4,
&pci_reg_read4,
&pci_reg_read4,
@@ -227,7 +227,7 @@ static void pci_reg_write4(void *opaque, target_phys_addr_t
addr,
};
}
-static CPUWriteMemoryFunc *e500_pci_reg_write[] = {
+static CPUWriteMemoryFunc * const e500_pci_reg_write[] = {
&pci_reg_write4,
&pci_reg_write4,
&pci_reg_write4,
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index 80058b1..2a1d0f9 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -107,13 +107,13 @@ static uint32_t PPC_PCIIO_readl (void *opaque,
target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
+static CPUWriteMemoryFunc * const PPC_PCIIO_write[] = {
&PPC_PCIIO_writeb,
&PPC_PCIIO_writew,
&PPC_PCIIO_writel,
};
-static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
+static CPUReadMemoryFunc * const PPC_PCIIO_read[] = {
&PPC_PCIIO_readb,
&PPC_PCIIO_readw,
&PPC_PCIIO_readl,
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 28e9610..5546ee2 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -134,13 +134,13 @@ static void pxa2xx_pm_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_pm_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = {
pxa2xx_pm_read,
pxa2xx_pm_read,
pxa2xx_pm_read,
};
-static CPUWriteMemoryFunc *pxa2xx_pm_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = {
pxa2xx_pm_write,
pxa2xx_pm_write,
pxa2xx_pm_write,
@@ -215,13 +215,13 @@ static void pxa2xx_cm_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_cm_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = {
pxa2xx_cm_read,
pxa2xx_cm_read,
pxa2xx_cm_read,
};
-static CPUWriteMemoryFunc *pxa2xx_cm_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = {
pxa2xx_cm_write,
pxa2xx_cm_write,
pxa2xx_cm_write,
@@ -515,13 +515,13 @@ static void pxa2xx_mm_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_mm_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = {
pxa2xx_mm_read,
pxa2xx_mm_read,
pxa2xx_mm_read,
};
-static CPUWriteMemoryFunc *pxa2xx_mm_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = {
pxa2xx_mm_write,
pxa2xx_mm_write,
pxa2xx_mm_write,
@@ -791,13 +791,13 @@ static void pxa2xx_ssp_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_ssp_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = {
pxa2xx_ssp_read,
pxa2xx_ssp_read,
pxa2xx_ssp_read,
};
-static CPUWriteMemoryFunc *pxa2xx_ssp_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = {
pxa2xx_ssp_write,
pxa2xx_ssp_write,
pxa2xx_ssp_write,
@@ -1155,13 +1155,13 @@ static void pxa2xx_rtc_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_rtc_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = {
pxa2xx_rtc_read,
pxa2xx_rtc_read,
pxa2xx_rtc_read,
};
-static CPUWriteMemoryFunc *pxa2xx_rtc_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = {
pxa2xx_rtc_write,
pxa2xx_rtc_write,
pxa2xx_rtc_write,
@@ -1439,13 +1439,13 @@ static void pxa2xx_i2c_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_i2c_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = {
pxa2xx_i2c_read,
pxa2xx_i2c_read,
pxa2xx_i2c_read,
};
-static CPUWriteMemoryFunc *pxa2xx_i2c_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = {
pxa2xx_i2c_write,
pxa2xx_i2c_write,
pxa2xx_i2c_write,
@@ -1666,13 +1666,13 @@ static void pxa2xx_i2s_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_i2s_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = {
pxa2xx_i2s_read,
pxa2xx_i2s_read,
pxa2xx_i2s_read,
};
-static CPUWriteMemoryFunc *pxa2xx_i2s_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = {
pxa2xx_i2s_write,
pxa2xx_i2s_write,
pxa2xx_i2s_write,
@@ -1909,13 +1909,13 @@ static void pxa2xx_fir_write(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *pxa2xx_fir_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = {
pxa2xx_fir_read,
pxa2xx_fir_read,
pxa2xx_fir_read,
};
-static CPUWriteMemoryFunc *pxa2xx_fir_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = {
pxa2xx_fir_write,
pxa2xx_fir_write,
pxa2xx_fir_write,
diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c
index f0351c4..66c2c30 100644
--- a/hw/pxa2xx_dma.c
+++ b/hw/pxa2xx_dma.c
@@ -416,13 +416,13 @@ static void pxa2xx_dma_writebad(void *opaque,
hw_error("%s: Bad access width\n", __FUNCTION__);
}
-static CPUReadMemoryFunc *pxa2xx_dma_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_dma_readfn[] = {
pxa2xx_dma_readbad,
pxa2xx_dma_readbad,
pxa2xx_dma_read
};
-static CPUWriteMemoryFunc *pxa2xx_dma_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_dma_writefn[] = {
pxa2xx_dma_writebad,
pxa2xx_dma_writebad,
pxa2xx_dma_write
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index 27f72ec..f354f4b 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -237,13 +237,13 @@ static void pxa2xx_gpio_write(void *opaque,
}
}
-static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = {
pxa2xx_gpio_read,
pxa2xx_gpio_read,
pxa2xx_gpio_read
};
-static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
pxa2xx_gpio_write,
pxa2xx_gpio_write,
pxa2xx_gpio_write
diff --git a/hw/pxa2xx_keypad.c b/hw/pxa2xx_keypad.c
index 80dcb58..060df58 100644
--- a/hw/pxa2xx_keypad.c
+++ b/hw/pxa2xx_keypad.c
@@ -257,13 +257,13 @@ static void pxa2xx_keypad_write(void *opaque,
}
}
-static CPUReadMemoryFunc *pxa2xx_keypad_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_keypad_readfn[] = {
pxa2xx_keypad_read,
pxa2xx_keypad_read,
pxa2xx_keypad_read
};
-static CPUWriteMemoryFunc *pxa2xx_keypad_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_keypad_writefn[] = {
pxa2xx_keypad_write,
pxa2xx_keypad_write,
pxa2xx_keypad_write
diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c
index c9fefc3..0bf03de 100644
--- a/hw/pxa2xx_lcd.c
+++ b/hw/pxa2xx_lcd.c
@@ -559,13 +559,13 @@ static void pxa2xx_lcdc_write(void *opaque,
}
}
-static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_lcdc_readfn[] = {
pxa2xx_lcdc_read,
pxa2xx_lcdc_read,
pxa2xx_lcdc_read
};
-static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_lcdc_writefn[] = {
pxa2xx_lcdc_write,
pxa2xx_lcdc_write,
pxa2xx_lcdc_write
diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c
index 4c306cf..a415349 100644
--- a/hw/pxa2xx_mmci.c
+++ b/hw/pxa2xx_mmci.c
@@ -403,7 +403,7 @@ static uint32_t pxa2xx_mmci_readw(void *opaque,
target_phys_addr_t offset)
return pxa2xx_mmci_read(opaque, offset);
}
-static CPUReadMemoryFunc *pxa2xx_mmci_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_mmci_readfn[] = {
pxa2xx_mmci_readb,
pxa2xx_mmci_readh,
pxa2xx_mmci_readw
@@ -433,7 +433,7 @@ static void pxa2xx_mmci_writew(void *opaque,
pxa2xx_mmci_write(opaque, offset, value);
}
-static CPUWriteMemoryFunc *pxa2xx_mmci_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_mmci_writefn[] = {
pxa2xx_mmci_writeb,
pxa2xx_mmci_writeh,
pxa2xx_mmci_writew
diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index cb13a26..5b42147 100644
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -85,37 +85,37 @@ static void pxa2xx_pcmcia_io_write(void *opaque,
}
}
-static CPUReadMemoryFunc *pxa2xx_pcmcia_common_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_pcmcia_common_readfn[] = {
pxa2xx_pcmcia_common_read,
pxa2xx_pcmcia_common_read,
pxa2xx_pcmcia_common_read,
};
-static CPUWriteMemoryFunc *pxa2xx_pcmcia_common_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_pcmcia_common_writefn[] = {
pxa2xx_pcmcia_common_write,
pxa2xx_pcmcia_common_write,
pxa2xx_pcmcia_common_write,
};
-static CPUReadMemoryFunc *pxa2xx_pcmcia_attr_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_pcmcia_attr_readfn[] = {
pxa2xx_pcmcia_attr_read,
pxa2xx_pcmcia_attr_read,
pxa2xx_pcmcia_attr_read,
};
-static CPUWriteMemoryFunc *pxa2xx_pcmcia_attr_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_pcmcia_attr_writefn[] = {
pxa2xx_pcmcia_attr_write,
pxa2xx_pcmcia_attr_write,
pxa2xx_pcmcia_attr_write,
};
-static CPUReadMemoryFunc *pxa2xx_pcmcia_io_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_pcmcia_io_readfn[] = {
pxa2xx_pcmcia_io_read,
pxa2xx_pcmcia_io_read,
pxa2xx_pcmcia_io_read,
};
-static CPUWriteMemoryFunc *pxa2xx_pcmcia_io_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_pcmcia_io_writefn[] = {
pxa2xx_pcmcia_io_write,
pxa2xx_pcmcia_io_write,
pxa2xx_pcmcia_io_write,
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index a4d56d8..0a98342 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -229,13 +229,13 @@ static void pxa2xx_pic_cp_write(void *opaque, int op2,
int reg, int crm,
pxa2xx_pic_mem_write(opaque, offset, value);
}
-static CPUReadMemoryFunc *pxa2xx_pic_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_pic_readfn[] = {
pxa2xx_pic_mem_read,
pxa2xx_pic_mem_read,
pxa2xx_pic_mem_read,
};
-static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = {
pxa2xx_pic_mem_write,
pxa2xx_pic_mem_write,
pxa2xx_pic_mem_write,
diff --git a/hw/pxa2xx_timer.c b/hw/pxa2xx_timer.c
index 4d47e4d..154537b 100644
--- a/hw/pxa2xx_timer.c
+++ b/hw/pxa2xx_timer.c
@@ -318,13 +318,13 @@ static void pxa2xx_timer_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *pxa2xx_timer_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
pxa2xx_timer_read,
pxa2xx_timer_read,
pxa2xx_timer_read,
};
-static CPUWriteMemoryFunc *pxa2xx_timer_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
pxa2xx_timer_write,
pxa2xx_timer_write,
pxa2xx_timer_write,
diff --git a/hw/r2d.c b/hw/r2d.c
index 697bcb6..ebcfbe7 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -155,13 +155,13 @@ r2d_fpga_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
}
}
-static CPUReadMemoryFunc *r2d_fpga_readfn[] = {
+static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
r2d_fpga_read,
r2d_fpga_read,
NULL,
};
-static CPUWriteMemoryFunc *r2d_fpga_writefn[] = {
+static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
r2d_fpga_write,
r2d_fpga_write,
NULL,
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 053504b..f4ac83f 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -417,13 +417,13 @@ static void rc4030_writeb(void *opaque,
target_phys_addr_t addr, uint32_t val)
rc4030_writel(opaque, addr & ~0x3, val);
}
-static CPUReadMemoryFunc *rc4030_read[3] = {
+static CPUReadMemoryFunc * const rc4030_read[3] = {
rc4030_readb,
rc4030_readw,
rc4030_readl,
};
-static CPUWriteMemoryFunc *rc4030_write[3] = {
+static CPUWriteMemoryFunc * const rc4030_write[3] = {
rc4030_writeb,
rc4030_writew,
rc4030_writel,
@@ -571,13 +571,13 @@ static void jazzio_writel(void *opaque,
target_phys_addr_t addr, uint32_t val)
jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff);
}
-static CPUReadMemoryFunc *jazzio_read[3] = {
+static CPUReadMemoryFunc * const jazzio_read[3] = {
jazzio_readb,
jazzio_readw,
jazzio_readl,
};
-static CPUWriteMemoryFunc *jazzio_write[3] = {
+static CPUWriteMemoryFunc * const jazzio_write[3] = {
jazzio_writeb,
jazzio_writew,
jazzio_writel,
diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index 089d94c..3dd6ae7 100644
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -39,13 +39,13 @@ static void realview_gic_cpu_write(void *opaque,
target_phys_addr_t offset,
gic_cpu_write(s, gic_get_current_cpu(), offset, value);
}
-static CPUReadMemoryFunc *realview_gic_cpu_readfn[] = {
+static CPUReadMemoryFunc * const realview_gic_cpu_readfn[] = {
realview_gic_cpu_read,
realview_gic_cpu_read,
realview_gic_cpu_read
};
-static CPUWriteMemoryFunc *realview_gic_cpu_writefn[] = {
+static CPUWriteMemoryFunc * const realview_gic_cpu_writefn[] = {
realview_gic_cpu_write,
realview_gic_cpu_write,
realview_gic_cpu_write
diff --git a/hw/rtl8139.c b/hw/rtl8139.c
index fcd6d95..8e15743 100644
--- a/hw/rtl8139.c
+++ b/hw/rtl8139.c
@@ -3353,13 +3353,13 @@ static void rtl8139_ioport_map(PCIDevice *pci_dev, int
region_num,
register_ioport_read( addr, 0x100, 4, rtl8139_ioport_readl, s);
}
-static CPUReadMemoryFunc *rtl8139_mmio_read[3] = {
+static CPUReadMemoryFunc * const rtl8139_mmio_read[3] = {
rtl8139_mmio_readb,
rtl8139_mmio_readw,
rtl8139_mmio_readl,
};
-static CPUWriteMemoryFunc *rtl8139_mmio_write[3] = {
+static CPUWriteMemoryFunc * const rtl8139_mmio_write[3] = {
rtl8139_mmio_writeb,
rtl8139_mmio_writew,
rtl8139_mmio_writel,
diff --git a/hw/sbi.c b/hw/sbi.c
index 3c8e95a..e6ced8b 100644
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -84,13 +84,13 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
}
}
-static CPUReadMemoryFunc *sbi_mem_read[3] = {
+static CPUReadMemoryFunc * const sbi_mem_read[3] = {
NULL,
NULL,
sbi_mem_readl,
};
-static CPUWriteMemoryFunc *sbi_mem_write[3] = {
+static CPUWriteMemoryFunc * const sbi_mem_write[3] = {
NULL,
NULL,
sbi_mem_writel,
diff --git a/hw/serial.c b/hw/serial.c
index bacacea..f5988a5 100644
--- a/hw/serial.c
+++ b/hw/serial.c
@@ -804,13 +804,13 @@ static void serial_mm_writel(void *opaque,
target_phys_addr_t addr,
serial_ioport_write(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc *serial_mm_read[] = {
+static CPUReadMemoryFunc * const serial_mm_read[] = {
&serial_mm_readb,
&serial_mm_readw,
&serial_mm_readl,
};
-static CPUWriteMemoryFunc *serial_mm_write[] = {
+static CPUWriteMemoryFunc * const serial_mm_write[] = {
&serial_mm_writeb,
&serial_mm_writew,
&serial_mm_writel,
diff --git a/hw/sh7750.c b/hw/sh7750.c
index ac1cc01..cf9cf16 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -434,13 +434,13 @@ static void sh7750_mem_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *sh7750_mem_read[] = {
+static CPUReadMemoryFunc * const sh7750_mem_read[] = {
sh7750_mem_readb,
sh7750_mem_readw,
sh7750_mem_readl
};
-static CPUWriteMemoryFunc *sh7750_mem_write[] = {
+static CPUWriteMemoryFunc * const sh7750_mem_write[] = {
sh7750_mem_writeb,
sh7750_mem_writew,
sh7750_mem_writel
@@ -688,13 +688,13 @@ static void sh7750_mmct_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *sh7750_mmct_read[] = {
+static CPUReadMemoryFunc * const sh7750_mmct_read[] = {
invalid_read,
invalid_read,
sh7750_mmct_readl
};
-static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
+static CPUWriteMemoryFunc * const sh7750_mmct_write[] = {
invalid_write,
invalid_write,
sh7750_mmct_writel
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index 9938160..b6f45f0 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -282,13 +282,13 @@ static void sh_intc_write(void *opaque,
target_phys_addr_t offset,
#endif
}
-static CPUReadMemoryFunc *sh_intc_readfn[] = {
+static CPUReadMemoryFunc * const sh_intc_readfn[] = {
sh_intc_read,
sh_intc_read,
sh_intc_read
};
-static CPUWriteMemoryFunc *sh_intc_writefn[] = {
+static CPUWriteMemoryFunc * const sh_intc_writefn[] = {
sh_intc_write,
sh_intc_write,
sh_intc_write
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index 1b148ab..659935f 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -148,8 +148,8 @@ static uint32_t sh_pci_inl (void *p, target_phys_addr_t
addr)
}
typedef struct {
- CPUReadMemoryFunc *r[3];
- CPUWriteMemoryFunc *w[3];
+ CPUReadMemoryFunc * const r[3];
+ CPUWriteMemoryFunc * const w[3];
} MemOp;
static MemOp sh_pci_reg = {
diff --git a/hw/sh_serial.c b/hw/sh_serial.c
index ddf63d5..2447b91 100644
--- a/hw/sh_serial.c
+++ b/hw/sh_serial.c
@@ -351,13 +351,13 @@ static void sh_serial_write (void *opaque,
sh_serial_ioport_write(s, addr, value);
}
-static CPUReadMemoryFunc *sh_serial_readfn[] = {
+static CPUReadMemoryFunc * const sh_serial_readfn[] = {
&sh_serial_read,
&sh_serial_read,
&sh_serial_read,
};
-static CPUWriteMemoryFunc *sh_serial_writefn[] = {
+static CPUWriteMemoryFunc * const sh_serial_writefn[] = {
&sh_serial_write,
&sh_serial_write,
&sh_serial_write,
diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index 5b9c903..fd2146a 100644
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -291,13 +291,13 @@ static void tmu012_write(void *opaque, target_phys_addr_t
offset,
}
}
-static CPUReadMemoryFunc *tmu012_readfn[] = {
+static CPUReadMemoryFunc * const tmu012_readfn[] = {
tmu012_read,
tmu012_read,
tmu012_read
};
-static CPUWriteMemoryFunc *tmu012_writefn[] = {
+static CPUWriteMemoryFunc * const tmu012_writefn[] = {
tmu012_write,
tmu012_write,
tmu012_write
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index c9bad26..7ac1c93 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -134,13 +134,13 @@ static void slavio_intctl_mem_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_intctl_mem_read[3] = {
NULL,
NULL,
slavio_intctl_mem_readl,
};
-static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_intctl_mem_write[3] = {
NULL,
NULL,
slavio_intctl_mem_writel,
@@ -208,13 +208,13 @@ static void slavio_intctlm_mem_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_intctlm_mem_read[3] = {
NULL,
NULL,
slavio_intctlm_mem_readl,
};
-static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_intctlm_mem_write[3] = {
NULL,
NULL,
slavio_intctlm_mem_writel,
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index c8dcd33..4c9337c 100644
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -128,13 +128,13 @@ static uint32_t slavio_cfg_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *slavio_cfg_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
slavio_cfg_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *slavio_cfg_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
slavio_cfg_mem_writeb,
NULL,
NULL,
@@ -159,13 +159,13 @@ static uint32_t slavio_diag_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *slavio_diag_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
slavio_diag_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *slavio_diag_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
slavio_diag_mem_writeb,
NULL,
NULL,
@@ -190,13 +190,13 @@ static uint32_t slavio_mdm_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *slavio_mdm_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
slavio_mdm_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *slavio_mdm_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
slavio_mdm_mem_writeb,
NULL,
NULL,
@@ -230,13 +230,13 @@ static uint32_t slavio_aux1_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
slavio_aux1_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
slavio_aux1_mem_writeb,
NULL,
NULL,
@@ -269,13 +269,13 @@ static uint32_t slavio_aux2_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
slavio_aux2_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
slavio_aux2_mem_writeb,
NULL,
NULL,
@@ -297,13 +297,13 @@ static uint32_t apc_mem_readb(void *opaque,
target_phys_addr_t addr)
return ret;
}
-static CPUReadMemoryFunc *apc_mem_read[3] = {
+static CPUReadMemoryFunc * const apc_mem_read[3] = {
apc_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *apc_mem_write[3] = {
+static CPUWriteMemoryFunc * const apc_mem_write[3] = {
apc_mem_writeb,
NULL,
NULL,
@@ -343,13 +343,13 @@ static void slavio_sysctrl_mem_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
NULL,
NULL,
slavio_sysctrl_mem_readl,
};
-static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
NULL,
NULL,
slavio_sysctrl_mem_writel,
@@ -386,13 +386,13 @@ static void slavio_led_mem_writew(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
NULL,
slavio_led_mem_readw,
NULL,
};
-static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
NULL,
slavio_led_mem_writew,
NULL,
diff --git a/hw/slavio_timer.c b/hw/slavio_timer.c
index 531d6db..08302e0 100644
--- a/hw/slavio_timer.c
+++ b/hw/slavio_timer.c
@@ -336,13 +336,13 @@ static void slavio_timer_mem_writel(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
+static CPUReadMemoryFunc * const slavio_timer_mem_read[3] = {
NULL,
NULL,
slavio_timer_mem_readl,
};
-static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
+static CPUWriteMemoryFunc * const slavio_timer_mem_write[3] = {
NULL,
NULL,
slavio_timer_mem_writel,
diff --git a/hw/sm501.c b/hw/sm501.c
index df40aaa..fc34a99 100644
--- a/hw/sm501.c
+++ b/hw/sm501.c
@@ -626,13 +626,13 @@ static void sm501_system_config_write(void *opaque,
}
}
-static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
+static CPUReadMemoryFunc * const sm501_system_config_readfn[] = {
NULL,
NULL,
&sm501_system_config_read,
};
-static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
+static CPUWriteMemoryFunc * const sm501_system_config_writefn[] = {
NULL,
NULL,
&sm501_system_config_write,
@@ -864,13 +864,13 @@ static void sm501_disp_ctrl_write(void *opaque,
}
}
-static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
+static CPUReadMemoryFunc * const sm501_disp_ctrl_readfn[] = {
NULL,
NULL,
&sm501_disp_ctrl_read,
};
-static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
+static CPUWriteMemoryFunc * const sm501_disp_ctrl_writefn[] = {
NULL,
NULL,
&sm501_disp_ctrl_write,
diff --git a/hw/smc91c111.c b/hw/smc91c111.c
index 5f6956a..fd288d4 100644
--- a/hw/smc91c111.c
+++ b/hw/smc91c111.c
@@ -680,13 +680,13 @@ static ssize_t smc91c111_receive(VLANClientState *vc,
const uint8_t *buf, size_t
return size;
}
-static CPUReadMemoryFunc *smc91c111_readfn[] = {
+static CPUReadMemoryFunc * const smc91c111_readfn[] = {
smc91c111_readb,
smc91c111_readw,
smc91c111_readl
};
-static CPUWriteMemoryFunc *smc91c111_writefn[] = {
+static CPUWriteMemoryFunc * const smc91c111_writefn[] = {
smc91c111_writeb,
smc91c111_writew,
smc91c111_writel
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index 7045453..6b04d24 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -202,13 +202,13 @@ static void dma_mem_writel(void *opaque,
target_phys_addr_t addr, uint32_t val)
s->dmaregs[saddr] = val;
}
-static CPUReadMemoryFunc *dma_mem_read[3] = {
+static CPUReadMemoryFunc * const dma_mem_read[3] = {
NULL,
NULL,
dma_mem_readl,
};
-static CPUWriteMemoryFunc *dma_mem_write[3] = {
+static CPUWriteMemoryFunc * const dma_mem_write[3] = {
NULL,
NULL,
dma_mem_writel,
diff --git a/hw/spitz.c b/hw/spitz.c
index 36bf534..c1d629f 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -156,12 +156,12 @@ static void sl_flash_register(PXA2xxState *cpu, int size)
{
int iomemtype;
SLNANDState *s;
- CPUReadMemoryFunc *sl_readfn[] = {
+ CPUReadMemoryFunc * const sl_readfn[] = {
sl_readb,
sl_readb,
sl_readl,
};
- CPUWriteMemoryFunc *sl_writefn[] = {
+ CPUWriteMemoryFunc * const sl_writefn[] = {
sl_writeb,
sl_writeb,
sl_writeb,
diff --git a/hw/stellaris.c b/hw/stellaris.c
index d9434ca..aa923ef 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -268,13 +268,13 @@ static void gptm_write(void *opaque, target_phys_addr_t
offset, uint32_t value)
gptm_update_irq(s);
}
-static CPUReadMemoryFunc *gptm_readfn[] = {
+static CPUReadMemoryFunc * const gptm_readfn[] = {
gptm_read,
gptm_read,
gptm_read
};
-static CPUWriteMemoryFunc *gptm_writefn[] = {
+static CPUWriteMemoryFunc * const gptm_writefn[] = {
gptm_write,
gptm_write,
gptm_write
@@ -579,13 +579,13 @@ static void ssys_write(void *opaque, target_phys_addr_t
offset, uint32_t value)
ssys_update(s);
}
-static CPUReadMemoryFunc *ssys_readfn[] = {
+static CPUReadMemoryFunc * const ssys_readfn[] = {
ssys_read,
ssys_read,
ssys_read
};
-static CPUWriteMemoryFunc *ssys_writefn[] = {
+static CPUWriteMemoryFunc * const ssys_writefn[] = {
ssys_write,
ssys_write,
ssys_write
@@ -827,13 +827,13 @@ static void stellaris_i2c_reset(stellaris_i2c_state *s)
stellaris_i2c_update(s);
}
-static CPUReadMemoryFunc *stellaris_i2c_readfn[] = {
+static CPUReadMemoryFunc * const stellaris_i2c_readfn[] = {
stellaris_i2c_read,
stellaris_i2c_read,
stellaris_i2c_read
};
-static CPUWriteMemoryFunc *stellaris_i2c_writefn[] = {
+static CPUWriteMemoryFunc * const stellaris_i2c_writefn[] = {
stellaris_i2c_write,
stellaris_i2c_write,
stellaris_i2c_write
@@ -1111,13 +1111,13 @@ static void stellaris_adc_write(void *opaque,
target_phys_addr_t offset,
stellaris_adc_update(s);
}
-static CPUReadMemoryFunc *stellaris_adc_readfn[] = {
+static CPUReadMemoryFunc * const stellaris_adc_readfn[] = {
stellaris_adc_read,
stellaris_adc_read,
stellaris_adc_read
};
-static CPUWriteMemoryFunc *stellaris_adc_writefn[] = {
+static CPUWriteMemoryFunc * const stellaris_adc_writefn[] = {
stellaris_adc_write,
stellaris_adc_write,
stellaris_adc_write
diff --git a/hw/stellaris_enet.c b/hw/stellaris_enet.c
index 43fa305..ae0f099 100644
--- a/hw/stellaris_enet.c
+++ b/hw/stellaris_enet.c
@@ -303,13 +303,13 @@ static void stellaris_enet_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *stellaris_enet_readfn[] = {
+static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
stellaris_enet_read,
stellaris_enet_read,
stellaris_enet_read
};
-static CPUWriteMemoryFunc *stellaris_enet_writefn[] = {
+static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
stellaris_enet_write,
stellaris_enet_write,
stellaris_enet_write
diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
index 76b739c..20c093c 100644
--- a/hw/sun4c_intctl.c
+++ b/hw/sun4c_intctl.c
@@ -82,13 +82,13 @@ static void sun4c_intctl_mem_writeb(void *opaque,
target_phys_addr_t addr,
sun4c_check_interrupts(s);
}
-static CPUReadMemoryFunc *sun4c_intctl_mem_read[3] = {
+static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = {
sun4c_intctl_mem_readb,
NULL,
NULL,
};
-static CPUWriteMemoryFunc *sun4c_intctl_mem_write[3] = {
+static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = {
sun4c_intctl_mem_writeb,
NULL,
NULL,
diff --git a/hw/syborg_fb.c b/hw/syborg_fb.c
index efa5c0e..11d90bf 100644
--- a/hw/syborg_fb.c
+++ b/hw/syborg_fb.c
@@ -445,13 +445,13 @@ static void syborg_fb_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *syborg_fb_readfn[] = {
+static CPUReadMemoryFunc * const syborg_fb_readfn[] = {
syborg_fb_read,
syborg_fb_read,
syborg_fb_read
};
-static CPUWriteMemoryFunc *syborg_fb_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_fb_writefn[] = {
syborg_fb_write,
syborg_fb_write,
syborg_fb_write
diff --git a/hw/syborg_interrupt.c b/hw/syborg_interrupt.c
index 1b44989..ae202c6 100644
--- a/hw/syborg_interrupt.c
+++ b/hw/syborg_interrupt.c
@@ -156,13 +156,13 @@ static void syborg_int_write(void *opaque,
target_phys_addr_t offset, uint32_t v
syborg_int_update(s);
}
-static CPUReadMemoryFunc *syborg_int_readfn[] = {
+static CPUReadMemoryFunc * const syborg_int_readfn[] = {
syborg_int_read,
syborg_int_read,
syborg_int_read
};
-static CPUWriteMemoryFunc *syborg_int_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_int_writefn[] = {
syborg_int_write,
syborg_int_write,
syborg_int_write
diff --git a/hw/syborg_keyboard.c b/hw/syborg_keyboard.c
index deece3c..96f35ce 100644
--- a/hw/syborg_keyboard.c
+++ b/hw/syborg_keyboard.c
@@ -121,13 +121,13 @@ static void syborg_keyboard_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *syborg_keyboard_readfn[] = {
+static CPUReadMemoryFunc * const syborg_keyboard_readfn[] = {
syborg_keyboard_read,
syborg_keyboard_read,
syborg_keyboard_read
};
-static CPUWriteMemoryFunc *syborg_keyboard_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_keyboard_writefn[] = {
syborg_keyboard_write,
syborg_keyboard_write,
syborg_keyboard_write
diff --git a/hw/syborg_pointer.c b/hw/syborg_pointer.c
index 152602a..5bd44f4 100644
--- a/hw/syborg_pointer.c
+++ b/hw/syborg_pointer.c
@@ -110,13 +110,13 @@ static void syborg_pointer_write(void *opaque,
target_phys_addr_t offset,
syborg_pointer_update(s);
}
-static CPUReadMemoryFunc *syborg_pointer_readfn[] = {
+static CPUReadMemoryFunc * const syborg_pointer_readfn[] = {
syborg_pointer_read,
syborg_pointer_read,
syborg_pointer_read
};
-static CPUWriteMemoryFunc *syborg_pointer_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_pointer_writefn[] = {
syborg_pointer_write,
syborg_pointer_write,
syborg_pointer_write
diff --git a/hw/syborg_rtc.c b/hw/syborg_rtc.c
index 48853f7..5fa8653 100644
--- a/hw/syborg_rtc.c
+++ b/hw/syborg_rtc.c
@@ -90,13 +90,13 @@ static void syborg_rtc_write(void *opaque,
target_phys_addr_t offset, uint32_t v
}
}
-static CPUReadMemoryFunc *syborg_rtc_readfn[] = {
+static CPUReadMemoryFunc * const syborg_rtc_readfn[] = {
syborg_rtc_read,
syborg_rtc_read,
syborg_rtc_read
};
-static CPUWriteMemoryFunc *syborg_rtc_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_rtc_writefn[] = {
syborg_rtc_write,
syborg_rtc_write,
syborg_rtc_write
diff --git a/hw/syborg_serial.c b/hw/syborg_serial.c
index f1c6c7e..63f0447 100644
--- a/hw/syborg_serial.c
+++ b/hw/syborg_serial.c
@@ -261,13 +261,13 @@ static void syborg_serial_event(void *opaque, int event)
/* TODO: Report BREAK events? */
}
-static CPUReadMemoryFunc *syborg_serial_readfn[] = {
+static CPUReadMemoryFunc * const syborg_serial_readfn[] = {
syborg_serial_read,
syborg_serial_read,
syborg_serial_read
};
-static CPUWriteMemoryFunc *syborg_serial_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_serial_writefn[] = {
syborg_serial_write,
syborg_serial_write,
syborg_serial_write
diff --git a/hw/syborg_timer.c b/hw/syborg_timer.c
index f64b824..7477a17 100644
--- a/hw/syborg_timer.c
+++ b/hw/syborg_timer.c
@@ -162,13 +162,13 @@ static void syborg_timer_write(void *opaque,
target_phys_addr_t offset,
}
}
-static CPUReadMemoryFunc *syborg_timer_readfn[] = {
+static CPUReadMemoryFunc * const syborg_timer_readfn[] = {
syborg_timer_read,
syborg_timer_read,
syborg_timer_read
};
-static CPUWriteMemoryFunc *syborg_timer_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_timer_writefn[] = {
syborg_timer_write,
syborg_timer_write,
syborg_timer_write
diff --git a/hw/syborg_virtio.c b/hw/syborg_virtio.c
index aed1563..fc45b35 100644
--- a/hw/syborg_virtio.c
+++ b/hw/syborg_virtio.c
@@ -219,13 +219,13 @@ static void syborg_virtio_writeb(void *opaque,
target_phys_addr_t offset,
BADF("Bad byte write offset 0x%x\n", (int)offset);
}
-static CPUReadMemoryFunc *syborg_virtio_readfn[] = {
+static CPUReadMemoryFunc * const syborg_virtio_readfn[] = {
syborg_virtio_readb,
syborg_virtio_readw,
syborg_virtio_readl
};
-static CPUWriteMemoryFunc *syborg_virtio_writefn[] = {
+static CPUWriteMemoryFunc * const syborg_virtio_writefn[] = {
syborg_virtio_writeb,
syborg_virtio_writew,
syborg_virtio_writel
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index 3962d98..e0c5e5f 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -567,12 +567,12 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
{
int iomemtype;
TC6393xbState *s;
- CPUReadMemoryFunc *tc6393xb_readfn[] = {
+ CPUReadMemoryFunc * const tc6393xb_readfn[] = {
tc6393xb_readb,
tc6393xb_readw,
tc6393xb_readl,
};
- CPUWriteMemoryFunc *tc6393xb_writefn[] = {
+ CPUWriteMemoryFunc * const tc6393xb_writefn[] = {
tc6393xb_writeb,
tc6393xb_writew,
tc6393xb_writel,
diff --git a/hw/tcx.c b/hw/tcx.c
index 68dbf02..754751c 100644
--- a/hw/tcx.c
+++ b/hw/tcx.c
@@ -481,13 +481,13 @@ static void tcx_dac_writel(void *opaque,
target_phys_addr_t addr, uint32_t val)
return;
}
-static CPUReadMemoryFunc *tcx_dac_read[3] = {
+static CPUReadMemoryFunc * const tcx_dac_read[3] = {
NULL,
NULL,
tcx_dac_readl,
};
-static CPUWriteMemoryFunc *tcx_dac_write[3] = {
+static CPUWriteMemoryFunc * const tcx_dac_write[3] = {
NULL,
NULL,
tcx_dac_writel,
@@ -503,13 +503,13 @@ static void tcx_dummy_writel(void *opaque,
target_phys_addr_t addr,
{
}
-static CPUReadMemoryFunc *tcx_dummy_read[3] = {
+static CPUReadMemoryFunc * const tcx_dummy_read[3] = {
NULL,
NULL,
tcx_dummy_readl,
};
-static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
+static CPUWriteMemoryFunc * const tcx_dummy_write[3] = {
NULL,
NULL,
tcx_dummy_writel,
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index 3fb0cf7..1ed9d4c 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -286,8 +286,8 @@ static void tusb_gpio_intr_update(TUSBState *s)
/* TODO: How is this signalled? */
}
-extern CPUReadMemoryFunc *musb_read[];
-extern CPUWriteMemoryFunc *musb_write[];
+extern CPUReadMemoryFunc * const musb_read[];
+extern CPUWriteMemoryFunc * const musb_write[];
static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
{
@@ -649,13 +649,13 @@ static void tusb_async_writew(void *opaque,
target_phys_addr_t addr,
}
}
-static CPUReadMemoryFunc *tusb_async_readfn[] = {
+static CPUReadMemoryFunc * const tusb_async_readfn[] = {
tusb_async_readb,
tusb_async_readh,
tusb_async_readw,
};
-static CPUWriteMemoryFunc *tusb_async_writefn[] = {
+static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
tusb_async_writeb,
tusb_async_writeh,
tusb_async_writew,
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index 73944af..908e046 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -71,25 +71,25 @@ static uint32_t pci_unin_main_config_readl (void *opaque,
return val;
}
-static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
+static CPUWriteMemoryFunc * const pci_unin_main_config_write[] = {
&pci_unin_main_config_writel,
&pci_unin_main_config_writel,
&pci_unin_main_config_writel,
};
-static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
+static CPUReadMemoryFunc * const pci_unin_main_config_read[] = {
&pci_unin_main_config_readl,
&pci_unin_main_config_readl,
&pci_unin_main_config_readl,
};
-static CPUWriteMemoryFunc *pci_unin_main_write[] = {
+static CPUWriteMemoryFunc * const pci_unin_main_write[] = {
&pci_host_data_writeb,
&pci_host_data_writew,
&pci_host_data_writel,
};
-static CPUReadMemoryFunc *pci_unin_main_read[] = {
+static CPUReadMemoryFunc * const pci_unin_main_read[] = {
&pci_host_data_readb,
&pci_host_data_readw,
&pci_host_data_readl,
@@ -111,25 +111,25 @@ static uint32_t pci_unin_config_readl (void *opaque,
return s->host_state.config_reg;
}
-static CPUWriteMemoryFunc *pci_unin_config_write[] = {
+static CPUWriteMemoryFunc * const pci_unin_config_write[] = {
&pci_unin_config_writel,
&pci_unin_config_writel,
&pci_unin_config_writel,
};
-static CPUReadMemoryFunc *pci_unin_config_read[] = {
+static CPUReadMemoryFunc * const pci_unin_config_read[] = {
&pci_unin_config_readl,
&pci_unin_config_readl,
&pci_unin_config_readl,
};
-static CPUWriteMemoryFunc *pci_unin_write[] = {
+static CPUWriteMemoryFunc * const pci_unin_write[] = {
&pci_host_data_writeb,
&pci_host_data_writew,
&pci_host_data_writel,
};
-static CPUReadMemoryFunc *pci_unin_read[] = {
+static CPUReadMemoryFunc * const pci_unin_read[] = {
&pci_host_data_readb,
&pci_host_data_readw,
&pci_host_data_readl,
diff --git a/hw/usb-musb.c b/hw/usb-musb.c
index d015d24..664f467 100644
--- a/hw/usb-musb.c
+++ b/hw/usb-musb.c
@@ -1436,13 +1436,13 @@ static void musb_writew(void *opaque,
target_phys_addr_t addr, uint32_t value)
};
}
-CPUReadMemoryFunc *musb_read[] = {
+CPUReadMemoryFunc * const musb_read[] = {
musb_readb,
musb_readh,
musb_readw,
};
-CPUWriteMemoryFunc *musb_write[] = {
+CPUWriteMemoryFunc * const musb_write[] = {
musb_writeb,
musb_writeh,
musb_writew,
diff --git a/hw/usb-ohci.c b/hw/usb-ohci.c
index 4c42ec0..093623f 100644
--- a/hw/usb-ohci.c
+++ b/hw/usb-ohci.c
@@ -1646,14 +1646,14 @@ static void ohci_mem_write(void *ptr,
target_phys_addr_t addr, uint32_t val)
}
/* Only dword reads are defined on OHCI register space */
-static CPUReadMemoryFunc *ohci_readfn[3]={
+static CPUReadMemoryFunc * const ohci_readfn[3]={
ohci_mem_read,
ohci_mem_read,
ohci_mem_read
};
/* Only dword writes are defined on OHCI register space */
-static CPUWriteMemoryFunc *ohci_writefn[3]={
+static CPUWriteMemoryFunc * const ohci_writefn[3]={
ohci_mem_write,
ohci_mem_write,
ohci_mem_write
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index 5eb2625..e36b10f 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -73,13 +73,13 @@ static uint32_t pci_vpb_config_readl (void *opaque,
target_phys_addr_t addr)
return val;
}
-static CPUWriteMemoryFunc *pci_vpb_config_write[] = {
+static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
&pci_vpb_config_writeb,
&pci_vpb_config_writew,
&pci_vpb_config_writel,
};
-static CPUReadMemoryFunc *pci_vpb_config_read[] = {
+static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
&pci_vpb_config_readb,
&pci_vpb_config_readw,
&pci_vpb_config_readl,
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 3371121..27e43d4 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -117,13 +117,13 @@ static void vpb_sic_write(void *opaque,
target_phys_addr_t offset,
vpb_sic_update(s);
}
-static CPUReadMemoryFunc *vpb_sic_readfn[] = {
+static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
vpb_sic_read,
vpb_sic_read,
vpb_sic_read
};
-static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
+static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
vpb_sic_write,
vpb_sic_write,
vpb_sic_write
diff --git a/hw/vga.c b/hw/vga.c
index 3882f20..791d8f5 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -2108,13 +2108,13 @@ static void vga_update_text(void *opaque, console_ch_t
*chardata)
dpy_update(s->ds, 0, 0, s->last_width, height);
}
-static CPUReadMemoryFunc *vga_mem_read[3] = {
+static CPUReadMemoryFunc * const vga_mem_read[3] = {
vga_mem_readb,
vga_mem_readw,
vga_mem_readl,
};
-static CPUWriteMemoryFunc *vga_mem_write[3] = {
+static CPUWriteMemoryFunc * const vga_mem_write[3] = {
vga_mem_writeb,
vga_mem_writew,
vga_mem_writel,
@@ -2401,13 +2401,13 @@ static void vga_mm_writel (void *opaque,
vga_ioport_write(s, addr >> s->it_shift, value);
}
-static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
+static CPUReadMemoryFunc * const vga_mm_read_ctrl[] = {
&vga_mm_readb,
&vga_mm_readw,
&vga_mm_readl,
};
-static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
+static CPUWriteMemoryFunc * const vga_mm_write_ctrl[] = {
&vga_mm_writeb,
&vga_mm_writew,
&vga_mm_writel,
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 5ceebf1..a856059 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1057,13 +1057,13 @@ static void vmsvga_vram_writel(void *opaque,
target_phys_addr_t addr,
*(uint32_t *) (s->vram_ptr + addr) = value;
}
-static CPUReadMemoryFunc *vmsvga_vram_read[] = {
+static CPUReadMemoryFunc * const vmsvga_vram_read[] = {
vmsvga_vram_readb,
vmsvga_vram_readw,
vmsvga_vram_readl,
};
-static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
+static CPUWriteMemoryFunc * const vmsvga_vram_write[] = {
vmsvga_vram_writeb,
vmsvga_vram_writew,
vmsvga_vram_writel,
diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
index 5e9fd7c..6a3bdb4 100644
--- a/hw/wdt_i6300esb.c
+++ b/hw/wdt_i6300esb.c
@@ -351,12 +351,12 @@ static void i6300esb_mem_writel(void *vp,
target_phys_addr_t addr, uint32_t val)
static void i6300esb_map(PCIDevice *dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
- static CPUReadMemoryFunc *mem_read[3] = {
+ static CPUReadMemoryFunc * const mem_read[3] = {
i6300esb_mem_readb,
i6300esb_mem_readw,
i6300esb_mem_readl,
};
- static CPUWriteMemoryFunc *mem_write[3] = {
+ static CPUWriteMemoryFunc * const mem_write[3] = {
i6300esb_mem_writeb,
i6300esb_mem_writew,
i6300esb_mem_writel,
diff --git a/hw/xilinx_ethlite.c b/hw/xilinx_ethlite.c
index f981d10..851b5ae 100644
--- a/hw/xilinx_ethlite.c
+++ b/hw/xilinx_ethlite.c
@@ -152,11 +152,11 @@ eth_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
}
}
-static CPUReadMemoryFunc *eth_read[] = {
+static CPUReadMemoryFunc * const eth_read[] = {
NULL, NULL, ð_readl,
};
-static CPUWriteMemoryFunc *eth_write[] = {
+static CPUWriteMemoryFunc * const eth_write[] = {
NULL, NULL, ð_writel,
};
diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c
index 7fadad5..2ecf962 100644
--- a/hw/xilinx_intc.c
+++ b/hw/xilinx_intc.c
@@ -116,12 +116,12 @@ pic_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
update_irq(p);
}
-static CPUReadMemoryFunc *pic_read[] = {
+static CPUReadMemoryFunc * const pic_read[] = {
NULL, NULL,
&pic_readl,
};
-static CPUWriteMemoryFunc *pic_write[] = {
+static CPUWriteMemoryFunc * const pic_write[] = {
NULL, NULL,
&pic_writel,
};
diff --git a/hw/xilinx_timer.c b/hw/xilinx_timer.c
index 196f011..0c20889 100644
--- a/hw/xilinx_timer.c
+++ b/hw/xilinx_timer.c
@@ -167,12 +167,12 @@ timer_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
timer_update_irq(t);
}
-static CPUReadMemoryFunc *timer_read[] = {
+static CPUReadMemoryFunc * const timer_read[] = {
NULL, NULL,
&timer_readl,
};
-static CPUWriteMemoryFunc *timer_write[] = {
+static CPUWriteMemoryFunc * const timer_write[] = {
NULL, NULL,
&timer_writel,
};
diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index 9bf2e91..175f3ee 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -147,13 +147,13 @@ uart_writel (void *opaque, target_phys_addr_t addr,
uint32_t value)
uart_update_irq(s);
}
-static CPUReadMemoryFunc *uart_read[] = {
+static CPUReadMemoryFunc * const uart_read[] = {
&uart_readl,
&uart_readl,
&uart_readl,
};
-static CPUWriteMemoryFunc *uart_write[] = {
+static CPUWriteMemoryFunc * const uart_write[] = {
&uart_writel,
&uart_writel,
&uart_writel,
diff --git a/hw/zaurus.c b/hw/zaurus.c
index 78a120c..db6ba75 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -142,12 +142,12 @@ static void scoop_writeb(void *opaque, target_phys_addr_t
addr, uint32_t value)
}
}
-static CPUReadMemoryFunc *scoop_readfn[] = {
+static CPUReadMemoryFunc * const scoop_readfn[] = {
scoop_readb,
scoop_readb,
scoop_readb,
};
-static CPUWriteMemoryFunc *scoop_writefn[] = {
+static CPUWriteMemoryFunc * const scoop_writefn[] = {
scoop_writeb,
scoop_writeb,
scoop_writeb,
diff --git a/kqemu.c b/kqemu.c
new file mode 100644
index 0000000..697c55b
--- /dev/null
+++ b/kqemu.c
@@ -0,0 +1,998 @@
+/*
+ * KQEMU support
+ *
+ * Copyright (c) 2005-2008 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "config.h"
+#ifdef _WIN32
+#include <windows.h>
+#include <winioctl.h>
+#else
+#include <sys/types.h>
+#include <sys/mman.h>
+#include <sys/ioctl.h>
+#endif
+#ifdef CONFIG_SOLARIS
+#include <sys/ioccom.h>
+#endif
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+#include <errno.h>
+#include <unistd.h>
+#include <inttypes.h>
+
+#include "cpu.h"
+#include "exec-all.h"
+#include "qemu-common.h"
+
+#ifdef CONFIG_KQEMU
+
+#define DEBUG
+//#define PROFILE
+
+
+#ifdef DEBUG
+# define LOG_INT(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
+# define LOG_INT_STATE(env) log_cpu_state_mask(CPU_LOG_INT, (env), 0)
+#else
+# define LOG_INT(...) do { } while (0)
+# define LOG_INT_STATE(env) do { } while (0)
+#endif
+
+#include <unistd.h>
+#include <fcntl.h>
+#include "kqemu.h"
+
+#ifdef _WIN32
+#define KQEMU_DEVICE "\\\\.\\kqemu"
+#else
+#define KQEMU_DEVICE "/dev/kqemu"
+#endif
+
+static void qpi_init(void);
+
+#ifdef _WIN32
+#define KQEMU_INVALID_FD INVALID_HANDLE_VALUE
+HANDLE kqemu_fd = KQEMU_INVALID_FD;
+#define kqemu_closefd(x) CloseHandle(x)
+#else
+#define KQEMU_INVALID_FD -1
+int kqemu_fd = KQEMU_INVALID_FD;
+#define kqemu_closefd(x) close(x)
+#endif
+
+/* 0 = not allowed
+ 1 = user kqemu
+ 2 = kernel kqemu
+*/
+int kqemu_allowed = 0;
+uint64_t *pages_to_flush;
+unsigned int nb_pages_to_flush;
+uint64_t *ram_pages_to_update;
+unsigned int nb_ram_pages_to_update;
+uint64_t *modified_ram_pages;
+unsigned int nb_modified_ram_pages;
+uint8_t *modified_ram_pages_table;
+int qpi_io_memory;
+uint32_t kqemu_comm_base; /* physical address of the QPI communication page */
+ram_addr_t kqemu_phys_ram_size;
+uint8_t *kqemu_phys_ram_base;
+
+#define cpuid(index, eax, ebx, ecx, edx) \
+ asm volatile ("cpuid" \
+ : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
+ : "0" (index))
+
+#ifdef __x86_64__
+static int is_cpuid_supported(void)
+{
+ return 1;
+}
+#else
+static int is_cpuid_supported(void)
+{
+ int v0, v1;
+ asm volatile ("pushf\n"
+ "popl %0\n"
+ "movl %0, %1\n"
+ "xorl $0x00200000, %0\n"
+ "pushl %0\n"
+ "popf\n"
+ "pushf\n"
+ "popl %0\n"
+ : "=a" (v0), "=d" (v1)
+ :
+ : "cc");
+ return (v0 != v1);
+}
+#endif
+
+static void kqemu_update_cpuid(CPUState *env)
+{
+ int critical_features_mask, features, ext_features, ext_features_mask;
+ uint32_t eax, ebx, ecx, edx;
+
+ /* the following features are kept identical on the host and
+ target cpus because they are important for user code. Strictly
+ speaking, only SSE really matters because the OS must support
+ it if the user code uses it. */
+ critical_features_mask =
+ CPUID_CMOV | CPUID_CX8 |
+ CPUID_FXSR | CPUID_MMX | CPUID_SSE |
+ CPUID_SSE2 | CPUID_SEP;
+ ext_features_mask = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR;
+ if (!is_cpuid_supported()) {
+ features = 0;
+ ext_features = 0;
+ } else {
+ cpuid(1, eax, ebx, ecx, edx);
+ features = edx;
+ ext_features = ecx;
+ }
+#ifdef __x86_64__
+ /* NOTE: on x86_64 CPUs, SYSENTER is not supported in
+ compatibility mode, so in order to have the best performances
+ it is better not to use it */
+ features &= ~CPUID_SEP;
+#endif
+ env->cpuid_features = (env->cpuid_features & ~critical_features_mask) |
+ (features & critical_features_mask);
+ env->cpuid_ext_features = (env->cpuid_ext_features & ~ext_features_mask) |
+ (ext_features & ext_features_mask);
+ /* XXX: we could update more of the target CPUID state so that the
+ non accelerated code sees exactly the same CPU features as the
+ accelerated code */
+}
+
+int kqemu_init(CPUState *env)
+{
+ struct kqemu_init kinit;
+ int ret, version;
+#ifdef _WIN32
+ DWORD temp;
+#endif
+
+ if (!kqemu_allowed)
+ return -1;
+
+#ifdef _WIN32
+ kqemu_fd = CreateFile(KQEMU_DEVICE, GENERIC_WRITE | GENERIC_READ,
+ FILE_SHARE_READ | FILE_SHARE_WRITE,
+ NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL,
+ NULL);
+ if (kqemu_fd == KQEMU_INVALID_FD) {
+ fprintf(stderr, "Could not open '%s' - QEMU acceleration layer not
activated: %lu\n",
+ KQEMU_DEVICE, GetLastError());
+ return -1;
+ }
+#else
+ kqemu_fd = open(KQEMU_DEVICE, O_RDWR);
+ if (kqemu_fd == KQEMU_INVALID_FD) {
+ fprintf(stderr, "Could not open '%s' - QEMU acceleration layer not
activated: %s\n",
+ KQEMU_DEVICE, strerror(errno));
+ return -1;
+ }
+#endif
+ version = 0;
+#ifdef _WIN32
+ DeviceIoControl(kqemu_fd, KQEMU_GET_VERSION, NULL, 0,
+ &version, sizeof(version), &temp, NULL);
+#else
+ ioctl(kqemu_fd, KQEMU_GET_VERSION, &version);
+#endif
+ if (version != KQEMU_VERSION) {
+ fprintf(stderr, "Version mismatch between kqemu module and qemu (%08x
%08x) - disabling kqemu use\n",
+ version, KQEMU_VERSION);
+ goto fail;
+ }
+
+ pages_to_flush = qemu_vmalloc(KQEMU_MAX_PAGES_TO_FLUSH *
+ sizeof(uint64_t));
+ if (!pages_to_flush)
+ goto fail;
+
+ ram_pages_to_update = qemu_vmalloc(KQEMU_MAX_RAM_PAGES_TO_UPDATE *
+ sizeof(uint64_t));
+ if (!ram_pages_to_update)
+ goto fail;
+
+ modified_ram_pages = qemu_vmalloc(KQEMU_MAX_MODIFIED_RAM_PAGES *
+ sizeof(uint64_t));
+ if (!modified_ram_pages)
+ goto fail;
+ modified_ram_pages_table =
+ qemu_mallocz(kqemu_phys_ram_size >> TARGET_PAGE_BITS);
+ if (!modified_ram_pages_table)
+ goto fail;
+
+ memset(&kinit, 0, sizeof(kinit)); /* set the paddings to zero */
+ kinit.ram_base = kqemu_phys_ram_base;
+ kinit.ram_size = kqemu_phys_ram_size;
+ kinit.ram_dirty = phys_ram_dirty;
+ kinit.pages_to_flush = pages_to_flush;
+ kinit.ram_pages_to_update = ram_pages_to_update;
+ kinit.modified_ram_pages = modified_ram_pages;
+#ifdef _WIN32
+ ret = DeviceIoControl(kqemu_fd, KQEMU_INIT, &kinit, sizeof(kinit),
+ NULL, 0, &temp, NULL) == TRUE ? 0 : -1;
+#else
+ ret = ioctl(kqemu_fd, KQEMU_INIT, &kinit);
+#endif
+ if (ret < 0) {
+ fprintf(stderr, "Error %d while initializing QEMU acceleration layer -
disabling it for now\n", ret);
+ fail:
+ kqemu_closefd(kqemu_fd);
+ kqemu_fd = KQEMU_INVALID_FD;
+ return -1;
+ }
+ kqemu_update_cpuid(env);
+ env->kqemu_enabled = kqemu_allowed;
+ nb_pages_to_flush = 0;
+ nb_ram_pages_to_update = 0;
+
+ qpi_init();
+ return 0;
+}
+
+void kqemu_flush_page(CPUState *env, target_ulong addr)
+{
+ LOG_INT("kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
+ if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH)
+ nb_pages_to_flush = KQEMU_FLUSH_ALL;
+ else
+ pages_to_flush[nb_pages_to_flush++] = addr;
+}
+
+void kqemu_flush(CPUState *env, int global)
+{
+ LOG_INT("kqemu_flush:\n");
+ nb_pages_to_flush = KQEMU_FLUSH_ALL;
+}
+
+void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr)
+{
+ LOG_INT("kqemu_set_notdirty: addr=%08lx\n",
+ (unsigned long)ram_addr);
+ /* we only track transitions to dirty state */
+ if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff)
+ return;
+ if (nb_ram_pages_to_update >= KQEMU_MAX_RAM_PAGES_TO_UPDATE)
+ nb_ram_pages_to_update = KQEMU_RAM_PAGES_UPDATE_ALL;
+ else
+ ram_pages_to_update[nb_ram_pages_to_update++] = ram_addr;
+}
+
+static void kqemu_reset_modified_ram_pages(void)
+{
+ int i;
+ unsigned long page_index;
+
+ for(i = 0; i < nb_modified_ram_pages; i++) {
+ page_index = modified_ram_pages[i] >> TARGET_PAGE_BITS;
+ modified_ram_pages_table[page_index] = 0;
+ }
+ nb_modified_ram_pages = 0;
+}
+
+void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr)
+{
+ unsigned long page_index;
+ int ret;
+#ifdef _WIN32
+ DWORD temp;
+#endif
+
+ page_index = ram_addr >> TARGET_PAGE_BITS;
+ if (!modified_ram_pages_table[page_index]) {
+#if 0
+ printf("%d: modify_page=%08lx\n", nb_modified_ram_pages, ram_addr);
+#endif
+ modified_ram_pages_table[page_index] = 1;
+ modified_ram_pages[nb_modified_ram_pages++] = ram_addr;
+ if (nb_modified_ram_pages >= KQEMU_MAX_MODIFIED_RAM_PAGES) {
+ /* flush */
+#ifdef _WIN32
+ ret = DeviceIoControl(kqemu_fd, KQEMU_MODIFY_RAM_PAGES,
+ &nb_modified_ram_pages,
+ sizeof(nb_modified_ram_pages),
+ NULL, 0, &temp, NULL);
+#else
+ ret = ioctl(kqemu_fd, KQEMU_MODIFY_RAM_PAGES,
+ &nb_modified_ram_pages);
+#endif
+ kqemu_reset_modified_ram_pages();
+ }
+ }
+}
+
+void kqemu_set_phys_mem(uint64_t start_addr, ram_addr_t size,
+ ram_addr_t phys_offset)
+{
+ struct kqemu_phys_mem kphys_mem1, *kphys_mem = &kphys_mem1;
+ uint64_t end;
+ int ret, io_index;
+
+ end = (start_addr + size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
+ start_addr &= TARGET_PAGE_MASK;
+ kphys_mem->phys_addr = start_addr;
+ kphys_mem->size = end - start_addr;
+ kphys_mem->ram_addr = phys_offset & TARGET_PAGE_MASK;
+ io_index = phys_offset & ~TARGET_PAGE_MASK;
+ switch(io_index) {
+ case IO_MEM_RAM:
+ kphys_mem->io_index = KQEMU_IO_MEM_RAM;
+ break;
+ case IO_MEM_ROM:
+ kphys_mem->io_index = KQEMU_IO_MEM_ROM;
+ break;
+ default:
+ if (qpi_io_memory == io_index) {
+ kphys_mem->io_index = KQEMU_IO_MEM_COMM;
+ } else {
+ kphys_mem->io_index = KQEMU_IO_MEM_UNASSIGNED;
+ }
+ break;
+ }
+#ifdef _WIN32
+ {
+ DWORD temp;
+ ret = DeviceIoControl(kqemu_fd, KQEMU_SET_PHYS_MEM,
+ kphys_mem, sizeof(*kphys_mem),
+ NULL, 0, &temp, NULL) == TRUE ? 0 : -1;
+ }
+#else
+ ret = ioctl(kqemu_fd, KQEMU_SET_PHYS_MEM, kphys_mem);
+#endif
+ if (ret < 0) {
+ fprintf(stderr, "kqemu: KQEMU_SET_PHYS_PAGE error=%d:
start_addr=0x%016" PRIx64 " size=0x%08lx phys_offset=0x%08lx\n",
+ ret, start_addr,
+ (unsigned long)size, (unsigned long)phys_offset);
+ }
+}
+
+struct fpstate {
+ uint16_t fpuc;
+ uint16_t dummy1;
+ uint16_t fpus;
+ uint16_t dummy2;
+ uint16_t fptag;
+ uint16_t dummy3;
+
+ uint32_t fpip;
+ uint32_t fpcs;
+ uint32_t fpoo;
+ uint32_t fpos;
+ uint8_t fpregs1[8 * 10];
+};
+
+struct fpxstate {
+ uint16_t fpuc;
+ uint16_t fpus;
+ uint16_t fptag;
+ uint16_t fop;
+ uint32_t fpuip;
+ uint16_t cs_sel;
+ uint16_t dummy0;
+ uint32_t fpudp;
+ uint16_t ds_sel;
+ uint16_t dummy1;
+ uint32_t mxcsr;
+ uint32_t mxcsr_mask;
+ uint8_t fpregs1[8 * 16];
+ uint8_t xmm_regs[16 * 16];
+ uint8_t dummy2[96];
+};
+
+static struct fpxstate fpx1 __attribute__((aligned(16)));
+
+static void restore_native_fp_frstor(CPUState *env)
+{
+ int fptag, i, j;
+ struct fpstate fp1, *fp = &fp1;
+
+ fp->fpuc = env->fpuc;
+ fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
+ fptag = 0;
+ for (i=7; i>=0; i--) {
+ fptag <<= 2;
+ if (env->fptags[i]) {
+ fptag |= 3;
+ } else {
+ /* the FPU automatically computes it */
+ }
+ }
+ fp->fptag = fptag;
+ j = env->fpstt;
+ for(i = 0;i < 8; i++) {
+ memcpy(&fp->fpregs1[i * 10], &env->fpregs[j].d, 10);
+ j = (j + 1) & 7;
+ }
+ asm volatile ("frstor %0" : "=m" (*fp));
+}
+
+static void save_native_fp_fsave(CPUState *env)
+{
+ int fptag, i, j;
+ uint16_t fpuc;
+ struct fpstate fp1, *fp = &fp1;
+
+ asm volatile ("fsave %0" : : "m" (*fp));
+ env->fpuc = fp->fpuc;
+ env->fpstt = (fp->fpus >> 11) & 7;
+ env->fpus = fp->fpus & ~0x3800;
+ fptag = fp->fptag;
+ for(i = 0;i < 8; i++) {
+ env->fptags[i] = ((fptag & 3) == 3);
+ fptag >>= 2;
+ }
+ j = env->fpstt;
+ for(i = 0;i < 8; i++) {
+ memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 10], 10);
+ j = (j + 1) & 7;
+ }
+ /* we must restore the default rounding state */
+ fpuc = 0x037f | (env->fpuc & (3 << 10));
+ asm volatile("fldcw %0" : : "m" (fpuc));
+}
+
+static void restore_native_fp_fxrstor(CPUState *env)
+{
+ struct fpxstate *fp = &fpx1;
+ int i, j, fptag;
+
+ fp->fpuc = env->fpuc;
+ fp->fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
+ fptag = 0;
+ for(i = 0; i < 8; i++)
+ fptag |= (env->fptags[i] << i);
+ fp->fptag = fptag ^ 0xff;
+
+ j = env->fpstt;
+ for(i = 0;i < 8; i++) {
+ memcpy(&fp->fpregs1[i * 16], &env->fpregs[j].d, 10);
+ j = (j + 1) & 7;
+ }
+ if (env->cpuid_features & CPUID_SSE) {
+ fp->mxcsr = env->mxcsr;
+ /* XXX: check if DAZ is not available */
+ fp->mxcsr_mask = 0xffff;
+ memcpy(fp->xmm_regs, env->xmm_regs, CPU_NB_REGS * 16);
+ }
+ asm volatile ("fxrstor %0" : "=m" (*fp));
+}
+
+static void save_native_fp_fxsave(CPUState *env)
+{
+ struct fpxstate *fp = &fpx1;
+ int fptag, i, j;
+ uint16_t fpuc;
+
+ asm volatile ("fxsave %0" : : "m" (*fp));
+ env->fpuc = fp->fpuc;
+ env->fpstt = (fp->fpus >> 11) & 7;
+ env->fpus = fp->fpus & ~0x3800;
+ fptag = fp->fptag ^ 0xff;
+ for(i = 0;i < 8; i++) {
+ env->fptags[i] = (fptag >> i) & 1;
+ }
+ j = env->fpstt;
+ for(i = 0;i < 8; i++) {
+ memcpy(&env->fpregs[j].d, &fp->fpregs1[i * 16], 10);
+ j = (j + 1) & 7;
+ }
+ if (env->cpuid_features & CPUID_SSE) {
+ env->mxcsr = fp->mxcsr;
+ memcpy(env->xmm_regs, fp->xmm_regs, CPU_NB_REGS * 16);
+ }
+
+ /* we must restore the default rounding state */
+ asm volatile ("fninit");
+ fpuc = 0x037f | (env->fpuc & (3 << 10));
+ asm volatile("fldcw %0" : : "m" (fpuc));
+}
+
+static int do_syscall(CPUState *env,
+ struct kqemu_cpu_state *kenv)
+{
+ int selector;
+
+ selector = (env->star >> 32) & 0xffff;
+#ifdef TARGET_X86_64
+ if (env->hflags & HF_LMA_MASK) {
+ int code64;
+
+ env->regs[R_ECX] = kenv->next_eip;
+ env->regs[11] = env->eflags;
+
+ code64 = env->hflags & HF_CS64_MASK;
+
+ cpu_x86_set_cpl(env, 0);
+ cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
+ 0, 0xffffffff,
+ DESC_G_MASK | DESC_P_MASK |
+ DESC_S_MASK |
+ DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
DESC_L_MASK);
+ cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
+ 0, 0xffffffff,
+ DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
+ DESC_S_MASK |
+ DESC_W_MASK | DESC_A_MASK);
+ env->eflags &= ~env->fmask;
+ if (code64)
+ env->eip = env->lstar;
+ else
+ env->eip = env->cstar;
+ } else
+#endif
+ {
+ env->regs[R_ECX] = (uint32_t)kenv->next_eip;
+
+ cpu_x86_set_cpl(env, 0);
+ cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
+ 0, 0xffffffff,
+ DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
+ DESC_S_MASK |
+ DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
+ cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
+ 0, 0xffffffff,
+ DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
+ DESC_S_MASK |
+ DESC_W_MASK | DESC_A_MASK);
+ env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
+ env->eip = (uint32_t)env->star;
+ }
+ return 2;
+}
+
+#ifdef CONFIG_PROFILER
+
+#define PC_REC_SIZE 1
+#define PC_REC_HASH_BITS 16
+#define PC_REC_HASH_SIZE (1 << PC_REC_HASH_BITS)
+
+typedef struct PCRecord {
+ unsigned long pc;
+ int64_t count;
+ struct PCRecord *next;
+} PCRecord;
+
+static PCRecord *pc_rec_hash[PC_REC_HASH_SIZE];
+static int nb_pc_records;
+
+static void kqemu_record_pc(unsigned long pc)
+{
+ unsigned long h;
+ PCRecord **pr, *r;
+
+ h = pc / PC_REC_SIZE;
+ h = h ^ (h >> PC_REC_HASH_BITS);
+ h &= (PC_REC_HASH_SIZE - 1);
+ pr = &pc_rec_hash[h];
+ for(;;) {
+ r = *pr;
+ if (r == NULL)
+ break;
+ if (r->pc == pc) {
+ r->count++;
+ return;
+ }
+ pr = &r->next;
+ }
+ r = malloc(sizeof(PCRecord));
+ r->count = 1;
+ r->pc = pc;
+ r->next = NULL;
+ *pr = r;
+ nb_pc_records++;
+}
+
+static int pc_rec_cmp(const void *p1, const void *p2)
+{
+ PCRecord *r1 = *(PCRecord **)p1;
+ PCRecord *r2 = *(PCRecord **)p2;
+ if (r1->count < r2->count)
+ return 1;
+ else if (r1->count == r2->count)
+ return 0;
+ else
+ return -1;
+}
+
+static void kqemu_record_flush(void)
+{
+ PCRecord *r, *r_next;
+ int h;
+
+ for(h = 0; h < PC_REC_HASH_SIZE; h++) {
+ for(r = pc_rec_hash[h]; r != NULL; r = r_next) {
+ r_next = r->next;
+ free(r);
+ }
+ pc_rec_hash[h] = NULL;
+ }
+ nb_pc_records = 0;
+}
+
+void kqemu_record_dump(void)
+{
+ PCRecord **pr, *r;
+ int i, h;
+ FILE *f;
+ int64_t total, sum;
+
+ pr = malloc(sizeof(PCRecord *) * nb_pc_records);
+ i = 0;
+ total = 0;
+ for(h = 0; h < PC_REC_HASH_SIZE; h++) {
+ for(r = pc_rec_hash[h]; r != NULL; r = r->next) {
+ pr[i++] = r;
+ total += r->count;
+ }
+ }
+ qsort(pr, nb_pc_records, sizeof(PCRecord *), pc_rec_cmp);
+
+ f = fopen("/tmp/kqemu.stats", "w");
+ if (!f) {
+ perror("/tmp/kqemu.stats");
+ exit(1);
+ }
+ fprintf(f, "total: %" PRId64 "\n", total);
+ sum = 0;
+ for(i = 0; i < nb_pc_records; i++) {
+ r = pr[i];
+ sum += r->count;
+ fprintf(f, "%08lx: %" PRId64 " %0.2f%% %0.2f%%\n",
+ r->pc,
+ r->count,
+ (double)r->count / (double)total * 100.0,
+ (double)sum / (double)total * 100.0);
+ }
+ fclose(f);
+ free(pr);
+
+ kqemu_record_flush();
+}
+#endif
+
+static inline void kqemu_load_seg(struct kqemu_segment_cache *ksc,
+ const SegmentCache *sc)
+{
+ ksc->selector = sc->selector;
+ ksc->flags = sc->flags;
+ ksc->limit = sc->limit;
+ ksc->base = sc->base;
+}
+
+static inline void kqemu_save_seg(SegmentCache *sc,
+ const struct kqemu_segment_cache *ksc)
+{
+ sc->selector = ksc->selector;
+ sc->flags = ksc->flags;
+ sc->limit = ksc->limit;
+ sc->base = ksc->base;
+}
+
+int kqemu_cpu_exec(CPUState *env)
+{
+ struct kqemu_cpu_state kcpu_state, *kenv = &kcpu_state;
+ int ret, cpl, i;
+#ifdef CONFIG_PROFILER
+ int64_t ti;
+#endif
+#ifdef _WIN32
+ DWORD temp;
+#endif
+
+#ifdef CONFIG_PROFILER
+ ti = profile_getclock();
+#endif
+ LOG_INT("kqemu: cpu_exec: enter\n");
+ LOG_INT_STATE(env);
+ for(i = 0; i < CPU_NB_REGS; i++)
+ kenv->regs[i] = env->regs[i];
+ kenv->eip = env->eip;
+ kenv->eflags = env->eflags;
+ for(i = 0; i < 6; i++)
+ kqemu_load_seg(&kenv->segs[i], &env->segs[i]);
+ kqemu_load_seg(&kenv->ldt, &env->ldt);
+ kqemu_load_seg(&kenv->tr, &env->tr);
+ kqemu_load_seg(&kenv->gdt, &env->gdt);
+ kqemu_load_seg(&kenv->idt, &env->idt);
+ kenv->cr0 = env->cr[0];
+ kenv->cr2 = env->cr[2];
+ kenv->cr3 = env->cr[3];
+ kenv->cr4 = env->cr[4];
+ kenv->a20_mask = env->a20_mask;
+ kenv->efer = env->efer;
+ kenv->tsc_offset = 0;
+ kenv->star = env->star;
+ kenv->sysenter_cs = env->sysenter_cs;
+ kenv->sysenter_esp = env->sysenter_esp;
+ kenv->sysenter_eip = env->sysenter_eip;
+#ifdef TARGET_X86_64
+ kenv->lstar = env->lstar;
+ kenv->cstar = env->cstar;
+ kenv->fmask = env->fmask;
+ kenv->kernelgsbase = env->kernelgsbase;
+#endif
+ if (env->dr[7] & 0xff) {
+ kenv->dr7 = env->dr[7];
+ kenv->dr0 = env->dr[0];
+ kenv->dr1 = env->dr[1];
+ kenv->dr2 = env->dr[2];
+ kenv->dr3 = env->dr[3];
+ } else {
+ kenv->dr7 = 0;
+ }
+ kenv->dr6 = env->dr[6];
+ cpl = (env->hflags & HF_CPL_MASK);
+ kenv->cpl = cpl;
+ kenv->nb_pages_to_flush = nb_pages_to_flush;
+ kenv->user_only = (env->kqemu_enabled == 1);
+ kenv->nb_ram_pages_to_update = nb_ram_pages_to_update;
+ nb_ram_pages_to_update = 0;
+ kenv->nb_modified_ram_pages = nb_modified_ram_pages;
+
+ kqemu_reset_modified_ram_pages();
+
+ if (env->cpuid_features & CPUID_FXSR)
+ restore_native_fp_fxrstor(env);
+ else
+ restore_native_fp_frstor(env);
+
+#ifdef _WIN32
+ if (DeviceIoControl(kqemu_fd, KQEMU_EXEC,
+ kenv, sizeof(struct kqemu_cpu_state),
+ kenv, sizeof(struct kqemu_cpu_state),
+ &temp, NULL)) {
+ ret = kenv->retval;
+ } else {
+ ret = -1;
+ }
+#else
+ ioctl(kqemu_fd, KQEMU_EXEC, kenv);
+ ret = kenv->retval;
+#endif
+ if (env->cpuid_features & CPUID_FXSR)
+ save_native_fp_fxsave(env);
+ else
+ save_native_fp_fsave(env);
+
+ for(i = 0; i < CPU_NB_REGS; i++)
+ env->regs[i] = kenv->regs[i];
+ env->eip = kenv->eip;
+ env->eflags = kenv->eflags;
+ for(i = 0; i < 6; i++)
+ kqemu_save_seg(&env->segs[i], &kenv->segs[i]);
+ cpu_x86_set_cpl(env, kenv->cpl);
+ kqemu_save_seg(&env->ldt, &kenv->ldt);
+ env->cr[0] = kenv->cr0;
+ env->cr[4] = kenv->cr4;
+ env->cr[3] = kenv->cr3;
+ env->cr[2] = kenv->cr2;
+ env->dr[6] = kenv->dr6;
+#ifdef TARGET_X86_64
+ env->kernelgsbase = kenv->kernelgsbase;
+#endif
+
+ /* flush pages as indicated by kqemu */
+ if (kenv->nb_pages_to_flush >= KQEMU_FLUSH_ALL) {
+ tlb_flush(env, 1);
+ } else {
+ for(i = 0; i < kenv->nb_pages_to_flush; i++) {
+ tlb_flush_page(env, pages_to_flush[i]);
+ }
+ }
+ nb_pages_to_flush = 0;
+
+#ifdef CONFIG_PROFILER
+ kqemu_time += profile_getclock() - ti;
+ kqemu_exec_count++;
+#endif
+
+ if (kenv->nb_ram_pages_to_update > 0) {
+ cpu_tlb_update_dirty(env);
+ }
+
+ if (kenv->nb_modified_ram_pages > 0) {
+ for(i = 0; i < kenv->nb_modified_ram_pages; i++) {
+ unsigned long addr;
+ addr = modified_ram_pages[i];
+ tb_invalidate_phys_page_range(addr, addr + TARGET_PAGE_SIZE, 0);
+ }
+ }
+
+ /* restore the hidden flags */
+ {
+ unsigned int new_hflags;
+#ifdef TARGET_X86_64
+ if ((env->hflags & HF_LMA_MASK) &&
+ (env->segs[R_CS].flags & DESC_L_MASK)) {
+ /* long mode */
+ new_hflags = HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
+ } else
+#endif
+ {
+ /* legacy / compatibility case */
+ new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
+ >> (DESC_B_SHIFT - HF_CS32_SHIFT);
+ new_hflags |= (env->segs[R_SS].flags & DESC_B_MASK)
+ >> (DESC_B_SHIFT - HF_SS32_SHIFT);
+ if (!(env->cr[0] & CR0_PE_MASK) ||
+ (env->eflags & VM_MASK) ||
+ !(env->hflags & HF_CS32_MASK)) {
+ /* XXX: try to avoid this test. The problem comes from the
+ fact that is real mode or vm86 mode we only modify the
+ 'base' and 'selector' fields of the segment cache to go
+ faster. A solution may be to force addseg to one in
+ translate-i386.c. */
+ new_hflags |= HF_ADDSEG_MASK;
+ } else {
+ new_hflags |= ((env->segs[R_DS].base |
+ env->segs[R_ES].base |
+ env->segs[R_SS].base) != 0) <<
+ HF_ADDSEG_SHIFT;
+ }
+ }
+ env->hflags = (env->hflags &
+ ~(HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)) |
+ new_hflags;
+ }
+ /* update FPU flags */
+ env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
+ ((env->cr[0] << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK |
HF_TS_MASK));
+ if (env->cr[4] & CR4_OSFXSR_MASK)
+ env->hflags |= HF_OSFXSR_MASK;
+ else
+ env->hflags &= ~HF_OSFXSR_MASK;
+
+ LOG_INT("kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
+ if (ret == KQEMU_RET_SYSCALL) {
+ /* syscall instruction */
+ return do_syscall(env, kenv);
+ } else
+ if ((ret & 0xff00) == KQEMU_RET_INT) {
+ env->exception_index = ret & 0xff;
+ env->error_code = 0;
+ env->exception_is_int = 1;
+ env->exception_next_eip = kenv->next_eip;
+#ifdef CONFIG_PROFILER
+ kqemu_ret_int_count++;
+#endif
+ LOG_INT("kqemu: interrupt v=%02x:\n", env->exception_index);
+ LOG_INT_STATE(env);
+ return 1;
+ } else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) {
+ env->exception_index = ret & 0xff;
+ env->error_code = kenv->error_code;
+ env->exception_is_int = 0;
+ env->exception_next_eip = 0;
+#ifdef CONFIG_PROFILER
+ kqemu_ret_excp_count++;
+#endif
+ LOG_INT("kqemu: exception v=%02x e=%04x:\n",
+ env->exception_index, env->error_code);
+ LOG_INT_STATE(env);
+ return 1;
+ } else if (ret == KQEMU_RET_INTR) {
+#ifdef CONFIG_PROFILER
+ kqemu_ret_intr_count++;
+#endif
+ LOG_INT_STATE(env);
+ return 0;
+ } else if (ret == KQEMU_RET_SOFTMMU) {
+#ifdef CONFIG_PROFILER
+ {
+ unsigned long pc = env->eip + env->segs[R_CS].base;
+ kqemu_record_pc(pc);
+ }
+#endif
+ LOG_INT_STATE(env);
+ return 2;
+ } else {
+ cpu_dump_state(env, stderr, fprintf, 0);
+ fprintf(stderr, "Unsupported return value: 0x%x\n", ret);
+ exit(1);
+ }
+ return 0;
+}
+
+void kqemu_cpu_interrupt(CPUState *env)
+{
+#if defined(_WIN32)
+ /* cancelling the I/O request causes KQEMU to finish executing the
+ current block and successfully returning. */
+ CancelIo(kqemu_fd);
+#endif
+}
+
+/*
+ QEMU paravirtualization interface. The current interface only
+ allows to modify the IF and IOPL flags when running in
+ kqemu.
+
+ At this point it is not very satisfactory. I leave it for reference
+ as it adds little complexity.
+*/
+
+#define QPI_COMM_PAGE_PHYS_ADDR 0xff000000
+
+static uint32_t qpi_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ return 0;
+}
+
+static uint32_t qpi_mem_readw(void *opaque, target_phys_addr_t addr)
+{
+ return 0;
+}
+
+static void qpi_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+}
+
+static void qpi_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+}
+
+static uint32_t qpi_mem_readl(void *opaque, target_phys_addr_t addr)
+{
+ CPUState *env;
+
+ env = cpu_single_env;
+ if (!env)
+ return 0;
+ return env->eflags & (IF_MASK | IOPL_MASK);
+}
+
+/* Note: after writing to this address, the guest code must make sure
+ it is exiting the current TB. pushf/popf can be used for that
+ purpose. */
+static void qpi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ CPUState *env;
+
+ env = cpu_single_env;
+ if (!env)
+ return;
+ env->eflags = (env->eflags & ~(IF_MASK | IOPL_MASK)) |
+ (val & (IF_MASK | IOPL_MASK));
+}
+
+static CPUReadMemoryFunc * const qpi_mem_read[3] = {
+ qpi_mem_readb,
+ qpi_mem_readw,
+ qpi_mem_readl,
+};
+
+static CPUWriteMemoryFunc * const qpi_mem_write[3] = {
+ qpi_mem_writeb,
+ qpi_mem_writew,
+ qpi_mem_writel,
+};
+
+static void qpi_init(void)
+{
+ kqemu_comm_base = 0xff000000 | 1;
+ qpi_io_memory = cpu_register_io_memory(
+ qpi_mem_read,
+ qpi_mem_write, NULL);
+ cpu_register_physical_memory(kqemu_comm_base & ~0xfff,
+ 0x1000, qpi_io_memory);
+}
+#endif
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- [Qemu-commits] [COMMIT d60efc6] Make CPURead/WriteFunc structure 'const',
Anthony Liguori <=