[Qemu-commits] [COMMIT 96db644] Convert addx

[Anthony Liguori]

From: Blue Swirl <address@hidden>

Signed-off-by: Blue Swirl <address@hidden>

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index e0d5aec..6455f95 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -860,6 +860,48 @@ static uint32_t compute_C_add_xcc(void)
 }
 #endif
 
+static uint32_t compute_all_addx(void)
+{
+    uint32_t ret;
+
+    ret = get_NZ_icc(CC_DST);
+    ret |= get_C_add_icc(CC_DST - CC_SRC2, CC_SRC);
+    ret |= get_C_add_icc(CC_DST, CC_SRC);
+    ret |= get_V_add_icc(CC_DST, CC_SRC, CC_SRC2);
+    return ret;
+}
+
+static uint32_t compute_C_addx(void)
+{
+    uint32_t ret;
+
+    ret = get_C_add_icc(CC_DST - CC_SRC2, CC_SRC);
+    ret |= get_C_add_icc(CC_DST, CC_SRC);
+    return ret;
+}
+
+#ifdef TARGET_SPARC64
+static uint32_t compute_all_addx_xcc(void)
+{
+    uint32_t ret;
+
+    ret = get_NZ_xcc(CC_DST);
+    ret |= get_C_add_xcc(CC_DST - CC_SRC2, CC_SRC);
+    ret |= get_C_add_xcc(CC_DST, CC_SRC);
+    ret |= get_V_add_xcc(CC_DST, CC_SRC, CC_SRC2);
+    return ret;
+}
+
+static uint32_t compute_C_addx_xcc(void)
+{
+    uint32_t ret;
+
+    ret = get_C_add_xcc(CC_DST - CC_SRC2, CC_SRC);
+    ret |= get_C_add_xcc(CC_DST, CC_SRC);
+    return ret;
+}
+#endif
+
 typedef struct CCTable {
     uint32_t (*compute_all)(void); /* return all the flags */
     uint32_t (*compute_c)(void);  /* return the C flag */
@@ -869,6 +911,7 @@ static const CCTable icc_table[CC_OP_NB] = {
     /* CC_OP_DYNAMIC should never happen */
     [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
     [CC_OP_ADD] = { compute_all_add, compute_C_add },
+    [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
 };
 
 #ifdef TARGET_SPARC64
@@ -876,6 +919,7 @@ static const CCTable xcc_table[CC_OP_NB] = {
     /* CC_OP_DYNAMIC should never happen */
     [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
     [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
+    [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
 };
 #endif
 
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f7bb15f..bbd6d9d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -475,33 +475,14 @@ static inline void gen_op_add_cc(TCGv dst, TCGv src1, 
TCGv src2)
     tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
-static inline void gen_op_addx_cc2(TCGv dst)
-{
-    gen_cc_NZ_icc(cpu_cc_dst);
-    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-    gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#ifdef TARGET_SPARC64
-    gen_cc_NZ_xcc(cpu_cc_dst);
-    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-    gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
-#endif
-    tcg_gen_mov_tl(dst, cpu_cc_dst);
-}
-
 static inline void gen_op_addxi_cc(TCGv dst, TCGv src1, target_long src2)
 {
     tcg_gen_mov_tl(cpu_cc_src, src1);
     tcg_gen_movi_tl(cpu_cc_src2, src2);
     gen_mov_reg_C(cpu_tmp0, cpu_psr);
     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
-    gen_cc_clear_icc();
-    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
     tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_dst, src2);
-    gen_op_addx_cc2(dst);
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -510,14 +491,8 @@ static inline void gen_op_addx_cc(TCGv dst, TCGv src1, 
TCGv src2)
     tcg_gen_mov_tl(cpu_cc_src2, src2);
     gen_mov_reg_C(cpu_tmp0, cpu_psr);
     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);
-    gen_cc_clear_icc();
-    gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);
-#ifdef TARGET_SPARC64
-    gen_cc_clear_xcc();
-    gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);
-#endif
     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);
-    gen_op_addx_cc2(dst);
+    tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
@@ -3258,8 +3233,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             if (xop & 0x10) {
                                 gen_helper_compute_psr();
                                 gen_op_addxi_cc(cpu_dst, cpu_src1, simm);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+                                dc->cc_op = CC_OP_ADDX;
                             } else {
                                 gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);
@@ -3270,8 +3245,8 @@ static void disas_sparc_insn(DisasContext * dc)
                             if (xop & 0x10) {
                                 gen_helper_compute_psr();
                                 gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
-                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
-                                dc->cc_op = CC_OP_FLAGS;
+                                tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADDX);
+                                dc->cc_op = CC_OP_ADDX;
                             } else {
                                 gen_helper_compute_psr();
                                 gen_mov_reg_C(cpu_tmp0, cpu_psr);