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[Qemu-commits] [COMMIT bcdd07b] Improve instruction name comments for ea
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From: |
Anthony Liguori |
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Subject: |
[Qemu-commits] [COMMIT bcdd07b] Improve instruction name comments for easiersearching |
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Date: |
Sat, 02 May 2009 20:22:34 -0000 |
From: Blue Swirl <address@hidden>
Signed-off-by: Blue Swirl <address@hidden>
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 1968656..438ace4 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2496,7 +2496,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_helper_check_ieee_exceptions();
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0x42:
+ case 0x42: /* faddd */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
@@ -2520,7 +2520,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_helper_check_ieee_exceptions();
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0x46:
+ case 0x46: /* fsubd */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
@@ -2571,7 +2571,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_helper_check_ieee_exceptions();
tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
break;
- case 0x4e:
+ case 0x4e: /* fdivd */
gen_op_load_fpr_DT0(DFPREG(rs1));
gen_op_load_fpr_DT1(DFPREG(rs2));
gen_clear_float_exceptions();
@@ -3136,7 +3136,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1 = get_src1(insn, cpu_src1);
cpu_src2 = get_src2(insn, cpu_src2);
switch (xop & ~0x10) {
- case 0x0:
+ case 0x0: /* add */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10) {
@@ -3152,7 +3152,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
}
break;
- case 0x1:
+ case 0x1: /* and */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
@@ -3163,7 +3163,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_logic_cc(cpu_dst);
}
break;
- case 0x2:
+ case 0x2: /* or */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
@@ -3173,7 +3173,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0x3:
+ case 0x3: /* xor */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
@@ -3183,7 +3183,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0x4:
+ case 0x4: /* sub */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10) {
@@ -3199,7 +3199,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
}
break;
- case 0x5:
+ case 0x5: /* andn */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
@@ -3209,7 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0x6:
+ case 0x6: /* orn */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
@@ -3219,7 +3219,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0x7:
+ case 0x7: /* xorn */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
@@ -3230,7 +3230,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0x8:
+ case 0x8: /* addx, V9 addc */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10)
@@ -3260,19 +3260,19 @@ static void disas_sparc_insn(DisasContext * dc)
}
break;
#endif
- case 0xa:
+ case 0xa: /* umul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0xb:
+ case 0xb: /* smul */
CHECK_IU_FEATURE(dc, MUL);
gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10)
gen_op_logic_cc(cpu_dst);
break;
- case 0xc:
+ case 0xc: /* subx, V9 subc */
if (IS_IMM) {
simm = GET_FIELDs(insn, 19, 31);
if (xop & 0x10) {
@@ -3300,13 +3300,13 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
break;
#endif
- case 0xe:
+ case 0xe: /* udiv */
CHECK_IU_FEATURE(dc, DIV);
gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10)
gen_op_div_cc(cpu_dst);
break;
- case 0xf:
+ case 0xf: /* sdiv */
CHECK_IU_FEATURE(dc, DIV);
gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
if (xop & 0x10)
@@ -4385,19 +4385,19 @@ static void disas_sparc_insn(DisasContext * dc)
(xop > 0x17 && xop <= 0x1d ) ||
(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
switch (xop) {
- case 0x0: /* load unsigned word */
+ case 0x0: /* ld, V9 lduw, load unsigned word */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x1: /* load unsigned byte */
+ case 0x1: /* ldub, load unsigned byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x2: /* load unsigned halfword */
+ case 0x2: /* lduh, load unsigned halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x3: /* load double word */
+ case 0x3: /* ldd, load double word */
if (rd & 1)
goto illegal_insn;
else {
@@ -4417,11 +4417,11 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
}
break;
- case 0x9: /* load signed byte */
+ case 0x9: /* ldsb, load signed byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0xa: /* load signed halfword */
+ case 0xa: /* ldsh, load signed halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
break;
@@ -4436,7 +4436,7 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_temp_free(r_const);
}
break;
- case 0x0f: /* swap register with memory. Also
+ case 0x0f: /* swap, swap register with memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
gen_movl_reg_TN(rd, cpu_val);
@@ -4446,7 +4446,7 @@ static void disas_sparc_insn(DisasContext * dc)
tcg_gen_mov_tl(cpu_val, cpu_tmp0);
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x10: /* load word alternate */
+ case 0x10: /* lda, V9 lduwa, load word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4456,7 +4456,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
break;
- case 0x11: /* load unsigned byte alternate */
+ case 0x11: /* lduba, load unsigned byte alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4466,7 +4466,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
break;
- case 0x12: /* load unsigned halfword alternate */
+ case 0x12: /* lduha, load unsigned halfword alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4476,7 +4476,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
break;
- case 0x13: /* load double word alternate */
+ case 0x13: /* ldda, load double word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4488,7 +4488,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
goto skip_move;
- case 0x19: /* load signed byte alternate */
+ case 0x19: /* ldsba, load signed byte alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4498,7 +4498,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
break;
- case 0x1a: /* load signed halfword alternate */
+ case 0x1a: /* ldsha, load signed halfword alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4518,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_ldstub_asi(cpu_val, cpu_addr, insn);
break;
- case 0x1f: /* swap reg with alt. memory. Also
+ case 0x1f: /* swapa, swap reg with alt. memory. Also
atomically */
CHECK_IU_FEATURE(dc, SWAP);
#ifndef TARGET_SPARC64
@@ -4586,7 +4586,7 @@ static void disas_sparc_insn(DisasContext * dc)
goto jmp_insn;
save_state(dc, cpu_cond);
switch (xop) {
- case 0x20: /* load fpreg */
+ case 0x20: /* ldf, load fpreg */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
@@ -4605,7 +4605,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
#endif
break;
- case 0x22: /* load quad fpreg */
+ case 0x22: /* ldqf, load quad fpreg */
{
TCGv_i32 r_const;
@@ -4616,7 +4616,7 @@ static void disas_sparc_insn(DisasContext * dc)
gen_op_store_QT0_fpr(QFPREG(rd));
}
break;
- case 0x23: /* load double fpreg */
+ case 0x23: /* lddf, load double fpreg */
{
TCGv_i32 r_const;
@@ -4633,19 +4633,19 @@ static void disas_sparc_insn(DisasContext * dc)
xop == 0xe || xop == 0x1e) {
gen_movl_reg_TN(rd, cpu_val);
switch (xop) {
- case 0x4: /* store word */
+ case 0x4: /* st, store word */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x5: /* store byte */
+ case 0x5: /* stb, store byte */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x6: /* store halfword */
+ case 0x6: /* sth, store halfword */
gen_address_mask(dc, cpu_addr);
tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
break;
- case 0x7: /* store double word */
+ case 0x7: /* std, store double word */
if (rd & 1)
goto illegal_insn;
else {
@@ -4662,7 +4662,7 @@ static void disas_sparc_insn(DisasContext * dc)
}
break;
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x14: /* store word alternate */
+ case 0x14: /* sta, V9 stwa, store word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4672,7 +4672,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 4);
break;
- case 0x15: /* store byte alternate */
+ case 0x15: /* stba, store byte alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4682,7 +4682,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 1);
break;
- case 0x16: /* store halfword alternate */
+ case 0x16: /* stha, store halfword alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4692,7 +4692,7 @@ static void disas_sparc_insn(DisasContext * dc)
save_state(dc, cpu_cond);
gen_st_asi(cpu_val, cpu_addr, insn, 2);
break;
- case 0x17: /* store double word alternate */
+ case 0x17: /* stda, store double word alternate */
#ifndef TARGET_SPARC64
if (IS_IMM)
goto illegal_insn;
@@ -4725,7 +4725,7 @@ static void disas_sparc_insn(DisasContext * dc)
goto jmp_insn;
save_state(dc, cpu_cond);
switch (xop) {
- case 0x24: /* store fpreg */
+ case 0x24: /* stf, store fpreg */
gen_address_mask(dc, cpu_addr);
tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
@@ -4768,7 +4768,7 @@ static void disas_sparc_insn(DisasContext * dc)
goto nfq_insn;
#endif
#endif
- case 0x27: /* store double fpreg */
+ case 0x27: /* stdf, store double fpreg */
{
TCGv_i32 r_const;
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Anthony Liguori <=