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[Qemu-commits] [COMMIT 8b88495] sparc64 support TSB related MMU register
From: |
Anthony Liguori |
Subject: |
[Qemu-commits] [COMMIT 8b88495] sparc64 support TSB related MMU registers |
Date: |
Mon, 27 Apr 2009 21:12:25 -0000 |
From: Igor Kovalenko <address@hidden>
Posting updated patch to the list...
>>> On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <address@hidden> wrote:
>>> Â >
>>> Â > Nice, though I didn't notice any visible improvement in my tests.
>>>
>>> This early in boot process there is not much to output; and I test
>>> Â recent kernel which may use different startup sequence.
>>> Â I modified openbios cif handler to output arguments and I now can see
>>> Â visible difference.
>>>
>>>
>>> Â >
>>> Â > About the patch, there are a few problems:
>>> Â > - it breaks Sparc32
>>>
>>> You mean it stops working?
>>
>> Does not even build.
Fixed now.
>>> Â > - commented out code is ugly
>>> Â > - if and else should be on the same line as '{' or '}'
>>> Â > - long lines should be wrapped
>>> Â > - in the line:
>>> Â > + Â Â return (((tag_access_register &
>>> 0x1fff)<<48)|(tag_access_register >> 22));
>>> Â > Â there should be white space between ) and << and 48.
>>> Â >
>>>
>>
>> Also the ")|(" in between is crowded.
>>
>> Maybe the coding style does not describe this well enough.
BTW Supplying indent template would be great.
Please see the updated patch qemu-sparc64-tsb-asi-2.patch attached.
--
Kind regards,
Igor V. Kovalenko
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 947a55a..b434593 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -39,6 +39,56 @@ do { printf("ASI: " fmt , ##args); } while (0)
#endif
#endif
+#ifdef TARGET_SPARC64
+// Calculates TSB pointer value for fault page size 8k or 64k
+static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
+ uint64_t tag_access_register,
+ int page_size)
+{
+ uint64_t tsb_base = tsb_register & ~0x1fffULL;
+ int tsb_split = (env->dmmuregs[5] & 0x1000ULL) ? 1 : 0;
+ int tsb_size = env->dmmuregs[5] & 0xf;
+
+ // discard lower 13 bits which hold tag access context
+ uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
+
+ // now reorder bits
+ uint64_t tsb_base_mask = ~0x1fffULL;
+ uint64_t va = tag_access_va;
+
+ // move va bits to correct position
+ if (page_size == 8*1024) {
+ va >>= 9;
+ } else if (page_size == 64*1024) {
+ va >>= 12;
+ }
+
+ if (tsb_size) {
+ tsb_base_mask <<= tsb_size;
+ }
+
+ // calculate tsb_base mask and adjust va if split is in use
+ if (tsb_split) {
+ if (page_size == 8*1024) {
+ va &= ~(1ULL << (13 + tsb_size));
+ } else if (page_size == 64*1024) {
+ va |= (1ULL << (13 + tsb_size));
+ }
+ tsb_base_mask <<= 1;
+ }
+
+ return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
+}
+
+// Calculates tag target register value by reordering bits
+// in tag access register
+static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
+{
+ return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >>
22);
+}
+
+#endif
+
static inline void address_mask(CPUState *env1, target_ulong *addr)
{
#ifdef TARGET_SPARC64
@@ -1652,13 +1702,31 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int
size, int sign)
{
int reg = (addr >> 3) & 0xf;
- ret = env->immuregs[reg];
+ if (reg == 0) {
+ // I-TSB Tag Target register
+ ret = ultrasparc_tag_target(env->immuregs[6]);
+ } else {
+ ret = env->immuregs[reg];
+ }
+
break;
}
case 0x51: // I-MMU 8k TSB pointer
+ {
+ // env->immuregs[5] holds I-MMU TSB register value
+ // env->immuregs[6] holds I-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
+ 8*1024);
+ break;
+ }
case 0x52: // I-MMU 64k TSB pointer
- // XXX
- break;
+ {
+ // env->immuregs[5] holds I-MMU TSB register value
+ // env->immuregs[6] holds I-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->immuregs[5], env->immuregs[6],
+ 64*1024);
+ break;
+ }
case 0x55: // I-MMU data access
{
int reg = (addr >> 3) & 0x3f;
@@ -1677,7 +1745,28 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int
size, int sign)
{
int reg = (addr >> 3) & 0xf;
- ret = env->dmmuregs[reg];
+ if (reg == 0) {
+ // D-TSB Tag Target register
+ ret = ultrasparc_tag_target(env->dmmuregs[6]);
+ } else {
+ ret = env->dmmuregs[reg];
+ }
+ break;
+ }
+ case 0x59: // D-MMU 8k TSB pointer
+ {
+ // env->dmmuregs[5] holds D-MMU TSB register value
+ // env->dmmuregs[6] holds D-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
+ 8*1024);
+ break;
+ }
+ case 0x5a: // D-MMU 64k TSB pointer
+ {
+ // env->dmmuregs[5] holds D-MMU TSB register value
+ // env->dmmuregs[6] holds D-MMU Tag Access register value
+ ret = ultrasparc_tsb_pointer(env->dmmuregs[5], env->dmmuregs[6],
+ 64*1024);
break;
}
case 0x5d: // D-MMU data access
@@ -1707,8 +1796,6 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int
size, int sign)
case 0x76: // E-cache tag
case 0x7e: // E-cache tag
break;
- case 0x59: // D-MMU 8k TSB pointer
- case 0x5a: // D-MMU 64k TSB pointer
case 0x5b: // D-MMU data pointer
case 0x48: // Interrupt dispatch, RO
case 0x49: // Interrupt data receive
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