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[PATCH v3 6/8] hw/block: m25p80: support quad mode for w25q01jvq
From: |
Jamin Lin |
Subject: |
[PATCH v3 6/8] hw/block: m25p80: support quad mode for w25q01jvq |
Date: |
Thu, 4 Jul 2024 16:29:20 +0800 |
According to the w25q01jv datasheet at page 16,
it is required to set QE bit in "Status Register 2".
Besides, users are able to utilize "Write Status Register 1(0x01)"
command to set QE bit in "Status Register 2" and
utilize "Read Status Register 2(0x35)" command to get the QE bit status.
To support quad mode for w25q01jvq, update collecting data needed
2 bytes for WRSR command in decode_new_cmd function and
verify QE bit at the second byte of collecting data bit 2
in complete_collecting_data.
Update RDCR_EQIO command to set bit 2 of return data
if quad mode enable in decode_new_cmd.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---
hw/block/m25p80.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index 8dec134832..9e99107b42 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -416,6 +416,7 @@ typedef enum {
/*
* Micron: 0x35 - enable QPI
* Spansion: 0x35 - read control register
+ * Winbond: 0x35 - quad enable
*/
RDCR_EQIO = 0x35,
RSTQIO = 0xf5,
@@ -798,6 +799,11 @@ static void complete_collecting_data(Flash *s)
s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
}
break;
+ case MAN_WINBOND:
+ if (s->len > 1) {
+ s->quad_enable = !!(s->data[1] & 0x02);
+ }
+ break;
default:
break;
}
@@ -1254,6 +1260,10 @@ static void decode_new_cmd(Flash *s, uint32_t value)
s->needed_bytes = 2;
s->state = STATE_COLLECTING_VAR_LEN_DATA;
break;
+ case MAN_WINBOND:
+ s->needed_bytes = 2;
+ s->state = STATE_COLLECTING_VAR_LEN_DATA;
+ break;
default:
s->needed_bytes = 1;
s->state = STATE_COLLECTING_DATA;
@@ -1431,6 +1441,12 @@ static void decode_new_cmd(Flash *s, uint32_t value)
case MAN_MACRONIX:
s->quad_enable = true;
break;
+ case MAN_WINBOND:
+ s->data[0] = (!!s->quad_enable) << 1;
+ s->pos = 0;
+ s->len = 1;
+ s->state = STATE_READING_DATA;
+ break;
default:
break;
}
--
2.34.1
- [PATCH v3 1/8] hw/net:ftgmac100: update memory region size to 64KB, (continued)
- [PATCH v3 1/8] hw/net:ftgmac100: update memory region size to 64KB, Jamin Lin, 2024/07/04
- [PATCH v3 2/8] hw/net:ftgmac100: update ring base address to 64 bits, Jamin Lin, 2024/07/04
- [PATCH v3 4/8] hw/net:ftgmac100: update TX and RX packet buffers address to 64 bits, Jamin Lin, 2024/07/04
- [PATCH v3 3/8] hw/net:ftgmac100: introduce TX and RX ring base address high registers to support 64 bits, Jamin Lin, 2024/07/04
- [PATCH v3 5/8] aspeed/soc: set dma64 property for AST2700 ftgmac100, Jamin Lin, 2024/07/04
- [PATCH v3 6/8] hw/block: m25p80: support quad mode for w25q01jvq,
Jamin Lin <=
- [PATCH v3 7/8] machine_aspeed.py: update to test ASPEED OpenBMC SDK v09.02 for AST2700, Jamin Lin, 2024/07/04
- [PATCH v3 8/8] machine_aspeed.py: update to test network for AST2700, Jamin Lin, 2024/07/04
- Re: [PATCH v3 0/8] support AST2700 network, Cédric Le Goater, 2024/07/09