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[PATCH 3/6] tests/tcg/aarch64: Explicitly specify register width
From: |
Akihiko Odaki |
Subject: |
[PATCH 3/6] tests/tcg/aarch64: Explicitly specify register width |
Date: |
Wed, 26 Jun 2024 20:26:24 +0900 |
clang version 18.1.6 assumes a register is 64-bit by default and
complains if a 32-bit value is given. Explicitly specify register width
when passing a 32-bit value.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
tests/tcg/aarch64/bti-1.c | 6 +++---
tests/tcg/aarch64/bti-3.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c
index 99a879af23d4..1fada8108d22 100644
--- a/tests/tcg/aarch64/bti-1.c
+++ b/tests/tcg/aarch64/bti-1.c
@@ -17,15 +17,15 @@ static void skip2_sigill(int sig, siginfo_t *info,
ucontext_t *uc)
#define BTI_JC "hint #38"
#define BTYPE_1(DEST) \
- asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %w0,#0" \
: "=r"(skipped) : : "x16")
#define BTYPE_2(DEST) \
- asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %w0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_3(DEST) \
- asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \
+ asm("mov %w0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %w0,#0" \
: "=r"(skipped) : : "x15")
#define TEST(WHICH, DEST, EXPECT) \
diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c
index 8c534c09d784..6a3bd037bcd6 100644
--- a/tests/tcg/aarch64/bti-3.c
+++ b/tests/tcg/aarch64/bti-3.c
@@ -11,15 +11,15 @@ static void skip2_sigill(int sig, siginfo_t *info,
ucontext_t *uc)
}
#define BTYPE_1() \
- asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; br x16; 1: hint #25; mov %w0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_2() \
- asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \
+ asm("mov %w0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %w0,#0" \
: "=r"(skipped) : : "x16", "x30")
#define BTYPE_3() \
- asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \
+ asm("mov %w0,#1; adr x15, 1f; br x15; 1: hint #25; mov %w0,#0" \
: "=r"(skipped) : : "x15", "x30")
#define TEST(WHICH, EXPECT) \
--
2.45.2
- [PATCH 0/6] tests/tcg/aarch64: Fix inline assemblies for clang, Akihiko Odaki, 2024/06/26
- [PATCH 1/6] tests/tcg/arm: Fix fcvt result messages, Akihiko Odaki, 2024/06/26
- [PATCH 4/6] tests/tcg/aarch64: Fix irg operand type, Akihiko Odaki, 2024/06/26
- [PATCH 2/6] tests/tcg/aarch64: Fix test architecture specification, Akihiko Odaki, 2024/06/26
- [PATCH 3/6] tests/tcg/aarch64: Explicitly specify register width,
Akihiko Odaki <=
- [PATCH 5/6] tests/tcg/aarch64: Do not use x constraint, Akihiko Odaki, 2024/06/26
- [PATCH 6/6] tests/tcg/arm: Manually bit-cast half-precision numbers, Akihiko Odaki, 2024/06/26
- Re: [PATCH 0/6] tests/tcg/aarch64: Fix inline assemblies for clang, Alex Bennée, 2024/06/26