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Re: [PATCH v2 00/67] target/arm: Convert a64 advsimd to decodetree (part
From: |
Peter Maydell |
Subject: |
Re: [PATCH v2 00/67] target/arm: Convert a64 advsimd to decodetree (part 1) |
Date: |
Tue, 28 May 2024 17:20:15 +0100 |
On Sat, 25 May 2024 at 00:22, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> In the process, convert more code to gvec as well -- I will need
> the gvec code for implementing SME2. I guess this is about 1/3
> of the job done, but there's no reason to wait until the patch
> set is completely unwieldy.
>
> Changes for v2:
> * Fix existing RISU failures vs neoverse-n1.
> * Introduce vfp_load_reg16, fixing a regression wrt VNEG (scalar, hp).
> * Fix typo in SUQADD vectorization.
> * Two more conversions.
I've now finished review for this. I pulled 2 and 4-36 into my
target-arm pullreq currently on list. To save you having to
go through a lot of replies that are just me giving r-by tags,
the patches I had comments/questions on are:
3, 38, 44, 46, 50, 65, 66.
thanks
-- PMM
- [PATCH v2 50/67] target/arm: Convert ADD, SUB (vector) to decodetree, (continued)
- [PATCH v2 50/67] target/arm: Convert ADD, SUB (vector) to decodetree, Richard Henderson, 2024/05/24
- [PATCH v2 66/67] target/arm: Convert FMADD, FMSUB, FNMADD, FNMSUB to decodetree, Richard Henderson, 2024/05/24
- [PATCH v2 61/67] target/arm: Convert SABA, SABD, UABA, UABD to decodetree, Richard Henderson, 2024/05/24
- [PATCH v2 65/67] target/arm: Convert SQDMULH, SQRDMULH to decodetree, Richard Henderson, 2024/05/24
- Re: [PATCH v2 00/67] target/arm: Convert a64 advsimd to decodetree (part 1),
Peter Maydell <=