RE: [PATCH v0 2/2] aspeed: fix hardcode boot address 0

[Jamin Lin]

> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, February 5, 2024 9:34 PM
> To: Jamin Lin <jamin_lin@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Andrew Jeffery <andrew@codeconstruct.com.au>;
> Joel Stanley <joel@jms.id.au>; open list:ASPEED BMCs
> <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>
> Subject: Re: [PATCH v0 2/2] aspeed: fix hardcode boot address 0
> 
> On 2/5/24 10:14, Jamin Lin wrote:
> > In the previous design of QEMU model for ASPEED SOCs, it set the boot
> > address at 0 which was the hardcode setting for ast10x0, ast2600,
> > ast2500 and ast2400.
> >
> > According to the design of ast2700, it has bootmcu which is used for
> > executing SPL and initialize DRAM, then, CPUs(cortex-a35) execute
> > u-boot, kernel and rofs. QEMU will only support CPU(coretax-a35) parts
> > and the boot address is "0x400000000" for ast2700.
> 
> On the previous SoC, the ASPEED_DEV_SPI_BOOT region is an alias, at 0x0, to
> the FMC CE0 region, mapped at 0x20000000.
> 
> Is 0x400000000 (or 0x40000000 ?) the address for FMC CE0 region on the
> ast2700 ? or an alias ?
> 
It is "0x4 00000000"(64bits address). CPU is armv8 cortex-a35 which is 64 bits 
CPU. 
The dram base address is "0x4 00000000".
The SPL base address is "0x1 00000000".
FMC_CS0 region mapped at "0x1 00000000" address.

> What is the cortex-a35 reset address ?
> 
> It would help to also introduce a basic skeleton of the ast2700 SoC.
> 
AST2700
Primary Service Processor:
Embedded quad-core ARM Cortex A35 64-bit RISC CPU
Maximum running frequency: 1.6GHZ
Support: MMU, FPU, NEON, trust-zone, GIC-500 controller and so on.

BootMCU:
Ibex-riscv 32bits riscv.

Boot flow
ROM Code -> BootMCU(SPL) -> CPU Cortex A35(U-boot-> kernel -> rofs)

> Anyhow, this change makes sense. Could you please respin and also remove
> ASPEED_SOC_SPI_BOOT_ADDR. ?
> 
Okay, will remove it.

> Thanks,
> 
> C.
> 
> > Therefore, fixed hardcode boot address 0.
> >
> > Signed-off-by: Troy Lee <troy_lee@aspeedtech.com>
> > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> > ---
> >   hw/arm/aspeed.c | 4 +++-
> >   1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index
> > 218b81298e..82a92e8142 100644
> > --- a/hw/arm/aspeed.c
> > +++ b/hw/arm/aspeed.c
> > @@ -289,12 +289,14 @@ static void
> aspeed_install_boot_rom(AspeedMachineState *bmc, BlockBackend *blk,
> >                                       uint64_t rom_size)
> >   {
> >       AspeedSoCState *soc = bmc->soc;
> > +    AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(soc);
> >
> >       memory_region_init_rom(&bmc->boot_rom, NULL,
> "aspeed.boot_rom", rom_size,
> >                              &error_abort);
> >       memory_region_add_subregion_overlap(&soc->spi_boot_container,
> 0,
> >                                           &bmc->boot_rom, 1);
> > -    write_boot_rom(blk, ASPEED_SOC_SPI_BOOT_ADDR, rom_size,
> &error_abort);
> > +    write_boot_rom(blk, sc->memmap[ASPEED_DEV_SPI_BOOT],
> > +                   rom_size, &error_abort);
> >   }
> >
> >   void aspeed_board_init_flashes(AspeedSMCState *s, const char
> > *flashtype,