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[PATCH v5 03/12] target/arm: Add feature detection for FEAT_Pauth2 and e
From: |
Richard Henderson |
Subject: |
[PATCH v5 03/12] target/arm: Add feature detection for FEAT_Pauth2 and extensions |
Date: |
Tue, 29 Aug 2023 16:23:26 -0700 |
From: Aaron Lindsay <aaron@os.amperecomputing.com>
Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5
to distinguish the other architectural algorithm qarma3.
Add ARMPauthFeature and isar_feature_pauth_feature to cover the
other pauth conditions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Message-Id: <20230609172324.982888-3-aaron@os.amperecomputing.com>
[rth: Add ARMPauthFeature and eliminate most other predicates]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 47 +++++++++++++++++++++++++++++------
target/arm/tcg/pauth_helper.c | 2 +-
2 files changed, 40 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4a5a5e9eb8..0e2545d631 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3801,28 +3801,59 @@ static inline bool isar_feature_aa64_fcma(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
}
+/*
+ * These are the values from APA/API/APA3.
+ * In general these must be compared '>=', per the normal Arm ARM
+ * treatment of fields in ID registers.
+ */
+typedef enum {
+ PauthFeat_None = 0,
+ PauthFeat_1 = 1,
+ PauthFeat_EPAC = 2,
+ PauthFeat_2 = 3,
+ PauthFeat_FPAC = 4,
+ PauthFeat_FPACCOMBINED = 5,
+} ARMPauthFeature;
+
+static inline ARMPauthFeature
+isar_feature_pauth_feature(const ARMISARegisters *id)
+{
+ /*
+ * Architecturally, only one of {APA,API,APA3} may be active (non-zero)
+ * and the other two must be zero. Thus we may avoid conditionals.
+ */
+ return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
+ FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
+ FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
+}
+
static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
{
/*
* Return true if any form of pauth is enabled, as this
* predicate controls migration of the 128-bit keys.
*/
- return (id->id_aa64isar1 &
- (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
- FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
- FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
- FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
+ return isar_feature_pauth_feature(id) != PauthFeat_None;
}
-static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id)
+static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
{
/*
- * Return true if pauth is enabled with the architected QARMA algorithm.
- * QEMU will always set APA+GPA to the same value.
+ * Return true if pauth is enabled with the architected QARMA5 algorithm.
+ * QEMU will always enable or disable both APA and GPA.
*/
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
}
+static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
+{
+ /*
+ * Return true if pauth is enabled with the architected QARMA3 algorithm.
+ * QEMU will always enable or disable both APA3 and GPA3.
+ */
+ return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
+}
+
static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c
index 62af569341..6271a84ec9 100644
--- a/target/arm/tcg/pauth_helper.c
+++ b/target/arm/tcg/pauth_helper.c
@@ -282,7 +282,7 @@ static uint64_t pauth_computepac_impdef(uint64_t data,
uint64_t modifier,
static uint64_t pauth_computepac(CPUARMState *env, uint64_t data,
uint64_t modifier, ARMPACKey key)
{
- if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) {
+ if (cpu_isar_feature(aa64_pauth_qarma5, env_archcpu(env))) {
return pauth_computepac_architected(data, modifier, key);
} else {
return pauth_computepac_impdef(data, modifier, key);
--
2.34.1
- [PATCH v5 00/12] Implement Most ARMv8.3 Pointer Authentication Features, Richard Henderson, 2023/08/29
- [PATCH v5 02/12] target/arm: Add ID_AA64ISAR2_EL1, Richard Henderson, 2023/08/29
- [PATCH v5 04/12] target/arm: Don't change pauth features when changing algorithm, Richard Henderson, 2023/08/29
- [PATCH v5 01/12] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC, Richard Henderson, 2023/08/29
- [PATCH v5 03/12] target/arm: Add feature detection for FEAT_Pauth2 and extensions,
Richard Henderson <=
- [PATCH v5 06/12] target/arm: Implement FEAT_EPAC, Richard Henderson, 2023/08/29
- [PATCH v5 05/12] target/arm: Implement FEAT_PACQARMA3, Richard Henderson, 2023/08/29
- [PATCH v5 10/12] linux-user/aarch64: Add ESR signal frame for SIGSEGV, SIGBUS, Richard Henderson, 2023/08/29
- [PATCH v5 07/12] target/arm: Implement FEAT_Pauth2, Richard Henderson, 2023/08/29
- [PATCH v5 09/12] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE, Richard Henderson, 2023/08/29
- [PATCH v5 08/12] targer/arm: Inform helpers whether a PAC instruction is 'combined', Richard Henderson, 2023/08/29
- [PATCH v5 11/12] linux-user/aarch64: Fix normal SIGILL si_code, Richard Henderson, 2023/08/29
- [PATCH v5 12/12] linux-user/aarch64: Add ESR signal frame for PACFAIL, Richard Henderson, 2023/08/29