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[PATCH 09/12] tcg/tcg-op: Add tcg_gen_hrev32_i64() and tcg_gen_hrev_i64(
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 09/12] tcg/tcg-op: Add tcg_gen_hrev32_i64() and tcg_gen_hrev_i64() |
Date: |
Tue, 22 Aug 2023 14:47:28 +0200 |
tcg_gen_hrev32_i64() is similar to tcg_gen_hrev64_i64() but
only modifies the lower 32-bit of a 64-bit value.
tcg_gen_hrev_i64() can be used when we don't know at build
time whether to clear the 32 high bits of the value or not.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
docs/devel/tcg-ops.rst | 4 +++
include/tcg/tcg-op-common.h | 2 ++
include/tcg/tcg-op.h | 2 ++
tcg/tcg-op.c | 49 +++++++++++++++++++++++++++----------
4 files changed, 44 insertions(+), 13 deletions(-)
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst
index e8a2f8aacc..3a8104929c 100644
--- a/docs/devel/tcg-ops.rst
+++ b/docs/devel/tcg-ops.rst
@@ -496,6 +496,10 @@ Misc
- | Byteswap each halfword within a 32/64-bit value.
+ * - hrev32_i64 *t0*, *t1*
+
+ - | Byteswap each halfword on the low bits of a 64-bit value.
+
* - hswap_i32/i64 *t0*, *t1*
- | Swap 16-bit halfwords within a 32/64-bit value.
diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index a9184caf9d..eb327ed964 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -562,7 +562,9 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int
flags);
void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg);
+void tcg_gen_hrev32_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_hrev64_i64(TCGv_i64 ret, TCGv_i64 arg);
+void tcg_gen_hrev_i64(TCGv_i64 ret, TCGv_i64 arg, int is64);
void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index d63683c47b..3ac1d13b19 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -225,6 +225,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
#define tcg_gen_bswap_tl tcg_gen_bswap64_i64
#define tcg_gen_hswap_tl tcg_gen_hswap_i64
#define tcg_gen_wswap_tl tcg_gen_wswap_i64
+#define tcg_gen_hrev32_tl tcg_gen_hrev32_i64
#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
#define tcg_gen_andc_tl tcg_gen_andc_i64
@@ -340,6 +341,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64)
#define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S)
#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
#define tcg_gen_hswap_tl tcg_gen_hswap_i32
+#define tcg_gen_hrev32_tl tcg_gen_hrev32_i32
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
#define tcg_gen_andc_tl tcg_gen_andc_i32
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 310acce410..75892e91ef 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1931,6 +1931,41 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_gen_rotli_i64(ret, arg, 32);
}
+/*
+ * hrev_i64: Byteswap each halfwords within a 64-bit value.
+ * If %is64 is not set, the 32 high bits are zeroed.
+ *
+ * Byte pattern: hrev_i64(xxxxabcd, 0) -> ....badc
+ * hrev_i64(abcdefgh, 1) -> badcfehg
+ */
+void tcg_gen_hrev_i64(TCGv_i64 ret, TCGv_i64 arg, int is64)
+{
+ TCGv_i64 mask = tcg_constant_i64(is64 ? 0x00ff00ff00ff00ffull :
0x00ff00ff);
+ TCGv_i64 t1 = tcg_temp_ebb_new_i64();
+ TCGv_i64 t2 = tcg_temp_ebb_new_i64();
+
+ /* is64=0 is64=1 */
+ /* arg = xxxxabcd abcdefgh */
+ tcg_gen_shri_i64(t1, arg, 8); /* t1 = .xxxxabc .abcdefg */
+ tcg_gen_and_i64(t2, t1, mask); /* t2 = .....a.c .a.c.e.g */
+ tcg_gen_and_i64(t1, arg, mask); /* t1 = .....b.d .b.d.f.h */
+ tcg_gen_shli_i64(t1, t1, 8); /* t1 = ....b.d. b.d.f.h. */
+ tcg_gen_or_i64(ret, t1, t2); /* ret = ....badc badcfehg */
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+/*
+ * hrev32_i64: Byteswap each halfword on the low bits of a 64-bit value.
+ *
+ * Byte pattern: hrev32_i64(xxxxabcd) -> ....badc
+ */
+void tcg_gen_hrev32_i64(TCGv_i64 ret, TCGv_i64 arg)
+{
+ tcg_gen_hrev_i64(ret, arg, false);
+}
+
/*
* hrev64_i64: Byteswap each halfwords within a 64-bit value.
*
@@ -1938,19 +1973,7 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg)
*/
void tcg_gen_hrev64_i64(TCGv_i64 ret, TCGv_i64 arg)
{
- TCGv_i64 mask = tcg_constant_i64(0x00ff00ff00ff00ffull);
- TCGv_i64 t1 = tcg_temp_ebb_new_i64();
- TCGv_i64 t2 = tcg_temp_ebb_new_i64();
-
- /* arg = abcdefgh */
- tcg_gen_shri_i64(t1, arg, 8); /* t1 = .abcdefg */
- tcg_gen_and_i64(t2, t1, mask); /* t2 = .a.c.e.g */
- tcg_gen_and_i64(t1, arg, mask); /* t1 = .b.d.f.h */
- tcg_gen_shli_i64(t1, t1, 8); /* t1 = b.d.f.h. */
- tcg_gen_or_i64(ret, t1, t2); /* ret = badcfehg */
-
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
+ tcg_gen_hrev_i64(ret, arg, true);
}
void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
--
2.41.0
- [PATCH 00/12] tcg: Factor hrev{32,64}_{i32,i64,tl} out, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 01/12] tcg/tcg-op: Factor tcg_gen_hrev32_i32() out, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 02/12] target/arm: Use generic hrev32_i32() in ARM REV16 and VREV16 opcodes, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 03/12] target/cris: Use generic hrev32_i32() in SWAPB opcode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 04/12] target/rx: Use generic hrev32_i32() in REVW opcode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 05/12] tcg/tcg-op: Factor tcg_gen_hrev64_i64() out, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 10/12] target/arm: Use generic hrev_i64() in Aarch64 REV16 opcode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 09/12] tcg/tcg-op: Add tcg_gen_hrev32_i64() and tcg_gen_hrev_i64(),
Philippe Mathieu-Daudé <=
- [PATCH 08/12] target/loongarch: Use generic hrev64_i64() in REVB.4H opcode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 11/12] target/loongarch: Use generic hrev64_i32() in REVB.2H opcode, Philippe Mathieu-Daudé, 2023/08/22
- [PATCH 07/12] target/ppc: Use generic hrev64_i64() in BRH / BSWAP16x8 opcodes, Philippe Mathieu-Daudé, 2023/08/22