[PATCH 1/6] target/arm: Use hswap_i32() in VREV/SMLAD opcodes

[Philippe Mathieu-Daudé]

Commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}")
introduced the generic hswap_i32(). Use it instead of open-coding
it as gen_swap_half().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/arm/tcg/translate-a32.h  | 6 ------
 target/arm/tcg/translate-neon.c | 4 ++--
 target/arm/tcg/translate.c      | 4 ++--
 3 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h
index 48a15379d2..0c8f408eea 100644
--- a/target/arm/tcg/translate-a32.h
+++ b/target/arm/tcg/translate-a32.h
@@ -158,10 +158,4 @@ DO_GEN_ST(32, MO_UL)
 /* Set NZCV flags from the high 4 bits of var.  */
 #define gen_set_nzcv(var) gen_set_cpsr(var, CPSR_NZCV)
 
-/* Swap low and high halfwords.  */
-static inline void gen_swap_half(TCGv_i32 dest, TCGv_i32 var)
-{
-    tcg_gen_rotri_i32(dest, var, 16);
-}
-
 #endif
diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c
index 8de4ceb203..0e59b03ff9 100644
--- a/target/arm/tcg/translate-neon.c
+++ b/target/arm/tcg/translate-neon.c
@@ -2906,7 +2906,7 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64 *a)
                 tcg_gen_bswap32_i32(tmp[half], tmp[half]);
                 break;
             case 1:
-                gen_swap_half(tmp[half], tmp[half]);
+                tcg_gen_hswap_i32(tmp[half], tmp[half]);
                 break;
             case 2:
                 break;
@@ -3516,7 +3516,7 @@ static bool trans_VREV32(DisasContext *s, arg_2misc *a)
 {
     static NeonGenOneOpFn * const fn[] = {
         tcg_gen_bswap32_i32,
-        gen_swap_half,
+        tcg_gen_hswap_i32,
         NULL,
         NULL,
     };
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 1a6938d1b3..39a42611c6 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -7612,7 +7612,7 @@ static bool op_smlad(DisasContext *s, arg_rrrr *a, bool 
m_swap, bool sub)
     t1 = load_reg(s, a->rn);
     t2 = load_reg(s, a->rm);
     if (m_swap) {
-        gen_swap_half(t2, t2);
+        tcg_gen_hswap_i32(t2, t2);
     }
     gen_smul_dual(t1, t2);
 
@@ -7700,7 +7700,7 @@ static bool op_smlald(DisasContext *s, arg_rrrr *a, bool 
m_swap, bool sub)
     t1 = load_reg(s, a->rn);
     t2 = load_reg(s, a->rm);
     if (m_swap) {
-        gen_swap_half(t2, t2);
+        tcg_gen_hswap_i32(t2, t2);
     }
     gen_smul_dual(t1, t2);
 
-- 
2.41.0