As far as I know, the order issue is caused by nested device realization. In this case, realizing TYPE_DESIGNWARE_PCIE_HOST will also realize TYPE_DESIGNWARE_PCIE_ROOT(see designware_pcie_host_realize()). device_set_realized() is the function that realizing a device must go through, and this function first realizes the device by dc->realize() and then realizes the device's child bus by qbus_realize(). Whether there is any child bus of the device may depend on dc->realize(). The realization flow will be like a recursive call to device_set_realized(). More precisely, the flow in this case is: qdev_realize() --> ... --> FIRST device_set_realized() --> FIRST dc->realize() --> ... --> designware_pcie_host_realize() --> qdev_realize() --> ... --> SECOND device_set_realized() --> SECOND dc->realize() --> ... --> designware_pcie_root_realize() --> ...--> back to the SECOND device_set_realized() --> SECOND qbus_realize() the CHILD bus "dw-pcie" --> ... --> back to the FIRST device_set_realized() --> FIRST qbus_realize() the PARENT bus "pcie".
I also found this
patch that solves the same bus issue.
Do you have any suggestions on the order of realization? Thanks!