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[PATCH v5 16/20] target/arm: Use get_phys_addr_with_struct for stage2
From: |
Richard Henderson |
Subject: |
[PATCH v5 16/20] target/arm: Use get_phys_addr_with_struct for stage2 |
Date: |
Tue, 20 Jun 2023 14:44:14 +0200 |
This fixes a bug in which we failed to initialize
the result attributes properly after the memset.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 558b4b731b..7c4526e2da 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -39,10 +39,6 @@ typedef struct S1Translate {
void *out_host;
} S1Translate;
-static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
- uint64_t address, MMUAccessType access_type,
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi);
-
static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw,
target_ulong address,
MMUAccessType access_type,
@@ -2886,12 +2882,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,
S1Translate *ptw,
cacheattrs1 = result->cacheattrs;
memset(result, 0, sizeof(*result));
- if (arm_feature(env, ARM_FEATURE_PMSA)) {
- ret = get_phys_addr_pmsav8(env, ipa, access_type,
- ptw->in_mmu_idx, is_secure, result, fi);
- } else {
- ret = get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi);
- }
+ ret = get_phys_addr_with_struct(env, ptw, ipa, access_type, result, fi);
fi->s2addr = ipa;
/* Combine the S1 and S2 perms. */
--
2.34.1
- [PATCH v5 05/20] target/arm: Introduce ARMSecuritySpace, (continued)
- [PATCH v5 05/20] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/06/20
- [PATCH v5 06/20] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/06/20
- [PATCH v5 07/20] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/06/20
- [PATCH v5 08/20] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/06/20
- [PATCH v5 09/20] target/arm: Remove __attribute__((nonnull)) from ptw.c, Richard Henderson, 2023/06/20
- [PATCH v5 10/20] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/06/20
- [PATCH v5 11/20] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/06/20
- [PATCH v5 13/20] target/arm: Handle no-execute for Realm and Root regimes, Richard Henderson, 2023/06/20
- [PATCH v5 14/20] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate, Richard Henderson, 2023/06/20
- [PATCH v5 15/20] target/arm: Move s1_is_el0 into S1Translate, Richard Henderson, 2023/06/20
- [PATCH v5 16/20] target/arm: Use get_phys_addr_with_struct for stage2,
Richard Henderson <=
- [PATCH v5 12/20] target/arm: Handle Block and Page bits for security space, Richard Henderson, 2023/06/20
- [PATCH v5 17/20] target/arm: Add GPC syndrome, Richard Henderson, 2023/06/20
- [PATCH v5 18/20] target/arm: Implement GPC exceptions, Richard Henderson, 2023/06/20
- [PATCH v5 19/20] target/arm: Implement the granule protection check, Richard Henderson, 2023/06/20
- [PATCH v5 20/20] target/arm: Add cpu properties for enabling FEAT_RME, Richard Henderson, 2023/06/20
- Re: [PATCH v5 00/20] target/arm: Implement FEAT_RME, Peter Maydell, 2023/06/20