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[PATCH 00/20] target/arm: Convert exception, system, loads and stores to
From: |
Peter Maydell |
Subject: |
[PATCH 00/20] target/arm: Convert exception, system, loads and stores to decodetree |
Date: |
Fri, 2 Jun 2023 16:52:03 +0100 |
This patchseries does more of the conversion of the A64 decoder to
decodetree. It covers the exception-generation, system, load and
store instructions.
After this the remaining legacy decoder pieces are:
* data-processing (register)
* data-processing (SIMD)
* data-processing (floating-point)
I plan to take a break from conversion after this series to work on
FEAT_MOPS, but want to come back to the dp-register parts for this
release cycle. The FP/SIMD stuff is a bigger job and I'm inclined to
leave it for the moment.
I include the LDSMIN/LDSMAX bugfix as patch 1 to avoid a conflict
later. Speaking of conflicts, this is going to conflict with RTH's
LSE2 series, which I expect to get in to the tree first, but I'm
hoping the rebase of this series won't be too painful.
thanks
-- PMM
Peter Maydell (20):
target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics
target/arm: Convert hint instruction space to decodetree
target/arm: Convert barrier insns to decodetree
target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree
target/arm: Convert MSR (immediate) to decodetree
target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree
target/arm: Convert exception generation instructions to decodetree
target/arm: Convert load/store exclusive and ordered to decodetree
target/arm: Convert LDXP, STXP, CASP, CAS to decodetree
target/arm: Convert load reg (literal) group to decodetree
target/arm: Convert load/store-pair to decodetree
target/arm: Convert ld/st reg+imm9 insns to decodetree
target/arm: Convert LDR/STR with 12-bit immediate to decodetree
target/arm: Convert LDR/STR reg+reg to decodetree
target/arm: Convert atomic memory ops to decodetree
target/arm: Convert load (pointer auth) insns to decodetree
target/arm: Convert LDAPR/STLR (imm) to decodetree
target/arm: Convert load/store (multiple structures) to decodetree
target/arm: Convert load/store single structure to decodetree
target/arm: Convert load/store tags insns to decodetree
target/arm/tcg/a64.decode | 406 ++++
target/arm/tcg/translate-a64.c | 3183 ++++++++++++++------------------
2 files changed, 1801 insertions(+), 1788 deletions(-)
--
2.34.1
- [PATCH 00/20] target/arm: Convert exception, system, loads and stores to decodetree,
Peter Maydell <=
- [PATCH 02/20] target/arm: Convert hint instruction space to decodetree, Peter Maydell, 2023/06/02
- [PATCH 01/20] target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics, Peter Maydell, 2023/06/02
- [PATCH 03/20] target/arm: Convert barrier insns to decodetree, Peter Maydell, 2023/06/02
- [PATCH 04/20] target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree, Peter Maydell, 2023/06/02
- [PATCH 05/20] target/arm: Convert MSR (immediate) to decodetree, Peter Maydell, 2023/06/02