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[PATCH v3 12/57] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st}
From: |
Richard Henderson |
Subject: |
[PATCH v3 12/57] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st} |
Date: |
Mon, 24 Apr 2023 06:40:20 +0100 |
Rename the 'ext' parameter 'data_type' to make the use clearer;
pass it to tcg_out_qemu_st as well to even out the interfaces.
Rename the 'otype' local 'addr_type' to make the use clearer.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 36 +++++++++++++++++-------------------
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 4ec3cf3172..ecbf6564fc 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1851,22 +1851,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp
memop,
}
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- MemOpIdx oi, TCGType ext)
+ MemOpIdx oi, TCGType data_type)
{
MemOp memop = get_memop(oi);
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+ TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
/* Byte swapping is left to middle-end expansion. */
tcg_debug_assert((memop & MO_BSWAP) == 0);
#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
- tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- TCG_REG_X1, otype, addr_reg);
- add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
+ tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 1);
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
+ TCG_REG_X1, addr_type, addr_reg);
+ add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
unsigned a_bits = get_alignment_bits(memop);
@@ -1874,33 +1873,32 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg
data_reg, TCGReg addr_reg,
tcg_out_test_alignment(s, true, addr_reg, a_bits);
}
if (USE_GUEST_BASE) {
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- TCG_REG_GUEST_BASE, otype, addr_reg);
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
+ TCG_REG_GUEST_BASE, addr_type, addr_reg);
} else {
- tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
+ tcg_out_qemu_ld_direct(s, memop, data_type, data_reg,
addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
}
#endif /* CONFIG_SOFTMMU */
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- MemOpIdx oi)
+ MemOpIdx oi, TCGType data_type)
{
MemOp memop = get_memop(oi);
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+ TCGType addr_type = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
/* Byte swapping is left to middle-end expansion. */
tcg_debug_assert((memop & MO_BSWAP) == 0);
#ifdef CONFIG_SOFTMMU
- unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
- tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
+ tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, get_mmuidx(oi), 0);
tcg_out_qemu_st_direct(s, memop, data_reg,
- TCG_REG_X1, otype, addr_reg);
- add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
- data_reg, addr_reg, s->code_ptr, label_ptr);
+ TCG_REG_X1, addr_type, addr_reg);
+ add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
+ s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
unsigned a_bits = get_alignment_bits(memop);
if (a_bits) {
@@ -1908,7 +1906,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg
data_reg, TCGReg addr_reg,
}
if (USE_GUEST_BASE) {
tcg_out_qemu_st_direct(s, memop, data_reg,
- TCG_REG_GUEST_BASE, otype, addr_reg);
+ TCG_REG_GUEST_BASE, addr_type, addr_reg);
} else {
tcg_out_qemu_st_direct(s, memop, data_reg,
addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
@@ -2249,7 +2247,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, REG0(0), a1, a2);
+ tcg_out_qemu_st(s, REG0(0), a1, a2, ext);
break;
case INDEX_op_bswap64_i64:
--
2.34.1
- [PATCH v3 15/57] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}, (continued)
- [PATCH v3 15/57] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/04/24
- [PATCH v3 13/57] tcg/aarch64: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 08/57] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load, Richard Henderson, 2023/04/24
- [PATCH v3 17/57] tcg/arm: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 37/57] tcg: Widen helper_*_st[bw]_mmu val arguments, Richard Henderson, 2023/04/24
- [PATCH v3 19/57] tcg/loongarch64: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 16/57] tcg/arm: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 12/57] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st},
Richard Henderson <=
- [PATCH v3 14/57] tcg/aarch64: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 18/57] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st}, Richard Henderson, 2023/04/24
- [PATCH v3 22/57] tcg/mips: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 23/57] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/04/24
- [PATCH v3 21/57] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/04/24
- [PATCH v3 20/57] tcg/loongarch64: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 25/57] tcg/ppc: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 24/57] tcg/ppc: Introduce HostAddress, Richard Henderson, 2023/04/24