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Re: [PATCH 2/2] target/arm: Add DynamIQ Shared Unit control registers
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH 2/2] target/arm: Add DynamIQ Shared Unit control registers |
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Date: |
Mon, 6 Mar 2023 12:32:14 +0000 |
On Fri, 3 Mar 2023 at 16:16, Chen Baozi <chenbaozi@phytium.com.cn> wrote:
>
> DynamIQ Shared Unit (DSU) contains system control registers in the SCU
> and L3 logic which are implemented as the system registers for the cores
> in the cluster. Add DSU control registers and enable it to the supported
> cores.
>
> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
This looks OK if we need it, but as I mentioned in my comments
on patch 1, I'd like to see if we can avoid having to have it...
thanks
-- PMM